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GET /api/patches/134982/?format=api
{ "id": 134982, "url": "http://patches.dpdk.org/api/patches/134982/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231210012455.20229-3-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231210012455.20229-3-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231210012455.20229-3-ajit.khaparde@broadcom.com", "date": "2023-12-10T01:24:43", "name": "[v2,02/14] net/bnxt: update HWRM API", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "392847bccc6c874d80c723f7b34b1a7919d139fc", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231210012455.20229-3-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 30499, "url": "http://patches.dpdk.org/api/series/30499/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30499", "date": "2023-12-10T01:24:41", "name": "support new 5760X P7 devices", "version": 2, "mbox": "http://patches.dpdk.org/series/30499/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134982/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/134982/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B8775436BE;\n\tSun, 10 Dec 2023 02:32:06 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8EABB406B7;\n\tSun, 10 Dec 2023 02:31:48 +0100 (CET)", "from mail-ot1-f47.google.com (mail-ot1-f47.google.com\n [209.85.210.47]) by mails.dpdk.org (Postfix) with ESMTP id 4AB7D402EA\n for <dev@dpdk.org>; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1702171903; x=1702776703;\n h=mime-version:references:in-reply-to:message-id:date:subject:to:from\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=E4J2mCvgNwTRM3AwU7HyXCn2DyYsWWwumtYtLP7QQTU=;\n b=ue4i4+LShWJX6YbVJBO5w2J70qjaEe9fBzgdmNZ5FuP0/G8RhTbL6waOiiF8wLg3l3\n e/U2LUaRjwvDJRvtAztkBV5FAda3ZgXllbgC3PsRh1epop1rT9GlVwORDWnqvMi98dha\n Wzzo/8Oe/N89L7wQ7ZGS1R1LPhj8P+WC4iVqO5OByXe2fPtOEpmegnG9OD3hGzMNsStZ\n UmXPX8662jaQKqS1xFmjuHNVKTbsDn6faSD0nTrUV3ENetAOd96MI8A7w2C/B9C1nHtA\n Bb2Bmrof45DrTDFx2mwunoTkjrI+zZDbdFOdYszsJxxvY/D20fV3aiJLwnAu5zGFFuHf\n RxMg==", "X-Gm-Message-State": "AOJu0YzeP5d+aFgANm423hSoVwyrFlDWXPmObc1UHBgv57LGRO8976ic\n tv0aHOcJcm8naOn8k8I6I3v0QbUpxEla5r2GDwDgHxtotN32X45xsm1S0OXwhlm8v/pMTZ1HHxt\n QY/jPMmpoqZzcvDYsGtptSa79qT93DZe3Yf8wMx1kcmrrrFJDV4GNV9iRvPy+peSo+qqE", "X-Google-Smtp-Source": "\n AGHT+IHXzSTH3sb6zXGnAPvgcEalmXxV8aWbLVvhlA4w35ZdiQi5FzhzSex+IrmAhDUnVEfJM3myXw==", "X-Received": "by 2002:a05:6808:6549:b0:3b8:b063:ae06 with SMTP id\n fn9-20020a056808654900b003b8b063ae06mr2816146oib.99.1702171902225;\n Sat, 09 Dec 2023 17:31:42 -0800 (PST)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Subject": "[PATCH v2 02/14] net/bnxt: update HWRM API", "Date": "Sat, 9 Dec 2023 17:24:43 -0800", "Message-Id": "<20231210012455.20229-3-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)", "In-Reply-To": "<20231210012455.20229-1-ajit.khaparde@broadcom.com>", "References": "<20231210012455.20229-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"000000000000ae0660060c1dc72e\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update HWRM API to version 1.10.2.158\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt_hwrm.c | 3 -\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 1531 ++++++++++++++++++++++--\n 2 files changed, 1429 insertions(+), 105 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 06f196760f..0a31b984e6 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -5175,9 +5175,6 @@ int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,\n \tif (enables &\n \t HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)\n \t\treq.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);\n-\tif (enables &\n-\t HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)\n-\t\treq.mirror_vnic_id = filter->mirror_vnic_id;\n \n \treq.enables = rte_cpu_to_le_32(enables);\n \ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 9afdd056ce..65f3f0576b 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -1154,8 +1154,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 2\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 138\n-#define HWRM_VERSION_STR \"1.10.2.138\"\n+#define HWRM_VERSION_RSVD 158\n+#define HWRM_VERSION_STR \"1.10.2.158\"\n \n /****************\n * hwrm_ver_get *\n@@ -6329,19 +6329,14 @@ struct rx_pkt_v3_cmpl_hi {\n \t#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \\\n \t\t(UINT32_C(0x5) << 9)\n \t/*\n-\t * Indicates that the IP checksum failed its check in the tunnel\n+\t * Indicates that the physical packet is shorter than that claimed\n+\t * by the tunnel header length. Valid for GTPv1-U packets.\n \t * header.\n \t */\n-\t#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \\\n+\t#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR \\\n \t\t(UINT32_C(0x6) << 9)\n-\t/*\n-\t * Indicates that the L4 checksum failed its check in the tunnel\n-\t * header.\n-\t */\n-\t#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \\\n-\t\t(UINT32_C(0x7) << 9)\n \t#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \\\n-\t\tRX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR\n+\t\tRX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR\n \t/*\n \t * This indicates that there was an error in the inner\n \t * portion of the packet when this\n@@ -6406,20 +6401,8 @@ struct rx_pkt_v3_cmpl_hi {\n \t */\n \t#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \\\n \t\t(UINT32_C(0x8) << 12)\n-\t/*\n-\t * Indicates that the IP checksum failed its check in the\n-\t * inner header.\n-\t */\n-\t#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \\\n-\t\t(UINT32_C(0x9) << 12)\n-\t/*\n-\t * Indicates that the L4 checksum failed its check in the\n-\t * inner header.\n-\t */\n-\t#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \\\n-\t\t(UINT32_C(0xa) << 12)\n \t#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST \\\n-\t\tRX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR\n+\t\tRX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN\n \t/*\n \t * This is data from the CFA block as indicated by the meta_format\n \t * field.\n@@ -14157,7 +14140,7 @@ struct hwrm_func_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcaps_output (size:896b/112B) */\n+/* hwrm_func_qcaps_output (size:1088b/136B) */\n struct hwrm_func_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -14840,9 +14823,85 @@ struct hwrm_func_qcaps_output {\n \t/*\n \t * When this bit is '1', it indicates that the hardware based\n \t * link aggregation group (L2 and RoCE) feature is supported.\n+\t * This LAG feature is only supported on the THOR2 or newer NIC\n+\t * with multiple ports.\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \\\n \t\tUINT32_C(0x400)\n+\t/*\n+\t * When this bit is '1', it indicates all contexts can be stored\n+\t * on chip instead of using host based backing store memory.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When this bit is '1', it indicates that the HW supports\n+\t * using a steering tag in the memory transactions targeting\n+\t * L2 or RoCE ring resources.\n+\t * Steering Tags are system-specific values that must follow the\n+\t * encoding requirements of the hardware platform. On devices that\n+\t * support steering to multiple address domains, a value of 0 in\n+\t * bit 0 of the steering tag specifies the address is associated\n+\t * with the SOC address space, and a value of 1 indicates the\n+\t * address is associated with the host address space.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * When this bit is '1', it indicates that driver can enable\n+\t * support for an enhanced VF scale.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting partition based XID management for KTLS/QUIC\n+\t * Tx/Rx Key Context types.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This bit is only valid on the condition that both\n+\t * “ktls_supported” and “quic_supported” flags are set. When this\n+\t * bit is valid, it conveys information below:\n+\t * 1. If it is set to ‘1’, it indicates that the firmware allows the\n+\t * driver to run KTLS and QUIC concurrently;\n+\t * 2. If it is cleared to ‘0’, it indicates that the driver has to\n+\t * make sure all crypto connections on all functions are of the\n+\t * same type, i.e., either KTLS or QUIC.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * When this bit is '1', it indicates that the device supports\n+\t * setting a cross TC cap on a scheduler queue.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * When this bit is '1', it indicates that the device supports\n+\t * setting a per TC cap on a scheduler queue.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED \\\n+\t\tUINT32_C(0x20000)\n+\t/*\n+\t * When this bit is '1', it indicates that the device supports\n+\t * setting a per TC reservation on a scheduler queues.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED \\\n+\t\tUINT32_C(0x40000)\n+\t/*\n+\t * When this bit is '1', it indicates that firmware supports query\n+\t * for statistics related to invalid doorbell errors and drops.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x80000)\n+\t/*\n+\t * When this bit is '1', it indicates that the device supports\n+\t * VF RoCE resource management.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED \\\n+\t\tUINT32_C(0x100000)\n \tuint16_t\ttunnel_disable_flag;\n \t/*\n \t * When this bit is '1', it indicates that the VXLAN parsing\n@@ -14892,7 +14951,35 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \\\n \t\tUINT32_C(0x80)\n-\tuint8_t\tunused_1[2];\n+\tuint16_t\txid_partition_cap;\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting partition based XID management for KTLS TX\n+\t * key contexts.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_KTLS_TKC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting partition based XID management for KTLS RX\n+\t * key contexts.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_KTLS_RKC \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting partition based XID management for QUIC TX\n+\t * key contexts.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_QUIC_TKC \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting partition based XID management for QUIC RX\n+\t * key contexts.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_QUIC_RKC \\\n+\t\tUINT32_C(0x8)\n \t/*\n \t * This value uniquely identifies the hardware NIC used by the\n \t * function. The value returned will be the same for all functions.\n@@ -14901,7 +14988,55 @@ struct hwrm_func_qcaps_output {\n \t * PCIe Capability Device Serial Number.\n \t */\n \tuint8_t\tdevice_serial_number[8];\n-\tuint8_t\tunused_2[7];\n+\t/*\n+\t * This field is only valid in the XID partition mode. It indicates\n+\t * the number contexts per partition.\n+\t */\n+\tuint16_t\tctxs_per_partition;\n+\tuint8_t\tunused_2[2];\n+\t/*\n+\t * The maximum number of address vectors that may be allocated across\n+\t * all VFs for the function. This is valid only on the PF with VF RoCE\n+\t * (SR-IOV) enabled. Returns zero if this command is called on a PF\n+\t * with VF RoCE (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_av;\n+\t/*\n+\t * The maximum number of completion queues that may be allocated across\n+\t * all VFs for the function. This is valid only on the PF with VF RoCE\n+\t * (SR-IOV) enabled. Returns zero if this command is called on a PF\n+\t * with VF RoCE (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_cq;\n+\t/*\n+\t * The maximum number of memory regions plus memory windows that may be\n+\t * allocated across all VFs for the function. This is valid only on the\n+\t * PF with VF RoCE (SR-IOV) enabled. Returns zero if this command is\n+\t * called on a PF with VF RoCE (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_mrw;\n+\t/*\n+\t * The maximum number of queue pairs that may be allocated across\n+\t * all VFs for the function. This is valid only on the PF with VF RoCE\n+\t * (SR-IOV) enabled. Returns zero if this command is called on a PF\n+\t * with VF RoCE (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_qp;\n+\t/*\n+\t * The maximum number of shared receive queues that may be allocated\n+\t * across all VFs for the function. This is valid only on the PF with\n+\t * VF RoCE (SR-IOV) enabled. Returns zero if this command is called on\n+\t * a PF with VF RoCE (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_srq;\n+\t/*\n+\t * The maximum number of GIDs that may be allocated across all VFs for\n+\t * the function. This is valid only on the PF with VF RoCE (SR-IOV)\n+\t * enabled. Returns zero if this command is called on a PF with VF RoCE\n+\t * (SR-IOV) disabled or on a VF.\n+\t */\n+\tuint32_t\troce_vf_max_gid;\n+\tuint8_t\tunused_3[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14959,7 +15094,7 @@ struct hwrm_func_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcfg_output (size:1024b/128B) */\n+/* hwrm_func_qcfg_output (size:1280b/160B) */\n struct hwrm_func_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -15604,11 +15739,68 @@ struct hwrm_func_qcfg_output {\n \t */\n \tuint16_t\tport_kdnet_fid;\n \tuint8_t\tunused_5[2];\n-\t/* Number of Tx Key Contexts allocated. */\n-\tuint32_t\talloc_tx_key_ctxs;\n-\t/* Number of Rx Key Contexts allocated. */\n-\tuint32_t\talloc_rx_key_ctxs;\n-\tuint8_t\tunused_6[7];\n+\t/* Number of KTLS Tx Key Contexts allocated. */\n+\tuint32_t\tnum_ktls_tx_key_ctxs;\n+\t/* Number of KTLS Rx Key Contexts allocated. */\n+\tuint32_t\tnum_ktls_rx_key_ctxs;\n+\t/*\n+\t * The LAG idx of this function. The lag_id is per port and the\n+\t * valid lag_id is from 0 to 7, if there is no valid lag_id,\n+\t * 0xff will be returned.\n+\t * This HW lag id is used for Truflow programming only.\n+\t */\n+\tuint8_t\tlag_id;\n+\t/* Partition interface for this function. */\n+\tuint8_t\tparif;\n+\t/*\n+\t * The LAG ID of a hardware link aggregation group (LAG) whose\n+\t * member ports include the port of this function. The LAG was\n+\t * previously created using HWRM_FUNC_LAG_CREATE. If the port of this\n+\t * function is not a member of any LAG, the fw_lag_id will be 0xff.\n+\t */\n+\tuint8_t\tfw_lag_id;\n+\tuint8_t\tunused_6;\n+\t/* Number of QUIC Tx Key Contexts allocated. */\n+\tuint32_t\tnum_quic_tx_key_ctxs;\n+\t/* Number of QUIC Rx Key Contexts allocated. */\n+\tuint32_t\tnum_quic_rx_key_ctxs;\n+\t/*\n+\t * Number of AVs per VF. Only valid for PF. This field is ignored\n+\t * when the flag, l2_vf_resource_mgmt, is not set in RoCE\n+\t * initialize_fw.\n+\t */\n+\tuint32_t\troce_max_av_per_vf;\n+\t/*\n+\t * Number of CQs per VF. Only valid for PF. This field is ignored when\n+\t * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw.\n+\t */\n+\tuint32_t\troce_max_cq_per_vf;\n+\t/*\n+\t * Number of MR/MWs per VF. Only valid for PF. This field is ignored\n+\t * when the flag, l2_vf_resource_mgmt, is not set in RoCE\n+\t * initialize_fw.\n+\t */\n+\tuint32_t\troce_max_mrw_per_vf;\n+\t/*\n+\t * Number of QPs per VF. Only valid for PF. This field is ignored when\n+\t * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw.\n+\t */\n+\tuint32_t\troce_max_qp_per_vf;\n+\t/*\n+\t * Number of SRQs per VF. Only valid for PF. This field is ignored\n+\t * when the flag, l2_vf_resource_mgmt, is not set in RoCE\n+\t * initialize_fw.\n+\t */\n+\tuint32_t\troce_max_srq_per_vf;\n+\t/*\n+\t * Number of GIDs per VF. Only valid for PF. This field is ignored\n+\t * when the flag, l2_vf_resource_mgmt, is not set in RoCE\n+\t * initialize_fw.\n+\t */\n+\tuint32_t\troce_max_gid_per_vf;\n+\t/* Bitmap of context types that have XID partition enabled. */\n+\tuint16_t\txid_partition_cfg;\n+\tuint8_t\tunused_7;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -15624,7 +15816,7 @@ struct hwrm_func_qcfg_output {\n *****************/\n \n \n-/* hwrm_func_cfg_input (size:1024b/128B) */\n+/* hwrm_func_cfg_input (size:1280b/160B) */\n struct hwrm_func_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -15888,15 +16080,6 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \\\n \t\tUINT32_C(0x40000000)\n-\t/*\n-\t * If this bit is set to 1, the driver is requesting FW to see if\n-\t * all the assets requested in this command (i.e. number of KTLS/\n-\t * QUIC key contexts) are available. The firmware will return an\n-\t * error if the requested assets are not available. The firmware\n-\t * will NOT reserve the assets if they are available.\n-\t */\n-\t#define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \\\n-\t\tUINT32_C(0x80000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the admin_mtu field to be\n@@ -16080,16 +16263,16 @@ struct hwrm_func_cfg_input {\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \\\n \t\tUINT32_C(0x20000000)\n \t/*\n-\t * This bit must be '1' for the number of Tx Key Contexts\n-\t * field to be configured.\n+\t * This bit must be '1' for the num_ktls_tx_key_ctxs field to be\n+\t * configured.\n \t */\n-\t#define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \\\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS \\\n \t\tUINT32_C(0x40000000)\n \t/*\n-\t * This bit must be '1' for the number of Rx Key Contexts\n-\t * field to be configured.\n+\t * This bit must be '1' for the num_ktls_rx_key_ctxs field to be\n+\t * configured.\n \t */\n-\t#define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \\\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS \\\n \t\tUINT32_C(0x80000000)\n \t/*\n \t * This field can be used by the admin PF to configure\n@@ -16542,19 +16725,93 @@ struct hwrm_func_cfg_input {\n \t * ring that is assigned to a function has a valid mtu.\n \t */\n \tuint16_t\thost_mtu;\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tflags2;\n+\t/*\n+\t * If this bit is set to 1, the driver is requesting the firmware\n+\t * to see if the assets (i.e., the number of KTLS key contexts)\n+\t * requested in this command are available. The firmware will return\n+\t * an error if the requested assets are not available. The firmware\n+\t * will NOT reserve the assets if they are available.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If this bit is set to 1, the driver is requesting the firmware\n+\t * to see if the assets (i.e., the number of QUIC key contexts)\n+\t * requested in this command are available. The firmware will return\n+\t * an error if the requested assets are not available. The firmware\n+\t * will NOT reserve the assets if they are available.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST \\\n+\t\tUINT32_C(0x2)\n \tuint32_t\tenables2;\n \t/*\n \t * This bit must be '1' for the kdnet_mode field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET \\\n+\t\tUINT32_C(0x1)\n \t/*\n \t * This bit must be '1' for the db_page_size field to be\n \t * configured. Legacy controller core FW may silently ignore\n \t * the db_page_size programming request through this command.\n \t */\n-\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the num_quic_tx_key_ctxs field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the num_quic_rx_key_ctxs field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the roce_max_av_per_vf field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the roce_max_cq_per_vf field to be\n+\t * configured. Only valid for PF.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the roce_max_mrw_per_vf field to be\n+\t * configured. Only valid for PF.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the roce_max_qp_per_vf field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the roce_max_srq_per_vf field to be\n+\t * configured. Only valid for PF.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the roce_max_gid_per_vf field to be\n+\t * configured. Only valid for PF.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the xid_partition_cfg field to be\n+\t * configured. Only valid for PF.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG \\\n+\t\tUINT32_C(0x400)\n \t/*\n \t * KDNet mode for the port for this function. If NPAR is\n \t * also configured on this port, it takes precedence. KDNet\n@@ -16602,11 +16859,56 @@ struct hwrm_func_cfg_input {\n \t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \\\n \t\tHWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB\n \tuint8_t\tunused_1[2];\n-\t/* Number of Tx Key Contexts requested. */\n-\tuint32_t\tnum_tx_key_ctxs;\n-\t/* Number of Rx Key Contexts requested. */\n-\tuint32_t\tnum_rx_key_ctxs;\n-\tuint8_t\tunused_2[4];\n+\t/* Number of KTLS Tx Key Contexts requested. */\n+\tuint32_t\tnum_ktls_tx_key_ctxs;\n+\t/* Number of KTLS Rx Key Contexts requested. */\n+\tuint32_t\tnum_ktls_rx_key_ctxs;\n+\t/* Number of QUIC Tx Key Contexts requested. */\n+\tuint32_t\tnum_quic_tx_key_ctxs;\n+\t/* Number of QUIC Rx Key Contexts requested. */\n+\tuint32_t\tnum_quic_rx_key_ctxs;\n+\t/* Number of AVs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_av_per_vf;\n+\t/* Number of CQs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_cq_per_vf;\n+\t/* Number of MR/MWs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_mrw_per_vf;\n+\t/* Number of QPs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_qp_per_vf;\n+\t/* Number of SRQs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_srq_per_vf;\n+\t/* Number of GIDs per VF. Only valid for PF. */\n+\tuint32_t\troce_max_gid_per_vf;\n+\t/*\n+\t * Bitmap of context kinds that have XID partition enabled.\n+\t * Only valid for PF.\n+\t */\n+\tuint16_t\txid_partition_cfg;\n+\t/*\n+\t * When this bit is '1', it indicates that driver enables XID\n+\t * partition on KTLS TX key contexts.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_KTLS_TKC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that driver enables XID\n+\t * partition on KTLS RX key contexts.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_KTLS_RKC \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that driver enables XID\n+\t * partition on QUIC TX key contexts.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_QUIC_TKC \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates that driver enables XID\n+\t * partition on QUIC RX key contexts.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_QUIC_RKC \\\n+\t\tUINT32_C(0x8)\n+\tuint16_t\tunused_2;\n } __rte_packed;\n \n /* hwrm_func_cfg_output (size:128b/16B) */\n@@ -22466,8 +22768,14 @@ struct hwrm_func_backing_store_cfg_v2_input {\n \t * which means \"0\" indicates the first instance. For backing\n \t * stores with single instance only, leave this field to 0.\n \t * 1. If the backing store type is MPC TQM ring, use the following\n-\t * instance value to MPC client mapping:\n+\t * instance value to map to MPC clients:\n \t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n+\t * 2. If the backing store type is TBL_SCOPE, use the following\n+\t * instance value to map to table scope regions:\n+\t * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)\n+\t * 3. If the backing store type is XID partition, use the following\n+\t * instance value to map to context types:\n+\t * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3)\n \t */\n \tuint16_t\tinstance;\n \t/* Control flags. */\n@@ -22578,7 +22886,8 @@ struct hwrm_func_backing_store_cfg_v2_input {\n \t * | SRQ | srq_split_entries |\n \t * | CQ | cq_split_entries |\n \t * | VINC | vnic_split_entries |\n-\t * | MRAV | marv_split_entries |\n+\t * | MRAV | mrav_split_entries |\n+\t * | TS | ts_split_entries |\n \t */\n \tuint32_t\tsplit_entry_0;\n \t/* Split entry #1. */\n@@ -22711,6 +23020,15 @@ struct hwrm_func_backing_store_qcfg_v2_input {\n \t * Instance of the backing store type. It is zero-based,\n \t * which means \"0\" indicates the first instance. For backing\n \t * stores with single instance only, leave this field to 0.\n+\t * 1. If the backing store type is MPC TQM ring, use the following\n+\t * instance value to map to MPC clients:\n+\t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n+\t * 2. If the backing store type is TBL_SCOPE, use the following\n+\t * instance value to map to table scope regions:\n+\t * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)\n+\t * 3. If the backing store type is XID partition, use the following\n+\t * instance value to map to context types:\n+\t * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3)\n \t */\n \tuint16_t\tinstance;\n \tuint8_t\trsvd[4];\n@@ -22779,6 +23097,15 @@ struct hwrm_func_backing_store_qcfg_v2_output {\n \t * Instance of the backing store type. It is zero-based,\n \t * which means \"0\" indicates the first instance. For backing\n \t * stores with single instance only, leave this field to 0.\n+\t * 1. If the backing store type is MPC TQM ring, use the following\n+\t * instance value to map to MPC clients:\n+\t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n+\t * 2. If the backing store type is TBL_SCOPE, use the following\n+\t * instance value to map to table scope regions:\n+\t * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)\n+\t * 3. If the backing store type is XID partition, use the following\n+\t * instance value to map to context types:\n+\t * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3)\n \t */\n \tuint16_t\tinstance;\n \t/* Control flags. */\n@@ -22855,7 +23182,8 @@ struct hwrm_func_backing_store_qcfg_v2_output {\n \t * | SRQ | srq_split_entries |\n \t * | CQ | cq_split_entries |\n \t * | VINC | vnic_split_entries |\n-\t * | MRAV | marv_split_entries |\n+\t * | MRAV | mrav_split_entries |\n+\t * | TS | ts_split_entries |\n \t */\n \tuint32_t\tsplit_entry_0;\n \t/* Split entry #1. */\n@@ -22876,17 +23204,20 @@ struct hwrm_func_backing_store_qcfg_v2_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n /* qpc_split_entries (size:128b/16B) */\n struct qpc_split_entries {\n \t/* Number of L2 QP backing store entries. */\n \tuint32_t\tqp_num_l2_entries;\n \t/* Number of QP1 entries. */\n \tuint32_t\tqp_num_qp1_entries;\n-\tuint32_t\trsvd[2];\n+\t/*\n+\t * Number of RoCE QP context entries required for this\n+\t * function to support fast QP modify destroy feature.\n+\t */\n+\tuint32_t\tqp_num_fast_qpmd_entries;\n+\tuint32_t\trsvd;\n } __rte_packed;\n \n-/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n /* srq_split_entries (size:128b/16B) */\n struct srq_split_entries {\n \t/* Number of L2 SRQ backing store entries. */\n@@ -22895,7 +23226,6 @@ struct srq_split_entries {\n \tuint32_t\trsvd2[2];\n } __rte_packed;\n \n-/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n /* cq_split_entries (size:128b/16B) */\n struct cq_split_entries {\n \t/* Number of L2 CQ backing store entries. */\n@@ -22904,7 +23234,6 @@ struct cq_split_entries {\n \tuint32_t\trsvd2[2];\n } __rte_packed;\n \n-/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n /* vnic_split_entries (size:128b/16B) */\n struct vnic_split_entries {\n \t/* Number of VNIC backing store entries. */\n@@ -22913,7 +23242,6 @@ struct vnic_split_entries {\n \tuint32_t\trsvd2[2];\n } __rte_packed;\n \n-/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n /* mrav_split_entries (size:128b/16B) */\n struct mrav_split_entries {\n \t/* Number of AV backing store entries. */\n@@ -22922,6 +23250,21 @@ struct mrav_split_entries {\n \tuint32_t\trsvd2[2];\n } __rte_packed;\n \n+/* ts_split_entries (size:128b/16B) */\n+struct ts_split_entries {\n+\t/* Max number of TBL_SCOPE region entries (QCAPS). */\n+\tuint32_t\tregion_num_entries;\n+\t/* tsid to configure (CFG). */\n+\tuint8_t\ttsid;\n+\t/*\n+\t * Lkup static bucket count (power of 2).\n+\t * Array is indexed by enum cfa_dir\n+\t */\n+\tuint8_t\tlkup_static_bkt_cnt_exp[2];\n+\tuint8_t\trsvd;\n+\tuint32_t\trsvd2[2];\n+} __rte_packed;\n+\n /************************************\n * hwrm_func_backing_store_qcaps_v2 *\n ************************************/\n@@ -23112,12 +23455,36 @@ struct hwrm_func_backing_store_qcaps_v2_output {\n \t */\n \t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * When set, it indicates the support of the following capability\n+\t * that is specific to the QP type:\n+\t * - For 2-port adapters, the ability to extend the RoCE QP\n+\t * entries configured on a PF, during some network events such as\n+\t * Link Down. These additional entries count is included in the\n+\t * advertised 'max_num_entries'.\n+\t * - The count of RoCE QP entries, derived from 'max_num_entries'\n+\t * (max_num_entries - qp_num_qp1_entries - qp_num_l2_entries -\n+\t * qp_num_fast_qpmd_entries, note qp_num_fast_qpmd_entries is\n+\t * always zero when QPs are pseudo-statically allocated), includes\n+\t * the count of QPs that can be migrated from the other PF (e.g.,\n+\t * during network link down). Therefore, during normal operation\n+\t * when both PFs are active, the supported number of RoCE QPs for\n+\t * each of the PF is half of the advertised value.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC \\\n+\t\tUINT32_C(0x8)\n \t/*\n \t * Bit map of the valid instances associated with the\n \t * backing store type.\n \t * 1. If the backing store type is MPC TQM ring, use the following\n-\t * bit to MPC client mapping:\n+\t * bits to map to MPC clients:\n \t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n+\t * 2. If the backing store type is TBL_SCOPE, use the following\n+\t * bits to map to table scope regions:\n+\t * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)\n+\t * 3. If the backing store type is VF XID partition in-use table, use\n+\t * the following bits to map to context types:\n+\t * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3)\n \t */\n \tuint32_t\tinstance_bit_map;\n \t/*\n@@ -23164,7 +23531,43 @@ struct hwrm_func_backing_store_qcaps_v2_output {\n \t * | 4 | All four split entries have valid data. |\n \t */\n \tuint8_t\tsubtype_valid_cnt;\n-\tuint8_t\trsvd2;\n+\t/*\n+\t * Bitmap that indicates if each of the 'split_entry' denotes an\n+\t * exact count (i.e., min = max). When the exact count bit is set,\n+\t * it indicates the exact number of entries as advertised has to be\n+\t * configured. The 'split_entry' to be set to contain exact count by\n+\t * this bitmap needs to be a valid split entry specified by\n+\t * 'subtype_valid_cnt'.\n+\t */\n+\tuint8_t\texact_cnt_bit_map;\n+\t/*\n+\t * When this bit is '1', it indicates 'split_entry_0' contains\n+\t * an exact count.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates 'split_entry_1' contains\n+\t * an exact count.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates 'split_entry_2' contains\n+\t * an exact count.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates 'split_entry_3' contains\n+\t * an exact count.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT \\\n+\t\tUINT32_C(0x8)\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_SFT \\\n+\t\t4\n \t/*\n \t * Split entry #0. Note that the four split entries (as a group)\n \t * must be cast to a type-specific data structure first before\n@@ -23176,7 +23579,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {\n \t * | SRQ | srq_split_entries |\n \t * | CQ | cq_split_entries |\n \t * | VINC | vnic_split_entries |\n-\t * | MRAV | marv_split_entries |\n+\t * | MRAV | mrav_split_entries |\n+\t * | TS | ts_split_entries |\n \t */\n \tuint32_t\tsplit_entry_0;\n \t/* Split entry #1. */\n@@ -23471,7 +23875,9 @@ struct hwrm_func_dbr_pacing_qcfg_output {\n \t * dbr_throttling_aeq_arm_reg register.\n \t */\n \tuint8_t\tdbr_throttling_aeq_arm_reg_val;\n-\tuint8_t\tunused_3[7];\n+\tuint8_t\tunused_3[3];\n+\t/* This field indicates the maximum depth of the doorbell FIFO. */\n+\tuint32_t\tdbr_stat_db_max_fifo_depth;\n \t/*\n \t * Specifies primary function’s NQ ID.\n \t * A value of 0xFFFF FFFF indicates NQ ID is invalid.\n@@ -25128,7 +25534,7 @@ struct hwrm_func_spd_qcfg_output {\n *********************/\n \n \n-/* hwrm_port_phy_cfg_input (size:448b/56B) */\n+/* hwrm_port_phy_cfg_input (size:512b/64B) */\n struct hwrm_port_phy_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -25505,6 +25911,18 @@ struct hwrm_port_phy_cfg_input {\n \t */\n \t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \\\n \t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the force_link_speeds2 field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This bit must be '1' for the auto_link_speeds2_mask field to\n+\t * be configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK \\\n+\t\tUINT32_C(0x4000)\n \t/* Port ID of port that is to be configured. */\n \tuint16_t\tport_id;\n \t/*\n@@ -25808,7 +26226,99 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x2)\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \\\n \t\tUINT32_C(0x4)\n-\tuint8_t\tunused_2[2];\n+\t/*\n+\t * This is the speed that will be used if the force_link_speeds2\n+\t * bit is '1'. If unsupported speed is selected, an error\n+\t * will be generated.\n+\t */\n+\tuint16_t\tforce_link_speeds2;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB \\\n+\t\tUINT32_C(0xa)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB \\\n+\t\tUINT32_C(0x64)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB \\\n+\t\tUINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB \\\n+\t\tUINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB \\\n+\t\tUINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB \\\n+\t\tUINT32_C(0x3e8)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x1f5)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x3e9)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x7d1)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 \\\n+\t\tUINT32_C(0xfa1)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x3ea)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x7d2)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 \\\n+\t\tUINT32_C(0xfa2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112\n+\t/*\n+\t * This is a mask of link speeds that will be used if\n+\t * auto_link_speeds2_mask bit in the \"enables\" field is 1.\n+\t * If unsupported speed is enabled an error will be generated.\n+\t */\n+\tuint16_t\tauto_link_speeds2_mask;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB \\\n+\t\tUINT32_C(0x1)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB \\\n+\t\tUINT32_C(0x2)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB \\\n+\t\tUINT32_C(0x4)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x40)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x80)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x100)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 \\\n+\t\tUINT32_C(0x200)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x400)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x800)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 \\\n+\t\tUINT32_C(0x1000)\n+\tuint8_t\tunused_2[6];\n } __rte_packed;\n \n /* hwrm_port_phy_cfg_output (size:128b/16B) */\n@@ -25932,11 +26442,14 @@ struct hwrm_port_phy_qcfg_output {\n \t/* NRZ signaling */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \\\n \t\tUINT32_C(0x0)\n-\t/* PAM4 signaling */\n+\t/* PAM4-56 signaling */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \\\n \t\tUINT32_C(0x1)\n+\t/* PAM4-112 signaling */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 \\\n+\t\tUINT32_C(0x2)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112\n \t/* This value indicates the current active FEC mode. */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \\\n \t\tUINT32_C(0xf0)\n@@ -25992,6 +26505,8 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)\n \t/* 200Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)\n+\t/* 400Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \\\n@@ -26446,8 +26961,56 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 100G_BASEER2 */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \\\n \t\tUINT32_C(0x27)\n+\t/* 400G_BASECR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR \\\n+\t\tUINT32_C(0x28)\n+\t/* 100G_BASESR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR \\\n+\t\tUINT32_C(0x29)\n+\t/* 100G_BASELR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR \\\n+\t\tUINT32_C(0x2a)\n+\t/* 100G_BASEER */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER \\\n+\t\tUINT32_C(0x2b)\n+\t/* 200G_BASECR2 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2 \\\n+\t\tUINT32_C(0x2c)\n+\t/* 200G_BASESR2 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2 \\\n+\t\tUINT32_C(0x2d)\n+\t/* 200G_BASELR2 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2 \\\n+\t\tUINT32_C(0x2e)\n+\t/* 200G_BASEER2 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2 \\\n+\t\tUINT32_C(0x2f)\n+\t/* 400G_BASECR8 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8 \\\n+\t\tUINT32_C(0x30)\n+\t/* 200G_BASESR8 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8 \\\n+\t\tUINT32_C(0x31)\n+\t/* 400G_BASELR8 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8 \\\n+\t\tUINT32_C(0x32)\n+\t/* 400G_BASEER8 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8 \\\n+\t\tUINT32_C(0x33)\n+\t/* 400G_BASECR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4 \\\n+\t\tUINT32_C(0x34)\n+\t/* 400G_BASESR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4 \\\n+\t\tUINT32_C(0x35)\n+\t/* 400G_BASELR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4 \\\n+\t\tUINT32_C(0x36)\n+\t/* 400G_BASEER4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4 \\\n+\t\tUINT32_C(0x37)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4\n \t/* This value represents a media type. */\n \tuint8_t\tmedia_type;\n \t/* Unknown */\n@@ -26855,6 +27418,12 @@ struct hwrm_port_phy_qcfg_output {\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', speeds2 fields are used to get\n+\t * speed details.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * Up to 16 bytes of null padded ASCII string representing\n \t * PHY vendor.\n@@ -26933,7 +27502,162 @@ struct hwrm_port_phy_qcfg_output {\n \tuint8_t\tlink_down_reason;\n \t/* Remote fault */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * The supported speeds for the port. This is a bit mask.\n+\t * For each speed that is supported, the corresponding\n+\t * bit will be set to '1'. This is valid only if speeds2_supported\n+\t * is set in option_flags\n+\t */\n+\tuint16_t\tsupport_speeds2;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB \\\n+\t\tUINT32_C(0x1)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB \\\n+\t\tUINT32_C(0x2)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB \\\n+\t\tUINT32_C(0x4)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x40)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x80)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x100)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56 \\\n+\t\tUINT32_C(0x200)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x400)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x800)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112 \\\n+\t\tUINT32_C(0x1000)\n+\t/* 800Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * Current setting of forced link speed. When the link speed is not\n+\t * being forced, this value shall be set to 0.\n+\t * This field is valid only if speeds2_supported is set in option_flags.\n+\t */\n+\tuint16_t\tforce_link_speeds2;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB \\\n+\t\tUINT32_C(0xa)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB \\\n+\t\tUINT32_C(0x64)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB \\\n+\t\tUINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB \\\n+\t\tUINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB \\\n+\t\tUINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB \\\n+\t\tUINT32_C(0x3e8)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x1f5)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x3e9)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x7d1)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 \\\n+\t\tUINT32_C(0xfa1)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x3ea)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x7d2)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 \\\n+\t\tUINT32_C(0xfa2)\n+\t/* 800Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 \\\n+\t\tUINT32_C(0x1f42)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112\n+\t/*\n+\t * Current setting of auto_link speed_mask that is used to advertise\n+\t * speeds during autonegotiation.\n+\t * This field is only valid when auto_mode is set to \"mask\".\n+\t * and if speeds2_supported is set in option_flags\n+\t * The speeds specified in this field shall be a subset of\n+\t * supported speeds on this port.\n+\t */\n+\tuint16_t\tauto_link_speeds2;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB \\\n+\t\tUINT32_C(0x1)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB \\\n+\t\tUINT32_C(0x2)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB \\\n+\t\tUINT32_C(0x4)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x40)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x80)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x100)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56 \\\n+\t\tUINT32_C(0x200)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x400)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x800)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112 \\\n+\t\tUINT32_C(0x1000)\n+\t/* 800Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This field is indicate the number of lanes used to transfer\n+\t * data. If the link is down, the value is zero.\n+\t * This is valid only if speeds2_supported is set in option_flags.\n+\t */\n+\tuint8_t\tactive_lanes;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -28381,7 +29105,7 @@ struct tx_port_stats_ext {\n } __rte_packed;\n \n /* Port Rx Statistics extended Format */\n-/* rx_port_stats_ext (size:3776b/472B) */\n+/* rx_port_stats_ext (size:3904b/488B) */\n struct rx_port_stats_ext {\n \t/* Number of times link state changed to down */\n \tuint64_t\tlink_down_events;\n@@ -28462,8 +29186,9 @@ struct rx_port_stats_ext {\n \t/* The number of events where the port receive buffer was over 85% full */\n \tuint64_t\trx_buffer_passed_threshold;\n \t/*\n-\t * The number of symbol errors that wasn't corrected by FEC correction\n-\t * algorithm\n+\t * This counter represents uncorrected symbol errors post-FEC and may not\n+\t * be populated in all cases. Each uncorrected FEC block may result in\n+\t * one or more symbol errors.\n \t */\n \tuint64_t\trx_pcs_symbol_err;\n \t/* The number of corrected bits on the port according to active FEC */\n@@ -28507,6 +29232,21 @@ struct rx_port_stats_ext {\n \t * FEC function in the PHY\n \t */\n \tuint64_t\trx_fec_uncorrectable_blocks;\n+\t/*\n+\t * Total number of packets that are dropped due to not matching\n+\t * any RX filter rules. This value is zero on the non supported\n+\t * controllers. This counter is per controller, Firmware reports the\n+\t * same value on active ports. This counter does not include the\n+\t * packet discards because of no available buffers.\n+\t */\n+\tuint64_t\trx_filter_miss;\n+\t/*\n+\t * This field represents the number of FEC symbol errors by counting\n+\t * once for each 10-bit symbol corrected by FEC block.\n+\t * rx_fec_corrected_blocks will be incremented if all symbol errors in a\n+\t * codeword gets corrected.\n+\t */\n+\tuint64_t\trx_fec_symbol_err;\n } __rte_packed;\n \n /*\n@@ -29435,7 +30175,7 @@ struct hwrm_port_phy_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_port_phy_qcaps_output (size:256b/32B) */\n+/* hwrm_port_phy_qcaps_output (size:320b/40B) */\n struct hwrm_port_phy_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -29725,6 +30465,13 @@ struct hwrm_port_phy_qcaps_output {\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then this field indicates that\n+\t * supported_speed2 field is to be used in lieu of all\n+\t * supported_speed variants.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n \t/*\n \t * Number of internal ports for this device. This field allows the FW\n \t * to advertise how many internal ports are present. Manufacturing\n@@ -29733,6 +30480,108 @@ struct hwrm_port_phy_qcaps_output {\n \t * option \"HPTN_MODE\" is set to 1.\n \t */\n \tuint8_t\tinternal_port_cnt;\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * This is a bit mask to indicate what speeds are supported\n+\t * as forced speeds on this link.\n+\t * For each speed that can be forced on this link, the\n+\t * corresponding mask bit shall be set to '1'.\n+\t * This field is valid only if speeds2_supported bit is set in flags2\n+\t */\n+\tuint16_t\tsupported_speeds2_force_mode;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB \\\n+\t\tUINT32_C(0x1)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB \\\n+\t\tUINT32_C(0x2)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB \\\n+\t\tUINT32_C(0x4)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x40)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x80)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x100)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 \\\n+\t\tUINT32_C(0x200)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x400)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x800)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 \\\n+\t\tUINT32_C(0x1000)\n+\t/* 800Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This is a bit mask to indicate what speeds are supported\n+\t * for autonegotiation on this link.\n+\t * For each speed that can be autonegotiated on this link, the\n+\t * corresponding mask bit shall be set to '1'.\n+\t * This field is valid only if speeds2_supported bit is set in flags2\n+\t */\n+\tuint16_t\tsupported_speeds2_auto_mode;\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB \\\n+\t\tUINT32_C(0x1)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB \\\n+\t\tUINT32_C(0x2)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB \\\n+\t\tUINT32_C(0x4)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 50Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 \\\n+\t\tUINT32_C(0x40)\n+\t/* 100Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 \\\n+\t\tUINT32_C(0x80)\n+\t/* 200Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 \\\n+\t\tUINT32_C(0x100)\n+\t/* 400Gb (PAM4-56: 50G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 \\\n+\t\tUINT32_C(0x200)\n+\t/* 100Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 \\\n+\t\tUINT32_C(0x400)\n+\t/* 200Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 \\\n+\t\tUINT32_C(0x800)\n+\t/* 400Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 \\\n+\t\tUINT32_C(0x1000)\n+\t/* 800Gb (PAM4-112: 100G per lane) link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 \\\n+\t\tUINT32_C(0x2000)\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -38132,6 +38981,9 @@ struct hwrm_vnic_qcaps_output {\n \t/* When this bit is '1' FW supports VNIC hash mode. */\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \\\n \t\tUINT32_C(0x10000000)\n+\t/* When this bit is set to '1', hardware supports tunnel TPA. */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP \\\n+\t\tUINT32_C(0x20000000)\n \t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2 or v3.\n@@ -38154,7 +39006,7 @@ struct hwrm_vnic_qcaps_output {\n *********************/\n \n \n-/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */\n+/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */\n struct hwrm_vnic_tpa_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -38276,6 +39128,12 @@ struct hwrm_vnic_tpa_cfg_input {\n \t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)\n \t/* deprecated bit. Do not use!!! */\n \t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the tnl_tpa_en_bitmap field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN \\\n+\t\tUINT32_C(0x10)\n \t/* Logical vnic ID */\n \tuint16_t\tvnic_id;\n \t/*\n@@ -38332,6 +39190,117 @@ struct hwrm_vnic_tpa_cfg_input {\n \t * and can be queried using hwrm_vnic_tpa_qcfg.\n \t */\n \tuint32_t\tmin_agg_len;\n+\t/*\n+\t * If the device supports hardware tunnel TPA feature, as indicated by\n+\t * the HWRM_VNIC_QCAPS command, this field is used to configure the\n+\t * tunnel types to be enabled. Each bit corresponds to a specific\n+\t * tunnel type. If a bit is set to '1', then the associated tunnel\n+\t * type is enabled; otherwise, it is disabled.\n+\t */\n+\tuint32_t\ttnl_tpa_en_bitmap;\n+\t/*\n+\t * When this bit is '1', enable VXLAN encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to ‘1’, enable GENEVE encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is set to ‘1’, enable NVGRE encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is set to ‘1’, enable GRE encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is set to ‘1’, enable IPV4 encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is set to ‘1’, enable IPV6 encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6 \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', enable VXLAN_GPE encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', enable UPAR1 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1 \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', enable UPAR2 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2 \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * When this bit is '1', enable UPAR3 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3 \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When this bit is '1', enable UPAR4 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4 \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * When this bit is '1', enable UPAR5 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When this bit is '1', enable UPAR6 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6 \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * When this bit is '1', enable UPAR7 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7 \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * When this bit is '1', enable UPAR8 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 \\\n+\t\tUINT32_C(0x10000)\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */\n@@ -38355,6 +39324,288 @@ struct hwrm_vnic_tpa_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/**********************\n+ * hwrm_vnic_tpa_qcfg *\n+ **********************/\n+\n+\n+/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */\n+struct hwrm_vnic_tpa_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Logical vnic ID */\n+\tuint16_t\tvnic_id;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */\n+struct hwrm_vnic_tpa_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) of\n+\t * non-tunneled TCP packets.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) of\n+\t * tunneled TCP packets.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) according\n+\t * to Windows Receive Segment Coalescing (RSC) rules.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) according\n+\t * to Linux Generic Receive Offload (GRO) rules.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) for TCP\n+\t * packets with IP ECN set to non-zero.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * GRE tunneled TCP packets only if all packets have the\n+\t * same GRE sequence.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1' and the GRO mode is enabled,\n+\t * the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * TCP/IPv4 packets with consecutively increasing IPIDs.\n+\t * In other words, the last packet that is being\n+\t * aggregated to an already existing aggregation context\n+\t * shall have IPID 1 more than the IPID of the last packet\n+\t * that was aggregated in that aggregation context.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1' and the GRO mode is enabled,\n+\t * the VNIC is configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)\n+\t * value.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This is the maximum number of TCP segments that can\n+\t * be aggregated (unit is Log2). Max value is 31.\n+\t */\n+\tuint16_t\tmax_agg_segs;\n+\t/* 1 segment */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)\n+\t/* 2 segments */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)\n+\t/* 4 segments */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)\n+\t/* 8 segments */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)\n+\t/* Any segment size larger than this is not valid */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \\\n+\t\tHWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX\n+\t/*\n+\t * This is the maximum number of aggregations this VNIC is\n+\t * allowed (unit is Log2). Max value is 7\n+\t */\n+\tuint16_t\tmax_aggs;\n+\t/* 1 aggregation */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)\n+\t/* 2 aggregations */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)\n+\t/* 4 aggregations */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)\n+\t/* 8 aggregations */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)\n+\t/* 16 aggregations */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)\n+\t/* Any aggregation size larger than this is not valid */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \\\n+\t\tHWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX\n+\t/*\n+\t * This is the maximum amount of time allowed for\n+\t * an aggregation context to complete after it was initiated.\n+\t */\n+\tuint32_t\tmax_agg_timer;\n+\t/*\n+\t * This is the minimum amount of payload length required to\n+\t * start an aggregation context.\n+\t */\n+\tuint32_t\tmin_agg_len;\n+\t/*\n+\t * If the device supports hardware tunnel TPA feature, as indicated by\n+\t * the HWRM_VNIC_QCAPS command, this field conveys the bitmap of the\n+\t * tunnel types that have been configured. Each bit corresponds to a\n+\t * specific tunnel type. If a bit is set to '1', then the associated\n+\t * tunnel type is enabled; otherwise, it is disabled.\n+\t */\n+\tuint32_t\ttnl_tpa_en_bitmap;\n+\t/*\n+\t * When this bit is '1', enable VXLAN encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to ‘1’, enable GENEVE encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is set to ‘1’, enable NVGRE encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is set to ‘1’, enable GRE encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is set to ‘1’, enable IPV4 encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4 \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is set to ‘1’, enable IPV6 encapsulated packets\n+\t * for aggregation..\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6 \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', enable VXLAN_GPE encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets\n+\t * for aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', enable UPAR1 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1 \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', enable UPAR2 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2 \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * When this bit is '1', enable UPAR3 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3 \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When this bit is '1', enable UPAR4 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4 \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * When this bit is '1', enable UPAR5 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5 \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When this bit is '1', enable UPAR6 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6 \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * When this bit is '1', enable UPAR7 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7 \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * When this bit is '1', enable UPAR8 encapsulated packets for\n+\t * aggregation.\n+\t */\n+\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8 \\\n+\t\tUINT32_C(0x10000)\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /*********************\n * hwrm_vnic_rss_cfg *\n *********************/\n@@ -38572,6 +39823,12 @@ struct hwrm_vnic_rss_cfg_input {\n \t */\n \t#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that the support of setting\n+\t * ipsec hash_types by the host drivers.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT \\\n+\t\tUINT32_C(0x4)\n \tuint8_t\tring_select_mode;\n \t/*\n \t * In this mode, HW uses Toeplitz algorithm and provided Toeplitz\n@@ -39439,6 +40696,12 @@ struct hwrm_ring_alloc_input {\n \t */\n \t#define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \\\n \t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the steering_tag field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID \\\n+\t\tUINT32_C(0x800)\n \t/* Ring Type. */\n \tuint8_t\tring_type;\n \t/* L2 Completion Ring (CR) */\n@@ -39664,7 +40927,8 @@ struct hwrm_ring_alloc_input {\n \t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \\\n \t\tUINT32_C(0xff00)\n \t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8\n-\tuint16_t\tunused_3;\n+\t/* Steering tag to use for memory transactions. */\n+\tuint16_t\tsteering_tag;\n \t/*\n \t * This field is reserved for the future use.\n \t * It shall be set to 0.\n@@ -43871,7 +45135,10 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t * Setting of this flag indicates that the dst_id field contains RFS\n \t * ring table index. If this is not set it indicates dst_id is VNIC\n \t * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx\n-\t * can’t be set at the same time.\n+\t * can't be set at the same time. Updated drivers should pass ring\n+\t * idx in the rfs_ring_tbl_idx field if the firmware indicates\n+\t * support for the new field in the HWRM_CFA_ADV_FLOW_MGMT_QCAPS\n+\t * response.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \\\n \t\tUINT32_C(0x20)\n@@ -43986,10 +45253,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n \t\tUINT32_C(0x10000)\n-\t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n-\t */\n+\t/* This flag is deprecated. */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n \t\tUINT32_C(0x20000)\n \t/*\n@@ -43998,7 +45262,10 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n \t\tUINT32_C(0x40000)\n-\t/* This flag is deprecated. */\n+\t/*\n+\t * This bit must be '1' for the rfs_ring_tbl_idx field to\n+\t * be configured.\n+\t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \\\n \t\tUINT32_C(0x80000)\n \t/*\n@@ -44069,10 +45336,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \tuint16_t\tdst_id;\n \t/*\n-\t * Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n+\t * If set, this value shall represent the ring table\n+\t * index for receive flow steering. Note that this offset\n+\t * was formerly used for the mirror_vnic_id field, which\n+\t * is no longer supported.\n \t */\n-\tuint16_t\tmirror_vnic_id;\n+\tuint16_t\trfs_ring_tbl_idx;\n \t/*\n \t * This value indicates the tunnel type for this filter.\n \t * If this field is not specified, then the filter shall\n@@ -50258,6 +51527,13 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \\\n \t\tUINT32_C(0x100000)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx (new offset) in HWRM_CFA_NTUPLE_ALLOC command.\n+\t * Value of 0 indicates ring tbl idx should be passed using dst_id.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED \\\n+\t\tUINT32_C(0x200000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -56744,9 +58020,17 @@ struct hwrm_tunnel_dst_port_query_input {\n \t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n \t\tUINT32_C(0x10)\n+\t/* Generic Routing Encapsulation */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE \\\n+\t\tUINT32_C(0x11)\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE\n-\tuint8_t\tunused_0[7];\n+\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE\n+\t/*\n+\t * This field is used to specify the next protocol value defined in the\n+\t * corresponding RFC spec for the applicable tunnel type.\n+\t */\n+\tuint8_t\ttunnel_next_proto;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */\n@@ -56808,7 +58092,21 @@ struct hwrm_tunnel_dst_port_query_output {\n \t/* This bit will be '1' when UPAR7 is IN_USE */\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \\\n \t\tUINT32_C(0x80)\n-\tuint8_t\tunused_0[2];\n+\t/*\n+\t * This field is used to convey the status of non udp port based\n+\t * tunnel parsing at chip level and at function level.\n+\t */\n+\tuint8_t\tstatus;\n+\t/* This bit will be '1' when tunnel parsing is enabled globally. */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit will be '1' when tunnel parsing is enabled\n+\t * on the corresponding function.\n+\t */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL \\\n+\t\tUINT32_C(0x2)\n+\tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -56886,9 +58184,16 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n \t\tUINT32_C(0x10)\n+\t/* Generic Routing Encapsulation */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE \\\n+\t\tUINT32_C(0x11)\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE\n-\tuint8_t\tunused_0;\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE\n+\t/*\n+\t * This field is used to specify the next protocol value defined in the\n+\t * corresponding RFC spec for the applicable tunnel type.\n+\t */\n+\tuint8_t\ttunnel_next_proto;\n \t/*\n \t * This field represents the value of L4 destination port used\n \t * for the given tunnel type. This field is valid for\n@@ -56900,7 +58205,7 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t * A value of 0 shall fail the command.\n \t */\n \tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_1[4];\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */\n@@ -56929,8 +58234,11 @@ struct hwrm_tunnel_dst_port_alloc_output {\n \t/* Out of resources error */\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \\\n \t\tUINT32_C(0x2)\n+\t/* Tunnel type is alread enabled */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED \\\n+\t\tUINT32_C(0x3)\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED\n \t/*\n \t * This field represents the UPAR usage status.\n \t * Available UPARs on wh+ are UPAR0 and UPAR1\n@@ -57040,15 +58348,22 @@ struct hwrm_tunnel_dst_port_free_input {\n \t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n \t\tUINT32_C(0x10)\n+\t/* Generic Routing Encapsulation */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE \\\n+\t\tUINT32_C(0x11)\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE\n-\tuint8_t\tunused_0;\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE\n+\t/*\n+\t * This field is used to specify the next protocol value defined in the\n+\t * corresponding RFC spec for the applicable tunnel type.\n+\t */\n+\tuint8_t\ttunnel_next_proto;\n \t/*\n \t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n \t * types that has l4 destination port parameters.\n \t */\n \tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_1[4];\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */\n@@ -57234,7 +58549,7 @@ struct ctx_eng_stats {\n ***********************/\n \n \n-/* hwrm_stat_ctx_alloc_input (size:256b/32B) */\n+/* hwrm_stat_ctx_alloc_input (size:320b/40B) */\n struct hwrm_stat_ctx_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -57305,6 +58620,18 @@ struct hwrm_stat_ctx_alloc_input {\n \t * for the periodic DMA updates.\n \t */\n \tuint16_t\tstats_dma_length;\n+\tuint16_t\tflags;\n+\t/* This stats context uses the steering tag specified in the command. */\n+\t#define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Steering tag to use for memory transactions from the periodic DMA\n+\t * updates. 'steering_tag_valid' should be set and 'steering_tag'\n+\t * should be specified, when the 'steering_tag_supported' bit is set\n+\t * under the 'flags_ext2' field of the hwrm_func_qcaps_output.\n+\t */\n+\tuint16_t\tsteering_tag;\n+\tuint32_t\tunused_1;\n } __rte_packed;\n \n /* hwrm_stat_ctx_alloc_output (size:128b/16B) */\n", "prefixes": [ "v2", "02/14" ] }