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GET /api/patches/134115/?format=api
{ "id": 134115, "url": "http://patches.dpdk.org/api/patches/134115/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231111160006.455767-3-jesna.k.e@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231111160006.455767-3-jesna.k.e@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231111160006.455767-3-jesna.k.e@amd.com", "date": "2023-11-11T16:00:06", "name": "[v1,3/3] net/axgbe: support TSO Implementation", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9f9145e340c4485502bdb04efc5c5136a000868c", "submitter": { "id": 2920, "url": "http://patches.dpdk.org/api/people/2920/?format=api", "name": "Jesna K E", "email": "jesna.k.e@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231111160006.455767-3-jesna.k.e@amd.com/mbox/", "series": [ { "id": 30251, "url": "http://patches.dpdk.org/api/series/30251/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30251", "date": "2023-11-11T16:00:04", "name": "[v1,1/3] net/axgbe: packet size doesn't exceed the configured MTU", "version": 1, "mbox": "http://patches.dpdk.org/series/30251/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134115/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/134115/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=LOXaX0CIELuKGLqQr7vpsn3s75Y9252pzf/3icuijvnsW0+oeEQY968M5qYsYBw7+zPBzp8aAnrWMaP3C4qyH6o0RNdcA89esI9+Z/Ugml7GOVvtxf9EJi8iZgqwLOxoJ+LFJd2vCtcW+GCKowT//lA9aYQVAm0yjUDeDRuLY60=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Jesna K E <jesna.k.e@amd.com>", "To": "<dev@dpdk.org>", "CC": "<Ferruh.Yigit@amd.com>, <Selwin.Sebastian@amd.com>, Jesna K E\n <jesna.k.e@amd.com>", "Subject": "[PATCH v1 3/3] net/axgbe: support TSO Implementation", "Date": "Sat, 11 Nov 2023 21:30:06 +0530", "Message-ID": "<20231111160006.455767-3-jesna.k.e@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": 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SFS:(13230031)(4636009)(396003)(376002)(136003)(346002)(39860400002)(230922051799003)(451199024)(186009)(64100799003)(1800799009)(82310400011)(46966006)(36840700001)(40470700004)(40460700003)(16526019)(336012)(426003)(1076003)(26005)(7696005)(6666004)(2616005)(36860700001)(83380400001)(47076005)(5660300002)(4326008)(8936002)(8676002)(30864003)(2906002)(41300700001)(478600001)(316002)(6916009)(54906003)(70206006)(70586007)(36756003)(103116003)(86362001)(82740400003)(356005)(81166007)(40480700001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 Nov 2023 16:00:37.1619 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5b6f9913-f4ef-493b-3558-08dbe2cf5861", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF0001AB71.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8873", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Signed-off-by: Jesna K E <jesna.k.e@amd.com>\n---\n drivers/net/axgbe/axgbe_common.h | 11 +\n drivers/net/axgbe/axgbe_dev.c | 19 ++\n drivers/net/axgbe/axgbe_ethdev.c | 1 +\n drivers/net/axgbe/axgbe_ethdev.h | 1 +\n drivers/net/axgbe/axgbe_rxtx.c | 305 +++++++++++++++----------\n drivers/net/axgbe/axgbe_rxtx_vec_sse.c | 1 +\n 6 files changed, 223 insertions(+), 115 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex a5d11c5832..1face6f361 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -162,6 +162,9 @@\n #define DMA_CH_SR\t\t\t0x60\n \n /* DMA channel register entry bit positions and sizes */\n+//TSO\n+#define DMA_CH_CR_MSS_INDEX 0\n+#define DMA_CH_CR_MSS_WIDTH 14\n #define DMA_CH_CR_PBLX8_INDEX\t\t16\n #define DMA_CH_CR_PBLX8_WIDTH\t\t1\n #define DMA_CH_CR_SPH_INDEX\t\t24\n@@ -1232,6 +1235,14 @@\n #define TX_CONTEXT_DESC3_VT_INDEX\t\t0\n #define TX_CONTEXT_DESC3_VT_WIDTH\t\t16\n \n+//TSO\n+#define TX_NORMAL_DESC3_TPL_INDEX 0\n+#define TX_NORMAL_DESC3_TPL_WIDTH 18\n+#define TX_NORMAL_DESC3_THL_INDEX 19\n+#define TX_NORMAL_DESC3_THL_WIDTH 4\n+#define TX_CONTEXT_DESC3_OSTC_INDEX 27\n+#define TX_CONTEXT_DESC3_OSTC_WIDTH 1\n+\n #define TX_NORMAL_DESC2_HL_B1L_INDEX\t\t0\n #define TX_NORMAL_DESC2_HL_B1L_WIDTH\t\t14\n #define TX_NORMAL_DESC2_IC_INDEX\t\t31\ndiff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex 6a7fddffca..7e0d387fc3 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -808,6 +808,24 @@ int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)\n \treturn 0;\n }\n \n+\n+static void xgbe_config_tso_mode(struct axgbe_port *pdata)\n+{\n+ unsigned int i;\n+\n+ struct axgbe_tx_queue *txq;\n+\n+ for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) {\n+ txq = pdata->eth_dev->data->tx_queues[i];\n+ AXGMAC_DMA_IOWRITE_BITS(txq,DMA_CH_TCR, TSE,\n+ 1);\n+\t\tAXGMAC_DMA_IOWRITE_BITS(txq,DMA_CH_CR, MSS,\n+\t\t\t\t\t800);\n+ }\n+\n+}\n+\n+\n static int axgbe_enable_rss(struct axgbe_port *pdata)\n {\n \tint ret;\n@@ -1314,6 +1332,7 @@ static int axgbe_init(struct axgbe_port *pdata)\n \taxgbe_config_rx_pbl_val(pdata);\n \taxgbe_config_rx_buffer_size(pdata);\n \taxgbe_config_rss(pdata);\n+\txgbe_config_tso_mode(pdata);\n \twrapper_tx_desc_init(pdata);\n \tret = wrapper_rx_desc_init(pdata);\n \tif (ret)\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c\nindex e1cb60c1c3..5aa8743a1a 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.c\n+++ b/drivers/net/axgbe/axgbe_ethdev.c\n@@ -1237,6 +1237,7 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tRTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\n \t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS |\n \t\tRTE_ETH_TX_OFFLOAD_UDP_CKSUM |\n+\t\tRTE_ETH_TX_OFFLOAD_TCP_TSO |\n \t\tRTE_ETH_TX_OFFLOAD_TCP_CKSUM;\n \n \tif (pdata->hw_feat.rss) {\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex 7f19321d88..31a583c2c6 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -583,6 +583,7 @@ struct axgbe_port {\n \tunsigned int tx_osp_mode;\n \tunsigned int tx_max_fifo_size;\n \tunsigned int multi_segs_tx;\n+\tunsigned int tso_tx;\n \n \t/* Rx settings */\n \tunsigned int rx_sf_mode;\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c\nindex 68aa67a3fa..6b5ea6d622 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.c\n+++ b/drivers/net/axgbe/axgbe_rxtx.c\n@@ -643,6 +643,10 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS))\n \t\tpdata->multi_segs_tx = true;\n \n+\tif ((dev_data->dev_conf.txmode.offloads &\n+ RTE_ETH_TX_OFFLOAD_TCP_TSO))\n+ pdata->tso_tx = true;\n+\n \n \treturn 0;\n }\n@@ -843,7 +847,7 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,\n \n \tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n \tdesc = &txq->desc[idx];\n-\n+\tprintf(\"tso::Inside axgbe_xmit_hw \\n\");\n \t/* Update buffer address and length */\n \tdesc->baddr = rte_mbuf_data_iova(mbuf);\n \tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,\n@@ -889,7 +893,6 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,\n \tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n \trte_wmb();\n \n-\n \t/* Save mbuf */\n \ttxq->sw_ring[idx] = mbuf;\n \t/* Update current index*/\n@@ -900,138 +903,208 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,\n \treturn 0;\n }\n \n+\n /* Tx Descriptor formation for segmented mbuf\n * Each mbuf will require multiple descriptors\n */\n \n static int\n axgbe_xmit_hw_seg(struct axgbe_tx_queue *txq,\n-\t\tstruct rte_mbuf *mbuf)\n+ struct rte_mbuf *mbuf)\n {\n-\tvolatile struct axgbe_tx_desc *desc;\n-\tuint16_t idx;\n-\tuint64_t mask;\n-\tint start_index;\n-\tuint32_t pkt_len = 0;\n-\tint nb_desc_free;\n-\tstruct rte_mbuf *tx_pkt;\n+ volatile struct axgbe_tx_desc *desc;\n+ uint16_t idx;\n+ uint64_t mask;\n+ int start_index;\n+ uint32_t pkt_len = 0;\n+ int nb_desc_free;\n+ struct rte_mbuf *tx_pkt;\n+ uint64_t l2_len = 0;\n+ uint64_t l3_len = 0;\n+ uint64_t l4_len = 0;\n+ uint64_t tso_segsz = 0;\n+ uint64_t total_hdr_len;\n+\tint tso = 0;\n+\n+ /*Parameters required for tso*/\n+ l2_len = mbuf->l2_len;\n+ l3_len = mbuf->l3_len;\n+ l4_len = mbuf->l4_len;\n+ tso_segsz = mbuf->tso_segsz;\n+ total_hdr_len = l2_len + l3_len + l4_len;\n+\n+ if ((txq->pdata->tso_tx))\n+ tso = 1;\n+ else\n+ tso = 0;\n+\n+ printf(\"tso:l2_len = %ld,l3_len=%ld,l4_len=%ld,tso_segsz=%ld,total_hdr_len%ld\\n\",l2_len,l3_len,l4_len,\n+ tso_segsz,total_hdr_len);\n+\n+ nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+\n+ printf(\"tso::Inside axgbe_xmit_hw_seg \\n\");\n+ if (mbuf->nb_segs > nb_desc_free) {\n+ axgbe_xmit_cleanup_seg(txq);\n+ nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+ if (unlikely(mbuf->nb_segs > nb_desc_free))\n+ return RTE_ETH_TX_DESC_UNAVAIL;\n+ }\n+\n+ idx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n+ desc = &txq->desc[idx];\n+ /* Saving the start index for setting the OWN bit finally */\n+ start_index = idx;\n+\ttx_pkt = mbuf;\n+ /* Max_pkt len = 9018 ; need to update it according to Jumbo pkt size */\n+ pkt_len = tx_pkt->pkt_len;\n \n-\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+ /* Update buffer address and length */\n+ desc->baddr = rte_pktmbuf_iova_offset(mbuf,0);\n+ /*For TSO first buffer contains the Header */\n+ if (tso)\n+\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,\n+ total_hdr_len);\n+\telse\n+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,\n+ tx_pkt->data_len);\n \n-\tif (mbuf->nb_segs > nb_desc_free) {\n-\t\taxgbe_xmit_cleanup_seg(txq);\n-\t\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n-\t\tif (unlikely(mbuf->nb_segs > nb_desc_free))\n-\t\t\treturn RTE_ETH_TX_DESC_UNAVAIL;\n-\t}\n+\trte_wmb();\n \n+\t/* Timestamp enablement check */\n+ if (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)\n+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);\n+\n+ rte_wmb();\n+ /* Mark it as First Descriptor */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);\n+ /* Mark it as a NORMAL descriptor */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n+ /* configure h/w Offload */\n+ mask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n+ if (mask == RTE_MBUF_F_TX_TCP_CKSUM || mask == RTE_MBUF_F_TX_UDP_CKSUM)\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);\n+ else if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);\n+ rte_wmb();\n+\n+ if (mbuf->ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {\n+ /* Mark it as a CONTEXT descriptor */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+ CTXT, 1);\n+ /* Set the VLAN tag */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+ VT, mbuf->vlan_tci);\n+ /* Indicate this descriptor contains the VLAN tag */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+ VLTV, 1);\n+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR,\n+ TX_NORMAL_DESC2_VLAN_INSERT);\n+ } else {\n+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0);\n+ }\n+ rte_wmb();\n+\n+\t/*Register settings for TSO*/\n+ if (tso) {\n+ printf(\"Inside register setting-tso\\n\");\n+ /* Enable TSO */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, TSE,1);\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, TPL,\n+ ((mbuf->pkt_len)-total_hdr_len));\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, THL,\n+ l4_len);\n+ } else {\n+ /* Enable CRC and Pad Insertion */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CPC, 0);\n+ /* Total msg length to transmit */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,\n+ mbuf->pkt_len);\n+ }\n+#if 0\n+\t/*For TSO , needs one more descriptor to hold\n+\t * the Payload\n+\t * But while adding another descriptor packets are not\n+\t * transmitted */\n+ /* Save mbuf */\n+ txq->sw_ring[idx] = tx_pkt;\n+ /* Update current index*/\n+ txq->cur++;\n \tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n \tdesc = &txq->desc[idx];\n-\t/* Saving the start index for setting the OWN bit finally */\n-\tstart_index = idx;\n+\tdesc->baddr = rte_pktmbuf_iova_offset(mbuf,total_hdr_len);\n+\tAXGMAC_SET_BITS_LE(desc->desc2,\n+\t\t\tTX_NORMAL_DESC2, HL_B1L, (mbuf->pkt_len)-total_hdr_len));\n \n-\ttx_pkt = mbuf;\n-\t/* Max_pkt len = 9018 ; need to update it according to Jumbo pkt size */\n-\tpkt_len = tx_pkt->pkt_len;\n+\tprintf(\"(mbuf->pkt_len)-total_hdr_len=%d\\n\",(mbuf->pkt_len)-total_hdr_len);\n+ printf(\"total_hdr_len=%d\\n\",total_hdr_len);\n \n-\t/* Update buffer address and length */\n-\tdesc->baddr = rte_mbuf_data_iova(tx_pkt);\n-\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,\n-\t\t\t\t\t tx_pkt->data_len);\n-\t/* Total msg length to transmit */\n-\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,\n-\t\t\t\t\t tx_pkt->pkt_len);\n-\t/* Timestamp enablement check */\n-\tif (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)\n-\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);\n-\n-\trte_wmb();\n-\t/* Mark it as First Descriptor */\n-\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);\n-\t/* Mark it as a NORMAL descriptor */\n \tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n-\t/* configure h/w Offload */\n-\tmask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n-\tif (mask == RTE_MBUF_F_TX_TCP_CKSUM || mask == RTE_MBUF_F_TX_UDP_CKSUM)\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);\n-\telse if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);\n-\trte_wmb();\n-\n-\tif (mbuf->ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {\n-\t\t/* Mark it as a CONTEXT descriptor */\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n-\t\t\t\tCTXT, 1);\n-\t\t/* Set the VLAN tag */\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n-\t\t\t\tVT, mbuf->vlan_tci);\n-\t\t/* Indicate this descriptor contains the VLAN tag */\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n-\t\t\t\tVLTV, 1);\n-\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR,\n-\t\t\t\tTX_NORMAL_DESC2_VLAN_INSERT);\n-\t} else {\n-\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0);\n-\t}\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n \trte_wmb();\n-\n-\t/* Save mbuf */\n-\ttxq->sw_ring[idx] = tx_pkt;\n-\t/* Update current index*/\n \ttxq->cur++;\n-\n-\ttx_pkt = tx_pkt->next;\n+#endif\n+#if 1\n+ /* Save mbuf */\n+ txq->sw_ring[idx] = tx_pkt;\n+ /* Update current index*/\n+ txq->cur++;\n+#endif\n+ tx_pkt = tx_pkt->next;\n \n \twhile (tx_pkt != NULL) {\n-\t\tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n-\t\tdesc = &txq->desc[idx];\n-\n-\t\t/* Update buffer address and length */\n-\t\tdesc->baddr = rte_mbuf_data_iova(tx_pkt);\n-\n-\t\tAXGMAC_SET_BITS_LE(desc->desc2,\n-\t\t\t\tTX_NORMAL_DESC2, HL_B1L, tx_pkt->data_len);\n-\n-\t\trte_wmb();\n-\n-\t\t/* Mark it as a NORMAL descriptor */\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n-\t\t/* configure h/w Offload */\n-\t\tmask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n-\t\tif (mask == RTE_MBUF_F_TX_TCP_CKSUM ||\n-\t\t\t\tmask == RTE_MBUF_F_TX_UDP_CKSUM)\n-\t\t\tAXGMAC_SET_BITS_LE(desc->desc3,\n-\t\t\t\t\tTX_NORMAL_DESC3, CIC, 0x3);\n-\t\telse if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n-\t\t\tAXGMAC_SET_BITS_LE(desc->desc3,\n-\t\t\t\t\tTX_NORMAL_DESC3, CIC, 0x1);\n-\n-\t\trte_wmb();\n-\n-\t\t /* Set OWN bit */\n-\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n-\t\trte_wmb();\n-\n-\t\t/* Save mbuf */\n-\t\ttxq->sw_ring[idx] = tx_pkt;\n-\t\t/* Update current index*/\n-\t\ttxq->cur++;\n-\n-\t\ttx_pkt = tx_pkt->next;\n-\t}\n-\n-\t/* Set LD bit for the last descriptor */\n-\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);\n-\trte_wmb();\n-\n-\t/* Update stats */\n-\ttxq->bytes += pkt_len;\n-\n-\t/* Set OWN bit for the first descriptor */\n-\tdesc = &txq->desc[start_index];\n-\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n-\trte_wmb();\n-\n+ idx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n+ desc = &txq->desc[idx];\n+\n+\t\tif (tso)\n+\t\tdesc->baddr = rte_pktmbuf_iova_offset(mbuf,total_hdr_len);\n+\t\telse\n+ /* Update buffer address and length */\n+ desc->baddr = rte_mbuf_data_iova(tx_pkt);\n+\n+ AXGMAC_SET_BITS_LE(desc->desc2,\n+ TX_NORMAL_DESC2, HL_B1L, tx_pkt->data_len);\n+\n+ rte_wmb();\n+\n+ /* Mark it as a NORMAL descriptor */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n+ /* configure h/w Offload */\n+ mask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n+ if (mask == RTE_MBUF_F_TX_TCP_CKSUM ||\n+ mask == RTE_MBUF_F_TX_UDP_CKSUM)\n+ AXGMAC_SET_BITS_LE(desc->desc3,\n+ TX_NORMAL_DESC3, CIC, 0x3);\n+ else if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n+ AXGMAC_SET_BITS_LE(desc->desc3,\n+ TX_NORMAL_DESC3, CIC, 0x1);\n+\n+ rte_wmb();\n+\n+ /* Set OWN bit */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n+ rte_wmb();\n+\n+ /* Save mbuf */\n+ txq->sw_ring[idx] = tx_pkt;\n+ /* Update current index*/\n+ txq->cur++;\n+\n+ tx_pkt = tx_pkt->next;\n+ }\n+\n+ /* Set LD bit for the last descriptor */\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);\n+ rte_wmb();\n+\n+\tprintf(\"tso:: pkt_len = %d\\n\",pkt_len);\n+ /* Update stats */\n+ txq->bytes += pkt_len;\n+\n+ /* Set OWN bit for the first descriptor */\n+ desc = &txq->desc[start_index];\n+ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n+ rte_wmb();\n \treturn 0;\n }\n \n@@ -1077,6 +1150,8 @@ axgbe_xmit_pkts_seg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\tidx * sizeof(struct axgbe_tx_desc));\n \t/* Update tail reg with next immediate address to kick Tx DMA channel*/\n \tAXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);\n+\n+\n \ttxq->pkts += nb_pkt_sent;\n \treturn nb_pkt_sent;\n }\ndiff --git a/drivers/net/axgbe/axgbe_rxtx_vec_sse.c b/drivers/net/axgbe/axgbe_rxtx_vec_sse.c\nindex d95a446bef..7034d5737a 100644\n--- a/drivers/net/axgbe/axgbe_rxtx_vec_sse.c\n+++ b/drivers/net/axgbe/axgbe_rxtx_vec_sse.c\n@@ -65,6 +65,7 @@ axgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint16_t idx, nb_commit, loop, i;\n \tuint32_t tail_addr;\n \n+\tprintf(\"jesna::Inside axgbe_xmit_pkts_vec \\n\");\n \ttxq = (struct axgbe_tx_queue *)tx_queue;\n \tif (txq->nb_desc_free < txq->free_thresh) {\n \t\taxgbe_xmit_cleanup_vec(txq);\n", "prefixes": [ "v1", "3/3" ] }