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GET /api/patches/134011/?format=api
{ "id": 134011, "url": "http://patches.dpdk.org/api/patches/134011/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231109085547.1313003-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231109085547.1313003-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231109085547.1313003-2-suanmingm@nvidia.com", "date": "2023-11-09T08:55:46", "name": "[1/2] net/mlx5: fix missing flow rules for external SQ", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7dd77dfe0dce16752e8579bbc2e7d31e792e5df1", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231109085547.1313003-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 30213, "url": "http://patches.dpdk.org/api/series/30213/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30213", "date": "2023-11-09T08:55:45", "name": "net/mlx5: fix flow rules for external SQ", "version": 1, "mbox": "http://patches.dpdk.org/series/30213/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134011/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/134011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 19862432E1;\n\tThu, 9 Nov 2023 09:56:33 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B232C42E35;\n\tThu, 9 Nov 2023 09:56:28 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2073.outbound.protection.outlook.com [40.107.93.73])\n by mails.dpdk.org (Postfix) with ESMTP id 88EB742DEF;\n Thu, 9 Nov 2023 09:56:27 +0100 (CET)", "from DM6PR14CA0055.namprd14.prod.outlook.com (2603:10b6:5:18f::32)\n by PH0PR12MB7078.namprd12.prod.outlook.com (2603:10b6:510:21d::6) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.18; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 1/2] net/mlx5: fix missing flow rules for external SQ", "Date": "Thu, 9 Nov 2023 16:55:46 +0800", "Message-ID": "<20231109085547.1313003-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231109085547.1313003-1-suanmingm@nvidia.com>", "References": "<20231109085547.1313003-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF0000343C:EE_|PH0PR12MB7078:EE_", "X-MS-Office365-Filtering-Correlation-Id": "92c8f702-3c63-4fd1-5fa0-08dbe101c0c9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n gD4Yq4NMTWRS1Y1TrR/sfHHxSZN00RE2WY3k2w8mvKcY9pi7mLvcd1VcvXGbr/tlRSVxRKuDMyhh+ZimRxniIvN+Zpxs3mRFXOuflI9q0e7ZDalH9HQZgOiTacU+os8qry8++AKddR0td10JjPaHuoRYa1vt5BtT5KDODd0UqKWyQuOF++hGYXxRo1IQN5mwlJG/YQ8BnSxh5qdC8CTHa3UaFJ4Lv04rus5sJM34kH+9+WVhIuTo46Gm1/EfGMwFHmpw4h+CHxI4900NhOrplOzOXHNqiWqOE36wPJ0Ds94+fIJDcY3PmxU5Aqx/Yv+ZZFiCr7roRzdNNPXjKgprDatraTuau+7rhg6e4DYPddOhWm5xt7YQPBjYK9yDH8gKXfPARcgyehegPyhqnEG85MSswO9d+zdz6gF2tZk9XUYQmNe88CGp4+o776+YmR+KEpym8YWVy5HaZVP6LVvgHbhNtQpzvXibZLILKgfwzVaux2YwiUMK1mJfA46OeRaqMm6J1BhXeAQzxJmC3dTxb1hF8QMBb3MtCPVAmMtUwZ8LlGLygW4AUVcMxcvyXVaW8qUeUm1/R783RS3qLQSw1E6A/WSynHcDMvFCKjQVAV14k7Cav8tL9j0LZLivZlnZ79UbLyWkdd9iEMaLfqdVDb24ZxSAkvuQqyd73nXb/XQ32oLKEKds1cFxqtT9VdUbSuRwwAx7ewCoPgSN45e44OFYcMPz7NODyws8bov+28ngUznR4KrL4lvQjll9dBjuVIjbCq/bvt76h24odwnKzQ9MNFcPlabPaqJ2Hvou1Gs=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF0000343C.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7078", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nmlx5 PMD exposes a capability to register externally created SQs\nas if it was an SQ of a given representor port. Registration would\ncause a creation of control flow rules in FDB domain used to\nforward traffic betwen SQ and destination represented port.\n\nBefore this patch, if representor matching was enabled (device argument\nrepr_matching_en is equal to 1, default configuration), then during\nregistration of external SQs, mlx5 PMD would not create control flow\nrules in NIC Tx domain. This caused an issue with packet metadata.\nIf a packet sent on external SQ had packet metadata attached, then\nit would be lost when it would go from NIC Tx to FDB domain.\n\nWith representor matching disabled everything is working correctly,\nbecause in that mode there is a single global flow rule for preserving\npacket metadata. This flow rule matches whole traffic on NIC Tx domain.\nWith representor matching enabled, NIC Tx flow rules are created per SQ.\n\nThis patch fixes that behavior. If representor matching is enabled, then\nNIC Tx flow rules are created for each external SQ registered in\nrte_pmd_mlx5_external_sq_enable().\n\nThis patch also adds an ability to destroy SQ miss flow rules for a\ngiven port and SQ number. This is required for error rollback flow in\nrte_pmd_mlx5_external_sq_enable().\n\nFixes: 26e1eaf2dac4 (\"net/mlx5: support device control for E-Switch default rule\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 40 ++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 107 +++++++++++++++++++++++++++++---\n drivers/net/mlx5/mlx5_txq.c | 12 +++-\n 4 files changed, 149 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f5eacb2c67..45ad0701f1 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1705,10 +1705,50 @@ struct mlx5_obj_ops {\n \n #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)\n \n+enum mlx5_hw_ctrl_flow_type {\n+\tMLX5_HW_CTRL_FLOW_TYPE_GENERAL,\n+\tMLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,\n+\tMLX5_HW_CTRL_FLOW_TYPE_SQ_MISS,\n+\tMLX5_HW_CTRL_FLOW_TYPE_DEFAULT_JUMP,\n+\tMLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY,\n+\tMLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH,\n+\tMLX5_HW_CTRL_FLOW_TYPE_LACP_RX,\n+\tMLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,\n+};\n+\n+/** Additional info about control flow rule. */\n+struct mlx5_hw_ctrl_flow_info {\n+\t/** Determines the kind of control flow rule. */\n+\tenum mlx5_hw_ctrl_flow_type type;\n+\tunion {\n+\t\t/**\n+\t\t * If control flow is a SQ miss flow (root or not),\n+\t\t * then fields contains matching SQ number.\n+\t\t */\n+\t\tuint32_t esw_mgr_sq;\n+\t\t/**\n+\t\t * If control flow is a Tx representor matching,\n+\t\t * then fields contains matching SQ number.\n+\t\t */\n+\t\tuint32_t tx_repr_sq;\n+\t};\n+};\n+\n+/** Entry for tracking control flow rules in HWS. */\n struct mlx5_hw_ctrl_flow {\n \tLIST_ENTRY(mlx5_hw_ctrl_flow) next;\n+\t/**\n+\t * Owner device is a port on behalf of which flow rule was created.\n+\t *\n+\t * It's different from the port which really created the flow rule\n+\t * if and only if flow rule is created on transfer proxy port\n+\t * on behalf of representor port.\n+\t */\n \tstruct rte_eth_dev *owner_dev;\n+\t/** Pointer to flow rule handle. */\n \tstruct rte_flow *flow;\n+\t/** Additional information about the control flow rule. */\n+\tstruct mlx5_hw_ctrl_flow_info info;\n };\n \n /*\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 094be12715..d57b3b5465 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2875,6 +2875,8 @@ int mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *dev);\n \n int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t sqn);\n+int mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev,\n+\t\t\t\t\t uint32_t sqn);\n int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev);\n int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev);\n int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn);\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex f57126e2ff..d512889682 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -11341,6 +11341,8 @@ const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {\n * Pointer to flow rule actions.\n * @param action_template_idx\n * Index of an action template associated with @p table.\n+ * @param info\n+ * Additional info about control flow rule.\n *\n * @return\n * 0 on success, negative errno value otherwise and rte_errno set.\n@@ -11352,7 +11354,8 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,\n \t\t\t struct rte_flow_item items[],\n \t\t\t uint8_t item_template_idx,\n \t\t\t struct rte_flow_action actions[],\n-\t\t\t uint8_t action_template_idx)\n+\t\t\t uint8_t action_template_idx,\n+\t\t\t struct mlx5_hw_ctrl_flow_info *info)\n {\n \tstruct mlx5_priv *priv = proxy_dev->data->dev_private;\n \tuint32_t queue = CTRL_QUEUE_ID(priv);\n@@ -11399,6 +11402,10 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,\n \t}\n \tentry->owner_dev = owner_dev;\n \tentry->flow = flow;\n+\tif (info)\n+\t\tentry->info = *info;\n+\telse\n+\t\tentry->info.type = MLX5_HW_CTRL_FLOW_TYPE_GENERAL;\n \tLIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);\n \trte_spinlock_unlock(&priv->hw_ctrl_lock);\n \treturn 0;\n@@ -11602,6 +11609,10 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t};\n \tstruct rte_flow_item items[3] = { { 0 } };\n \tstruct rte_flow_action actions[3] = { { 0 } };\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,\n+\t\t.esw_mgr_sq = sqn,\n+\t};\n \tstruct rte_eth_dev *proxy_dev;\n \tstruct mlx5_priv *proxy_priv;\n \tuint16_t proxy_port_id = dev->data->port_id;\n@@ -11657,7 +11668,7 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t\t.type = RTE_FLOW_ACTION_TYPE_END,\n \t};\n \tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_root_tbl,\n-\t\t\t\t items, 0, actions, 0);\n+\t\t\t\t items, 0, actions, 0, &flow_info);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u failed to create root SQ miss flow rule for SQ %u, ret %d\",\n \t\t\tport_id, sqn, ret);\n@@ -11686,8 +11697,9 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \tactions[1] = (struct rte_flow_action){\n \t\t.type = RTE_FLOW_ACTION_TYPE_END,\n \t};\n+\tflow_info.type = MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS;\n \tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_tbl,\n-\t\t\t\t items, 0, actions, 0);\n+\t\t\t\t items, 0, actions, 0, &flow_info);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d\",\n \t\t\tport_id, sqn, ret);\n@@ -11696,6 +11708,58 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \treturn 0;\n }\n \n+static bool\n+flow_hw_is_matching_sq_miss_flow(struct mlx5_hw_ctrl_flow *cf,\n+\t\t\t\t struct rte_eth_dev *dev,\n+\t\t\t\t uint32_t sqn)\n+{\n+\tif (cf->owner_dev != dev)\n+\t\treturn false;\n+\tif (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)\n+\t\treturn true;\n+\tif (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)\n+\t\treturn true;\n+\treturn false;\n+}\n+\n+int\n+mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n+{\n+\tuint16_t port_id = dev->data->port_id;\n+\tuint16_t proxy_port_id = dev->data->port_id;\n+\tstruct rte_eth_dev *proxy_dev;\n+\tstruct mlx5_priv *proxy_priv;\n+\tstruct mlx5_hw_ctrl_flow *cf;\n+\tstruct mlx5_hw_ctrl_flow *cf_next;\n+\tint ret;\n+\n+\tret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Unable to pick transfer proxy port for port %u. Transfer proxy \"\n+\t\t\t \"port must be present for default SQ miss flow rules to exist.\",\n+\t\t\t port_id);\n+\t\treturn ret;\n+\t}\n+\tproxy_dev = &rte_eth_devices[proxy_port_id];\n+\tproxy_priv = proxy_dev->data->dev_private;\n+\tif (!proxy_priv->dr_ctx)\n+\t\treturn 0;\n+\tif (!proxy_priv->hw_esw_sq_miss_root_tbl ||\n+\t !proxy_priv->hw_esw_sq_miss_tbl)\n+\t\treturn 0;\n+\tcf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);\n+\twhile (cf != NULL) {\n+\t\tcf_next = LIST_NEXT(cf, next);\n+\t\tif (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {\n+\t\t\tclaim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));\n+\t\t\tLIST_REMOVE(cf, next);\n+\t\t\tmlx5_free(cf);\n+\t\t}\n+\t\tcf = cf_next;\n+\t}\n+\treturn 0;\n+}\n+\n int\n mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)\n {\n@@ -11724,6 +11788,9 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)\n \t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n \t\t}\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_JUMP,\n+\t};\n \tstruct rte_eth_dev *proxy_dev;\n \tstruct mlx5_priv *proxy_priv;\n \tuint16_t proxy_port_id = dev->data->port_id;\n@@ -11754,7 +11821,7 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)\n \t}\n \treturn flow_hw_create_ctrl_flow(dev, proxy_dev,\n \t\t\t\t\tproxy_priv->hw_esw_zero_tbl,\n-\t\t\t\t\titems, 0, actions, 0);\n+\t\t\t\t\titems, 0, actions, 0, &flow_info);\n }\n \n int\n@@ -11800,13 +11867,16 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)\n \t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n \t\t},\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY,\n+\t};\n \n \tMLX5_ASSERT(priv->master);\n \tif (!priv->dr_ctx || !priv->hw_tx_meta_cpy_tbl)\n \t\treturn 0;\n \treturn flow_hw_create_ctrl_flow(dev, dev,\n \t\t\t\t\tpriv->hw_tx_meta_cpy_tbl,\n-\t\t\t\t\teth_all, 0, copy_reg_action, 0);\n+\t\t\t\t\teth_all, 0, copy_reg_action, 0, &flow_info);\n }\n \n int\n@@ -11835,6 +11905,10 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH,\n+\t\t.tx_repr_sq = sqn,\n+\t};\n \n \t/* It is assumed that caller checked for representor matching. */\n \tMLX5_ASSERT(priv->sh->config.repr_matching);\n@@ -11860,7 +11934,7 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t\tactions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;\n \t}\n \treturn flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,\n-\t\t\t\t\titems, 0, actions, 0);\n+\t\t\t\t\titems, 0, actions, 0, &flow_info);\n }\n \n static uint32_t\n@@ -11975,6 +12049,9 @@ __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_RSS },\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,\n+\t};\n \n \tif (!eth_spec)\n \t\treturn -EINVAL;\n@@ -11988,7 +12065,7 @@ __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,\n \titems[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);\n \titems[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };\n \t/* Without VLAN filtering, only a single flow rule must be created. */\n-\treturn flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0);\n+\treturn flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info);\n }\n \n static int\n@@ -12004,6 +12081,9 @@ __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_RSS },\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,\n+\t};\n \tunsigned int i;\n \n \tif (!eth_spec)\n@@ -12026,7 +12106,7 @@ __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,\n \t\t};\n \n \t\titems[1].spec = &vlan_spec;\n-\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0))\n+\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info))\n \t\t\treturn -rte_errno;\n \t}\n \treturn 0;\n@@ -12044,6 +12124,9 @@ __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_RSS },\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,\n+\t};\n \tconst struct rte_ether_addr cmp = {\n \t\t.addr_bytes = \"\\x00\\x00\\x00\\x00\\x00\\x00\",\n \t};\n@@ -12067,7 +12150,7 @@ __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,\n \t\tif (!memcmp(mac, &cmp, sizeof(*mac)))\n \t\t\tcontinue;\n \t\tmemcpy(ð_spec.hdr.dst_addr.addr_bytes, mac->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0))\n+\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info))\n \t\t\treturn -rte_errno;\n \t}\n \treturn 0;\n@@ -12086,6 +12169,9 @@ __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_RSS },\n \t\t{ .type = RTE_FLOW_ACTION_TYPE_END },\n \t};\n+\tstruct mlx5_hw_ctrl_flow_info flow_info = {\n+\t\t.type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,\n+\t};\n \tconst struct rte_ether_addr cmp = {\n \t\t.addr_bytes = \"\\x00\\x00\\x00\\x00\\x00\\x00\",\n \t};\n@@ -12117,7 +12203,8 @@ __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,\n \t\t\t};\n \n \t\t\titems[1].spec = &vlan_spec;\n-\t\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0))\n+\t\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0,\n+\t\t\t\t\t\t &flow_info))\n \t\t\t\treturn -rte_errno;\n \t\t}\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex b584055fa8..ccdf2ffb14 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -1310,8 +1310,16 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)\n \t\treturn -rte_errno;\n \t}\n #ifdef HAVE_MLX5_HWS_SUPPORT\n-\tif (priv->sh->config.dv_flow_en == 2)\n-\t\treturn mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num);\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num))\n+\t\t\treturn -rte_errno;\n+\t\tif (priv->sh->config.repr_matching &&\n+\t\t mlx5_flow_hw_tx_repr_matching_flow(dev, sq_num)) {\n+\t\t\tmlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num);\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\treturn 0;\n+\t}\n #endif\n \tflow = mlx5_flow_create_devx_sq_miss_flow(dev, sq_num);\n \tif (flow > 0)\n", "prefixes": [ "1/2" ] }