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GET /api/patches/133841/?format=api
{ "id": 133841, "url": "http://patches.dpdk.org/api/patches/133841/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/7c61824f1ed1e720c974d1baadfa7c55578c0c4f.1699025423.git.gmuthukrishn@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<7c61824f1ed1e720c974d1baadfa7c55578c0c4f.1699025423.git.gmuthukrishn@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/7c61824f1ed1e720c974d1baadfa7c55578c0c4f.1699025423.git.gmuthukrishn@marvell.com", "date": "2023-11-03T15:38:03", "name": "[v3,3/3] test/dma: add SG copy tests", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c396fa1a18695a17b392c3a28342e559a6abdc43", "submitter": { "id": 2301, "url": "http://patches.dpdk.org/api/people/2301/?format=api", "name": "Gowrishankar Muthukrishnan", "email": "gmuthukrishn@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/7c61824f1ed1e720c974d1baadfa7c55578c0c4f.1699025423.git.gmuthukrishn@marvell.com/mbox/", "series": [ { "id": 30139, "url": "http://patches.dpdk.org/api/series/30139/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30139", "date": "2023-11-03T15:38:00", "name": "test/dma: add vchan reconfig and SG tests", "version": 3, "mbox": "http://patches.dpdk.org/series/30139/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133841/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133841/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BF02C4327C;\n\tFri, 3 Nov 2023 16:38:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 41BB142DDD;\n\tFri, 3 Nov 2023 16:38:23 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0734A42DDC\n for <dev@dpdk.org>; Fri, 3 Nov 2023 16:38:21 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3A3BVgxZ010483; Fri, 3 Nov 2023 08:38:21 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3u4m34awnu-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Fri, 03 Nov 2023 08:38:21 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 3 Nov 2023 08:38:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 3 Nov 2023 08:38:19 -0700", "from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34])\n by maili.marvell.com (Postfix) with ESMTP id 28C393F70BF;\n Fri, 3 Nov 2023 08:38:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=FRobPminORP3A83KhCIe0TfwbdqLDxN3h04uG4X0Lks=;\n b=Nz9LhKtf51wvM4zJ3t4rc86c9U37KN0Z0eixQiWy3VWjDgAWCbxPBx1iVOyQYcOH55Hg\n SVEx4Q+32ClCtQXqxrejP79UrUcSGE7MFJn1znlFAZjWcM5t6zAdZQshqdqr+nwEn7tD\n 8VrvYZarb31pjkkx7soOzmKtq5fP9enQJsSZC8FSnYAgixCA5KrWK0DgYWGAX/oQ7nTx\n uw6msu6PSFKt9Ox3mF0R2+KUPc7qJ9GHIo3HXt9ncL5GxnG5WM6FsACFyUg+FTQT0yNk\n IG1SjzRNbTTmsFk11D40sN+23KUTOay9/JjdTjQ9UOeEjZgDwwjHDV+JkO1ZQtbrUFCY hA==", "From": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<anoobj@marvell.com>, Chengwen Feng <fengchengwen@huawei.com>, \"Vamsi\n Attunuru\" <vattunuru@marvell.com>, Amit Prakash Shukla\n <amitprakashs@marvell.com>, Vidya Sagar Velumuri <vvelumuri@marvell.com>,\n Kevin Laatz <kevin.laatz@intel.com>, Bruce Richardson\n <bruce.richardson@intel.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>", "Subject": "[PATCH v3 3/3] test/dma: add SG copy tests", "Date": "Fri, 3 Nov 2023 21:08:03 +0530", "Message-ID": "\n <7c61824f1ed1e720c974d1baadfa7c55578c0c4f.1699025423.git.gmuthukrishn@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<cover.1699025423.git.gmuthukrishn@marvell.com>", "References": "<cover.1699025423.git.gmuthukrishn@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "J09bwy4CsUNN7eKZDvpYsztGNWnGPbtz", "X-Proofpoint-GUID": "J09bwy4CsUNN7eKZDvpYsztGNWnGPbtz", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-11-03_15,2023-11-02_03,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add scatter-gather copy tests.\n\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n---\n app/test/test_dmadev.c | 132 +++++++++++++++++++++++++++++-\n app/test/test_dmadev_api.c | 163 ++++++++++++++++++++++++++++++++++---\n app/test/test_dmadev_api.h | 2 +\n 3 files changed, 283 insertions(+), 14 deletions(-)", "diff": "diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c\nindex 780941fc1e..a2f3a7f999 100644\n--- a/app/test/test_dmadev.c\n+++ b/app/test/test_dmadev.c\n@@ -19,7 +19,7 @@\n #define ERR_RETURN(...) do { print_err(__func__, __LINE__, __VA_ARGS__); return -1; } while (0)\n \n #define TEST_RINGSIZE 512\n-#define COPY_LEN 1024\n+#define COPY_LEN 1032\n \n static struct rte_mempool *pool;\n static int16_t test_dev_id;\n@@ -396,6 +396,120 @@ test_stop_start(int16_t dev_id, uint16_t vchan)\n \treturn 0;\n }\n \n+static int\n+test_enqueue_sg_copies(int16_t dev_id, uint16_t vchan)\n+{\n+\tunsigned int src_len, dst_len, n_sge, len, i, j, k;\n+\tchar orig_src[COPY_LEN], orig_dst[COPY_LEN];\n+\tstruct rte_dma_info info = { 0 };\n+\tenum rte_dma_status_code status;\n+\tuint16_t id, n_src, n_dst;\n+\n+\tif (rte_dma_info_get(dev_id, &info) < 0)\n+\t\tERR_RETURN(\"Failed to get dev info\");\n+\n+\tn_sge = RTE_MIN(info.max_sges, TEST_SG_MAX);\n+\tlen = COPY_LEN;\n+\n+\tfor (n_src = 1; n_src <= n_sge; n_src++) {\n+\t\tsrc_len = len / n_src;\n+\t\tfor (n_dst = 1; n_dst <= n_sge; n_dst++) {\n+\t\t\tdst_len = len / n_dst;\n+\n+\t\t\tstruct rte_dma_sge sg_src[n_sge], sg_dst[n_sge];\n+\t\t\tstruct rte_mbuf *src[n_sge], *dst[n_sge];\n+\t\t\tchar *src_data[n_sge], *dst_data[n_sge];\n+\n+\t\t\tfor (i = 0 ; i < COPY_LEN; i++)\n+\t\t\t\torig_src[i] = rte_rand() & 0xFF;\n+\n+\t\t\tmemset(orig_dst, 0, COPY_LEN);\n+\n+\t\t\tfor (i = 0; i < n_src; i++) {\n+\t\t\t\tsrc[i] = rte_pktmbuf_alloc(pool);\n+\t\t\t\tRTE_ASSERT(src[i] != NULL);\n+\t\t\t\tsg_src[i].addr = rte_pktmbuf_iova(src[i]);\n+\t\t\t\tsg_src[i].length = src_len;\n+\t\t\t\tsrc_data[i] = rte_pktmbuf_mtod(src[i], char *);\n+\t\t\t}\n+\n+\t\t\tfor (k = 0; k < n_dst; k++) {\n+\t\t\t\tdst[k] = rte_pktmbuf_alloc(pool);\n+\t\t\t\tRTE_ASSERT(dst[k] != NULL);\n+\t\t\t\tsg_dst[k].addr = rte_pktmbuf_iova(dst[k]);\n+\t\t\t\tsg_dst[k].length = dst_len;\n+\t\t\t\tdst_data[k] = rte_pktmbuf_mtod(dst[k], char *);\n+\t\t\t}\n+\n+\t\t\tfor (i = 0; i < n_src; i++) {\n+\t\t\t\tfor (j = 0; j < src_len; j++)\n+\t\t\t\t\tsrc_data[i][j] = orig_src[i * src_len + j];\n+\t\t\t}\n+\n+\t\t\tfor (k = 0; k < n_dst; k++)\n+\t\t\t\tmemset(dst_data[k], 0, dst_len);\n+\n+\t\t\tprintf(\"\\tsrc segs: %2d [seg len: %4d] - dst segs: %2d [seg len : %4d]\\n\",\n+\t\t\t\tn_src, src_len, n_dst, dst_len);\n+\n+\t\t\tid = rte_dma_copy_sg(dev_id, vchan, sg_src, sg_dst, n_src, n_dst,\n+\t\t\t\t\t RTE_DMA_OP_FLAG_SUBMIT);\n+\n+\t\t\tif (id != id_count)\n+\t\t\t\tERR_RETURN(\"Error with rte_dma_copy_sg, got %u, expected %u\\n\",\n+\t\t\t\t\tid, id_count);\n+\n+\t\t\t/* Give time for copy to finish, then check it was done */\n+\t\t\tawait_hw(dev_id, vchan);\n+\n+\t\t\tfor (k = 0; k < n_dst; k++)\n+\t\t\t\tmemcpy((&orig_dst[0] + k * dst_len), dst_data[k], dst_len);\n+\n+\t\t\tif (memcmp(orig_src, orig_dst, COPY_LEN))\n+\t\t\t\tERR_RETURN(\"Data mismatch\");\n+\n+\t\t\t/* Verify completion */\n+\t\t\tid = ~id;\n+\t\t\tif (rte_dma_completed(dev_id, vchan, 1, &id, NULL) != 1)\n+\t\t\t\tERR_RETURN(\"Error with rte_dma_completed\\n\");\n+\n+\t\t\t/* Verify expected index(id_count) */\n+\t\t\tif (id != id_count)\n+\t\t\t\tERR_RETURN(\"Error:incorrect job id received, %u [expected %u]\\n\",\n+\t\t\t\t\t\tid, id_count);\n+\n+\t\t\t/* Check for completed and id when no job done */\n+\t\t\tid = ~id;\n+\t\t\tif (rte_dma_completed(dev_id, vchan, 1, &id, NULL) != 0)\n+\t\t\t\tERR_RETURN(\"Error with rte_dma_completed when no job done\\n\");\n+\n+\t\t\tif (id != id_count)\n+\t\t\t\tERR_RETURN(\"Error:incorrect job id received when no job done, %u [expected %u]\\n\",\n+\t\t\t\t\t id, id_count);\n+\n+\t\t\t/* Check for completed_status and id when no job done */\n+\t\t\tid = ~id;\n+\t\t\tif (rte_dma_completed_status(dev_id, vchan, 1, &id, &status) != 0)\n+\t\t\t\tERR_RETURN(\"Error with rte_dma_completed_status when no job done\\n\");\n+\t\t\tif (id != id_count)\n+\t\t\t\tERR_RETURN(\"Error:incorrect job id received when no job done, %u [expected %u]\\n\",\n+\t\t\t\t\t\tid, 0);\n+\n+\t\t\tfor (i = 0; i < n_src; i++)\n+\t\t\t\trte_pktmbuf_free(src[i]);\n+\t\t\tfor (i = 0; i < n_dst; i++)\n+\t\t\t\trte_pktmbuf_free(dst[i]);\n+\n+\t\t\t/* Verify that completion returns nothing more */\n+\t\t\tif (rte_dma_completed(dev_id, 0, 1, NULL, NULL) != 0)\n+\t\t\t\tERR_RETURN(\"Error with rte_dma_completed in empty check\\n\");\n+\n+\t\t\tid_count++;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n /* Failure handling test cases - global macros and variables for those tests*/\n #define COMP_BURST_SZ\t16\n #define OPT_FENCE(idx) ((fence && idx == 8) ? RTE_DMA_OP_FLAG_FENCE : 0)\n@@ -1003,7 +1117,7 @@ test_dmadev_setup(void)\n \t\t\tTEST_RINGSIZE * 2, /* n == num elements */\n \t\t\t32, /* cache size */\n \t\t\t0, /* priv size */\n-\t\t\t2048, /* data room size */\n+\t\t\tCOPY_LEN + RTE_PKTMBUF_HEADROOM, /* data room size */\n \t\t\tinfo.numa_node);\n \tif (pool == NULL)\n \t\tERR_RETURN(\"Error with mempool creation\\n\");\n@@ -1026,6 +1140,7 @@ test_dmadev_instance(int16_t dev_id)\n #define CHECK_ERRS true\n \tenum {\n \t\t TEST_COPY = 0,\n+\t\t TEST_COPY_SG,\n \t\t TEST_START,\n \t\t TEST_BURST,\n \t\t TEST_ERR,\n@@ -1060,6 +1175,13 @@ test_dmadev_instance(int16_t dev_id)\n \tparam[TEST_COPY].vchan = vchan;\n \tparam[TEST_COPY].check_err_stats = CHECK_ERRS;\n \n+\tparam[TEST_COPY_SG].printable = \"copy\";\n+\tparam[TEST_COPY_SG].test_fn = test_enqueue_sg_copies;\n+\tparam[TEST_COPY_SG].iterations = 1;\n+\tparam[TEST_COPY_SG].dev_id = dev_id;\n+\tparam[TEST_COPY_SG].vchan = vchan;\n+\tparam[TEST_COPY_SG].check_err_stats = CHECK_ERRS;\n+\n \tparam[TEST_START].printable = \"stop-start\";\n \tparam[TEST_START].test_fn = test_stop_start;\n \tparam[TEST_START].iterations = 1;\n@@ -1122,6 +1244,12 @@ test_dmadev_instance(int16_t dev_id)\n \t/* run tests stopping/starting devices and check jobs still work after restart */\n \tts->unit_test_cases[TEST_START].enabled = 1;\n \n+\t/* run SG test cases */\n+\tif ((dev_info.dev_capa & RTE_DMA_CAPA_OPS_COPY_SG) == 0)\n+\t\tprintf(\"DMA Dev %u: No SG support, skipping SG copy tests\\n\", dev_id);\n+\telse\n+\t\tts->unit_test_cases[TEST_COPY_SG].enabled = 1;\n+\n \t/* run some burst capacity tests */\n \tts->unit_test_cases[TEST_BURST].setup = test_dmadev_burst_setup;\n \tts->unit_test_cases[TEST_BURST].enabled = 1;\ndiff --git a/app/test/test_dmadev_api.c b/app/test/test_dmadev_api.c\nindex aa07d2b359..37e43c9336 100644\n--- a/app/test/test_dmadev_api.c\n+++ b/app/test/test_dmadev_api.c\n@@ -10,6 +10,7 @@\n #include <rte_dmadev.h>\n \n #include \"test.h\"\n+#include \"test_dmadev_api.h\"\n \n extern int test_dma_api(uint16_t dev_id);\n \n@@ -21,36 +22,62 @@ static int16_t invalid_dev_id;\n \n static char *src;\n static char *dst;\n+static char *src_sg[TEST_SG_MAX];\n+static char *dst_sg[TEST_SG_MAX];\n \n static int\n testsuite_setup(void)\n {\n \tinvalid_dev_id = -1;\n-\n-\tsrc = rte_malloc(\"dmadev_test_src\", TEST_MEMCPY_SIZE, 0);\n-\tif (src == NULL)\n-\t\treturn -ENOMEM;\n-\tdst = rte_malloc(\"dmadev_test_dst\", TEST_MEMCPY_SIZE, 0);\n-\tif (dst == NULL) {\n-\t\trte_free(src);\n-\t\tsrc = NULL;\n-\t\treturn -ENOMEM;\n+\tint i, rc = 0;\n+\n+\tfor (i = 0; i < TEST_SG_MAX; i++) {\n+\t\tsrc_sg[i] = rte_malloc(\"dmadev_test_src\", TEST_MEMCPY_SIZE, 0);\n+\t\tif (src_sg[i] == NULL) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tdst_sg[i] = rte_malloc(\"dmadev_test_dst\", TEST_MEMCPY_SIZE, 0);\n+\t\tif (dst_sg[i] == NULL) {\n+\t\t\trte_free(src_sg[i]);\n+\t\t\tsrc_sg[i] = NULL;\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n \t}\n \n+\tsrc = src_sg[0];\n+\tdst = dst_sg[0];\n+\n \t/* Set dmadev log level to critical to suppress unnecessary output\n \t * during API tests.\n \t */\n \trte_log_set_level_pattern(\"lib.dmadev\", RTE_LOG_CRIT);\n \n-\treturn 0;\n+\treturn rc;\n+exit:\n+\twhile (--i >= 0) {\n+\t\trte_free(src_sg[i]);\n+\t\trte_free(dst_sg[i]);\n+\t}\n+\n+\treturn rc;\n }\n \n static void\n testsuite_teardown(void)\n {\n-\trte_free(src);\n+\tint i;\n+\n+\tfor (i = 0; i < TEST_SG_MAX; i++) {\n+\t\trte_free(src_sg[i]);\n+\t\tsrc_sg[i] = NULL;\n+\t\trte_free(dst_sg[i]);\n+\t\tdst_sg[i] = NULL;\n+\t}\n+\n \tsrc = NULL;\n-\trte_free(dst);\n \tdst = NULL;\n \t/* Ensure the dmadev is stopped. */\n \trte_dma_stop(test_dev_id);\n@@ -437,6 +464,37 @@ verify_memory(void)\n \treturn 0;\n }\n \n+static void\n+sg_memory_setup(int n)\n+{\n+\tint i, j;\n+\n+\tfor (i = 0; i < n; i++) {\n+\t\tfor (j = 0; j < TEST_MEMCPY_SIZE; j++)\n+\t\t\tsrc_sg[i][j] = (char)j;\n+\n+\t\tmemset(dst_sg[i], 0, TEST_MEMCPY_SIZE);\n+\t}\n+}\n+\n+static int\n+sg_memory_verify(int n)\n+{\n+\tint i, j;\n+\n+\tfor (i = 0; i < n; i++) {\n+\t\tfor (j = 0; j < TEST_MEMCPY_SIZE; j++) {\n+\t\t\tif (src_sg[i][j] == dst_sg[i][j])\n+\t\t\t\tcontinue;\n+\n+\t\t\tRTE_TEST_ASSERT_EQUAL(src_sg[i][j], dst_sg[i][j], \"Failed to copy memory, %d %d\",\n+\t\t\t\tsrc_sg[i][j], dst_sg[i][j]);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n test_dma_completed(void)\n {\n@@ -551,6 +609,86 @@ test_dma_completed_status(void)\n \treturn TEST_SUCCESS;\n }\n \n+static int\n+test_dma_sg(void)\n+{\n+\tstruct rte_dma_sge src_sge[TEST_SG_MAX], dst_sge[TEST_SG_MAX];\n+\tstruct rte_dma_info dev_info = { 0 };\n+\tuint16_t last_idx = -1;\n+\tbool has_error = true;\n+\tint n_sge, i, ret;\n+\tuint16_t cpl_ret;\n+\n+\tret = rte_dma_info_get(test_dev_id, &dev_info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info, %d\", ret);\n+\n+\tif ((dev_info.dev_capa & RTE_DMA_CAPA_OPS_COPY_SG) == 0)\n+\t\treturn TEST_SKIPPED;\n+\n+\tn_sge = RTE_MIN(dev_info.max_sges, TEST_SG_MAX);\n+\n+\tret = setup_vchan(1);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup one vchan, %d\", ret);\n+\n+\tret = rte_dma_start(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to start, %d\", ret);\n+\n+\tfor (i = 0; i < n_sge; i++) {\n+\t\tsrc_sge[i].addr = rte_malloc_virt2iova(src_sg[i]);\n+\t\tsrc_sge[i].length = TEST_MEMCPY_SIZE;\n+\t\tdst_sge[i].addr = rte_malloc_virt2iova(dst_sg[i]);\n+\t\tdst_sge[i].length = TEST_MEMCPY_SIZE;\n+\t}\n+\n+\tsg_memory_setup(n_sge);\n+\n+\t/* Check enqueue without submit */\n+\tret = rte_dma_copy_sg(test_dev_id, 0, src_sge, dst_sge, n_sge, n_sge, 0);\n+\tRTE_TEST_ASSERT_EQUAL(ret, 0, \"Failed to enqueue copy, %d\", ret);\n+\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\n+\tcpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 0, \"Failed to get completed\");\n+\n+\t/* Check DMA submit */\n+\tret = rte_dma_submit(test_dev_id, 0);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to submit, %d\", ret);\n+\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\n+\tcpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to get completed\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 0, \"Last idx should be zero, %u\", last_idx);\n+\tRTE_TEST_ASSERT_EQUAL(has_error, false, \"Should have no error\");\n+\n+\tret = sg_memory_verify(n_sge);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to verify memory\");\n+\n+\tsg_memory_setup(n_sge);\n+\n+\t/* Check for enqueue with submit */\n+\tret = rte_dma_copy_sg(test_dev_id, 0, src_sge, dst_sge, n_sge, n_sge,\n+\t\t\t RTE_DMA_OP_FLAG_SUBMIT);\n+\tRTE_TEST_ASSERT_EQUAL(ret, 1, \"Failed to enqueue copy, %d\", ret);\n+\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\n+\tcpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to get completed\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 1, \"Last idx should be 1, %u\", last_idx);\n+\tRTE_TEST_ASSERT_EQUAL(has_error, false, \"Should have no error\");\n+\n+\tret = sg_memory_verify(n_sge);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to verify memory\");\n+\n+\t/* Stop dmadev to make sure dmadev to a known state */\n+\tret = rte_dma_stop(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to stop, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n static struct unit_test_suite dma_api_testsuite = {\n \t.suite_name = \"DMA API Test Suite\",\n \t.setup = testsuite_setup,\n@@ -568,6 +706,7 @@ static struct unit_test_suite dma_api_testsuite = {\n \t\tTEST_CASE(test_dma_dump),\n \t\tTEST_CASE(test_dma_completed),\n \t\tTEST_CASE(test_dma_completed_status),\n+\t\tTEST_CASE(test_dma_sg),\n \t\tTEST_CASES_END()\n \t}\n };\ndiff --git a/app/test/test_dmadev_api.h b/app/test/test_dmadev_api.h\nindex 33fbc5bd41..10ab925f80 100644\n--- a/app/test/test_dmadev_api.h\n+++ b/app/test/test_dmadev_api.h\n@@ -2,4 +2,6 @@\n * Copyright(c) 2021 HiSilicon Limited\n */\n \n+#define TEST_SG_MAX 4\n+\n int test_dma_api(uint16_t dev_id);\n", "prefixes": [ "v3", "3/3" ] }