Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/133709/?format=api
{ "id": 133709, "url": "http://patches.dpdk.org/api/patches/133709/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231101044419.732726-14-rongweil@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231101044419.732726-14-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231101044419.732726-14-rongweil@nvidia.com", "date": "2023-11-01T04:44:19", "name": "[v4,13/13] net/mlx5/hws: add stc reparse support for srv6 push pop", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d989293757b16d3fd7fca6d7b83d229949793252", "submitter": { "id": 2223, "url": "http://patches.dpdk.org/api/people/2223/?format=api", "name": "Rongwei Liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231101044419.732726-14-rongweil@nvidia.com/mbox/", "series": [ { "id": 30088, "url": "http://patches.dpdk.org/api/series/30088/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30088", "date": "2023-11-01T04:44:06", "name": "support IPv6 push remove action", "version": 4, "mbox": "http://patches.dpdk.org/series/30088/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133709/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133709/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 562FA43258;\n\tWed, 1 Nov 2023 05:46:35 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A70E040E54;\n\tWed, 1 Nov 2023 05:45:26 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2061.outbound.protection.outlook.com [40.107.243.61])\n by mails.dpdk.org (Postfix) with ESMTP id A5B8C42D96\n for <dev@dpdk.org>; Wed, 1 Nov 2023 05:45:24 +0100 (CET)", "from CY5PR13CA0032.namprd13.prod.outlook.com (2603:10b6:930:11::6)\n by MN0PR12MB6174.namprd12.prod.outlook.com (2603:10b6:208:3c5::19) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.22; Wed, 1 Nov\n 2023 04:45:22 +0000", "from CY4PEPF0000E9CE.namprd03.prod.outlook.com\n (2603:10b6:930:11:cafe::c5) by CY5PR13CA0032.outlook.office365.com\n (2603:10b6:930:11::6) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.15 via Frontend\n Transport; Wed, 1 Nov 2023 04:45:22 +0000", "from mail.nvidia.com (216.228.117.161) by\n CY4PEPF0000E9CE.mail.protection.outlook.com (10.167.241.141) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6954.19 via Frontend Transport; Wed, 1 Nov 2023 04:45:21 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct\n 2023 21:45:09 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct\n 2023 21:45:07 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=JkrCpA1cED5R74TlMYP7DovQgt2lD4uC669cSiFiIVN4/POYhcjI2QPIscZPqHujEqVus5FWxexiaxyHd1xMrctzV6dtH3jcbx84NwwCHaeJ26AtoK1QnGtHhxBTmTP63fNxEV0tfXV4NF+vHsmk5mQv92KQcOjIocvux5uDb+nvRs9zsQ7YIrzjLW5T51AZM4Y5iEqHxDG4E8EHtC/oBLy34jdGjY7T4gkpRqHKb+ZVffz0udFLQFk3kR0TfX2QdG7+QRl6ePzNAehrrXQA//ZPBC1iqcbMnbKMh2oGmwudqP39NI8LokGCuAVklO6VZ+5X/uicUdQ7b8yg4oPoGQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=QUqiHoWUVwN+cqlv4jPDulGpPr5YkmR3yObQvkJYpXQ=;\n b=Mvb2SNn+0SHKtq9Tq6vFQwCXyo3SGM9H1TMPs/g7w+flLPx34WBSQK9EOKDEL3x2NN7zJp7cSeGnmMko5ffZR7fQTFj+vT3jVAqbaBl6zIJ7ycxNzjFzRbESOL0rt1WML6bLffOWHfu0L5k1Zjw2Jyv6Vuyp032EyVHFTT9s53sAaOcqrjbwktUMUX/HozjBAdFzIANAt96s0eR6whtmTlZoUwvNfprv9oqGDupLtqUAUeBDUqraZY3nX1MhP/u8IRkzDFQxhnLXxS9bOnnb/Xq5vAwHXHJaxvCSVcYvSMKn8USqLy5d28pu0O3obBNHtuXyUlMznu2dFOfWktrW2A==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=QUqiHoWUVwN+cqlv4jPDulGpPr5YkmR3yObQvkJYpXQ=;\n b=XHvJaFBZGaiLwM1YT6eUCHXfoO8pxe/bEKFCG1Ofh3QIxWfDUhsL72qJbhogFv4H6QJWn8XOzT0kloeNQvlhtlr+Gg7rOOhyvfDNkj7ReeMSpiEmruESqoquUQrz7f6a7G0Bk0hic6gZB2/8mMmnIdJvpKFP2ZrBgaXxVLU9xEJnkXNyacW0C/hPy2x9yfS6RCMH9ZGF4wzZ6508VFQx/JdbIPL6SpfxH56LdOhpCijjVq+4PyvZ/TFnmlNwADq7lXls8v+mPuOGud1Dzwp9FJN/pdFxEOZSvS0GQFEV12YeUhEZxbF7r1WGvxhOhMufUaACLbYrncwy1wRbfOqtJA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Rongwei Liu <rongweil@nvidia.com>", "To": "<dev@dpdk.org>, <matan@nvidia.com>, <viacheslavo@nvidia.com>,\n <orika@nvidia.com>, <suanmingm@nvidia.com>, <thomas@monjalon.net>", "CC": "Erez Shitrit <erezsh@nvidia.com>", "Subject": "[PATCH v4 13/13] net/mlx5/hws: add stc reparse support for srv6 push\n pop", "Date": "Wed, 1 Nov 2023 06:44:19 +0200", "Message-ID": "<20231101044419.732726-14-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20231101044419.732726-1-rongweil@nvidia.com>", "References": "<20231031105131.441078-1-rongweil@nvidia.com>\n <20231101044419.732726-1-rongweil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9CE:EE_|MN0PR12MB6174:EE_", "X-MS-Office365-Filtering-Correlation-Id": "155b9a85-ac4b-4e82-731e-08dbda955b67", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n dk4MldTObgKH3pf/6O0roumlYfDRfWYcIPeXwhcXzZhnXyptXWPrfbRCNuKxCeVbsJgIiMoJ7q5CIE5tACvZ6uqfB4E86FWlqRVDWEWnFluYfQQIUZU0j0u/ofnYl6Y/8oe4KxXCJ7COpKHoQcfP3XXxQKcDtuhVSbV/78KRXOGQLJ4t0RBKaQmr0lsMTaaaBPMn+W+291sgM5fNGNG7Wim6HlKSvZXS/Di4oNPWiSQU97GUDNDwQyfSay/ZEed2ercvdygQJWHegRjkC7wqoen2AuNnfdMFSFejPxgdZg1AvmqhM/hkV+gwIaaBi+wsn366CoCbAvXznwC14e2QObYDN8Gv+KfRqLSYvTIrTYp+neqoNuf2xbcddvze+zP3vZVb+K/I1zudhhgS3eCn+S254XLRwR29NWWcb/+wFlT9kDivLb1VQyF9f9oFlgR7UmmxAvLjbtY/B19sMsqex+nnAPnjLduPyEAXnfToD66s3qdGf7p4SNQ9u+wtYRY1T1jStEX3MUj0KD1JBBowg3chG+pQrmaPQn8NKDp4BHQdrTz6fPVHa0UiuC9IpMYl6ENzctPr29sYYYOi0M2zj9S72x54Loc09CiCubbAZwzf4ZSMb1QBueqQFFbEshp+xmCzLDK4+O8pCfYckIZVZrZgg4ZbMmvMwFPNG6b3L2JU/V7u66rMkSv7tal3Ad1gs2wT2POGsrdQYP6hXnXf26YRUl9BV3lwSxS9kr+RqZtvNVsDdhUWaxlT9s4IR9XS10rXm/y7pOMCdlCrBqJbwU+ciax3XyaUPpx3koIxXSs=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(136003)(39860400002)(346002)(376002)(230922051799003)(230273577357003)(230173577357003)(186009)(64100799003)(451199024)(82310400011)(1800799009)(46966006)(36840700001)(40470700004)(7696005)(426003)(40480700001)(55016003)(336012)(83380400001)(6666004)(478600001)(40460700003)(86362001)(5660300002)(6286002)(107886003)(16526019)(36756003)(4326008)(2616005)(26005)(1076003)(8936002)(41300700001)(316002)(8676002)(356005)(2906002)(82740400003)(110136005)(30864003)(7636003)(36860700001)(70586007)(47076005)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Nov 2023 04:45:21.9983 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 155b9a85-ac4b-4e82-731e-08dbda955b67", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9CE.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB6174", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "After pushing/popping srv6 into/from IPv6 packets, the checksum\nneeds to be correct.\n\nIn order to achieve this, there is a need to control each STE' reparse\nbehavior(CX7 and above). Add two more flags enumeration definitions to\nallow external control of reparse property in stc.\n\n1. Push\n a. 1st STE, insert header action, reparse ignored(default reparse\n always)\n b. 2nd STE, modify IPv6 protocol, reparse always as default.\n c. 3rd STE, modify header list, reparse always(default reparse\n ignored)\n2. Pop\n a. 1st STE, modify header list, reparse always(default reparse\n ignored)\n b. 2nd STE, modify header list, reparse always(default reparse\n ignored)\n c. 3rd STE, modify IPv6 protocol, reparse ignored(default reparse\n always); remove header action, reparse always as default.\n\nFor CX6Lx and CX6Dx, the reparse behavior is controlled by RTC as\nalways. Only pop action can work well.\n\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nReviewed-by: Erez Shitrit <erezsh@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_action.c | 115 +++++++++++++++++++--------\n drivers/net/mlx5/hws/mlx5dr_action.h | 7 ++\n 2 files changed, 87 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex 43a65bdfd1..862ee3e332 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -552,6 +552,7 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action,\n \tcase MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:\n \tcase MLX5DR_ACTION_TYP_MODIFY_HDR:\n \t\tattr->action_offset = MLX5DR_ACTION_OFFSET_DW6;\n+\t\tattr->reparse_mode = MLX5_IFC_STC_REPARSE_IGNORE;\n \t\tif (action->modify_header.require_reparse)\n \t\t\tattr->reparse_mode = MLX5_IFC_STC_REPARSE_ALWAYS;\n \n@@ -590,9 +591,12 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action,\n \tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:\n \tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:\n \tcase MLX5DR_ACTION_TYP_INSERT_HEADER:\n+\t\tattr->reparse_mode = MLX5_IFC_STC_REPARSE_ALWAYS;\n+\t\tif (!action->reformat.require_reparse)\n+\t\t\tattr->reparse_mode = MLX5_IFC_STC_REPARSE_IGNORE;\n+\n \t\tattr->action_type = MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT;\n \t\tattr->action_offset = MLX5DR_ACTION_OFFSET_DW6;\n-\t\tattr->reparse_mode = MLX5_IFC_STC_REPARSE_ALWAYS;\n \t\tattr->insert_header.encap = action->reformat.encap;\n \t\tattr->insert_header.insert_anchor = action->reformat.anchor;\n \t\tattr->insert_header.arg_id = action->reformat.arg_obj->id;\n@@ -1301,7 +1305,7 @@ static int\n mlx5dr_action_handle_insert_with_ptr(struct mlx5dr_action *action,\n \t\t\t\t uint8_t num_of_hdrs,\n \t\t\t\t struct mlx5dr_action_reformat_header *hdrs,\n-\t\t\t\t uint32_t log_bulk_sz)\n+\t\t\t\t uint32_t log_bulk_sz, uint32_t reparse)\n {\n \tstruct mlx5dr_devx_obj *arg_obj;\n \tsize_t max_sz = 0;\n@@ -1338,6 +1342,11 @@ mlx5dr_action_handle_insert_with_ptr(struct mlx5dr_action *action,\n \t\t\taction[i].reformat.encap = 1;\n \t\t}\n \n+\t\tif (likely(reparse == MLX5DR_ACTION_STC_REPARSE_DEFAULT))\n+\t\t\taction[i].reformat.require_reparse = true;\n+\t\telse if (reparse == MLX5DR_ACTION_STC_REPARSE_ON)\n+\t\t\taction[i].reformat.require_reparse = true;\n+\n \t\tret = mlx5dr_action_create_stcs(&action[i], NULL);\n \t\tif (ret) {\n \t\t\tDR_LOG(ERR, \"Failed to create stc for reformat\");\n@@ -1374,7 +1383,8 @@ mlx5dr_action_handle_l2_to_tunnel_l3(struct mlx5dr_action *action,\n \tret = mlx5dr_action_handle_insert_with_ptr(action,\n \t\t\t\t\t\t num_of_hdrs,\n \t\t\t\t\t\t hdrs,\n-\t\t\t\t\t\t log_bulk_sz);\n+\t\t\t\t\t\t log_bulk_sz,\n+\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_DEFAULT);\n \tif (ret)\n \t\tgoto put_shared_stc;\n \n@@ -1517,7 +1527,8 @@ mlx5dr_action_create_reformat_hws(struct mlx5dr_action *action,\n \t\tret = mlx5dr_action_create_stcs(action, NULL);\n \t\tbreak;\n \tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:\n-\t\tret = mlx5dr_action_handle_insert_with_ptr(action, num_of_hdrs, hdrs, bulk_size);\n+\t\tret = mlx5dr_action_handle_insert_with_ptr(action, num_of_hdrs, hdrs, bulk_size,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_DEFAULT);\n \t\tbreak;\n \tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:\n \t\tret = mlx5dr_action_handle_l2_to_tunnel_l3(action, num_of_hdrs, hdrs, bulk_size);\n@@ -1625,7 +1636,8 @@ static int\n mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action,\n \t\t\t\t uint8_t num_of_patterns,\n \t\t\t\t struct mlx5dr_action_mh_pattern *pattern,\n-\t\t\t\t uint32_t log_bulk_size)\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t reparse)\n {\n \tstruct mlx5dr_devx_obj *pat_obj, *arg_obj = NULL;\n \tstruct mlx5dr_context *ctx = action->ctx;\n@@ -1659,8 +1671,12 @@ mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action,\n \t\taction[i].modify_header.num_of_patterns = num_of_patterns;\n \t\taction[i].modify_header.max_num_of_actions = max_mh_actions;\n \t\taction[i].modify_header.num_of_actions = num_actions;\n-\t\taction[i].modify_header.require_reparse =\n-\t\t\tmlx5dr_pat_require_reparse(pattern[i].data, num_actions);\n+\n+\t\tif (likely(reparse == MLX5DR_ACTION_STC_REPARSE_DEFAULT))\n+\t\t\taction[i].modify_header.require_reparse =\n+\t\t\t\tmlx5dr_pat_require_reparse(pattern[i].data, num_actions);\n+\t\telse if (reparse == MLX5DR_ACTION_STC_REPARSE_ON)\n+\t\t\taction[i].modify_header.require_reparse = true;\n \n \t\tif (num_actions == 1) {\n \t\t\tpat_obj = NULL;\n@@ -1703,12 +1719,12 @@ mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action,\n \treturn rte_errno;\n }\n \n-struct mlx5dr_action *\n-mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n-\t\t\t\t uint8_t num_of_patterns,\n-\t\t\t\t struct mlx5dr_action_mh_pattern *patterns,\n-\t\t\t\t uint32_t log_bulk_size,\n-\t\t\t\t uint32_t flags)\n+static struct mlx5dr_action *\n+mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx,\n+\t\t\t\t\t uint8_t num_of_patterns,\n+\t\t\t\t\t struct mlx5dr_action_mh_pattern *patterns,\n+\t\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t\t uint32_t flags, uint32_t reparse)\n {\n \tstruct mlx5dr_action *action;\n \tint ret;\n@@ -1756,7 +1772,8 @@ mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n \tret = mlx5dr_action_create_modify_header_hws(action,\n \t\t\t\t\t\t num_of_patterns,\n \t\t\t\t\t\t patterns,\n-\t\t\t\t\t\t log_bulk_size);\n+\t\t\t\t\t\t log_bulk_size,\n+\t\t\t\t\t\t reparse);\n \tif (ret)\n \t\tgoto free_action;\n \n@@ -1767,6 +1784,17 @@ mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n \treturn NULL;\n }\n \n+struct mlx5dr_action *\n+mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n+\t\t\t\t uint8_t num_of_patterns,\n+\t\t\t\t struct mlx5dr_action_mh_pattern *patterns,\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t flags)\n+{\n+\treturn mlx5dr_action_create_modify_header_reparse(ctx, num_of_patterns, patterns,\n+\t\t\t\t\t\t\t log_bulk_size, flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_DEFAULT);\n+}\n static struct mlx5dr_devx_obj *\n mlx5dr_action_dest_array_process_reformat(struct mlx5dr_context *ctx,\n \t\t\t\t\t enum mlx5dr_action_type type,\n@@ -2007,12 +2035,12 @@ mlx5dr_action_create_dest_root(struct mlx5dr_context *ctx,\n \treturn NULL;\n }\n \n-struct mlx5dr_action *\n-mlx5dr_action_create_insert_header(struct mlx5dr_context *ctx,\n-\t\t\t\t uint8_t num_of_hdrs,\n-\t\t\t\t struct mlx5dr_action_insert_header *hdrs,\n-\t\t\t\t uint32_t log_bulk_size,\n-\t\t\t\t uint32_t flags)\n+static struct mlx5dr_action *\n+mlx5dr_action_create_insert_header_reparse(struct mlx5dr_context *ctx,\n+\t\t\t\t\t uint8_t num_of_hdrs,\n+\t\t\t\t\t struct mlx5dr_action_insert_header *hdrs,\n+\t\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t\t uint32_t flags, uint32_t reparse)\n {\n \tstruct mlx5dr_action_reformat_header *reformat_hdrs;\n \tstruct mlx5dr_action *action;\n@@ -2065,7 +2093,8 @@ mlx5dr_action_create_insert_header(struct mlx5dr_context *ctx,\n \t}\n \n \tret = mlx5dr_action_handle_insert_with_ptr(action, num_of_hdrs,\n-\t\t\t\t\t\t reformat_hdrs, log_bulk_size);\n+\t\t\t\t\t\t reformat_hdrs, log_bulk_size,\n+\t\t\t\t\t\t reparse);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to create HWS reformat action\");\n \t\tgoto free_reformat_hdrs;\n@@ -2082,6 +2111,18 @@ mlx5dr_action_create_insert_header(struct mlx5dr_context *ctx,\n \treturn NULL;\n }\n \n+struct mlx5dr_action *\n+mlx5dr_action_create_insert_header(struct mlx5dr_context *ctx,\n+\t\t\t\t uint8_t num_of_hdrs,\n+\t\t\t\t struct mlx5dr_action_insert_header *hdrs,\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t flags)\n+{\n+\treturn mlx5dr_action_create_insert_header_reparse(ctx, num_of_hdrs, hdrs,\n+\t\t\t\t\t\t\t log_bulk_size, flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_DEFAULT);\n+}\n+\n struct mlx5dr_action *\n mlx5dr_action_create_remove_header(struct mlx5dr_context *ctx,\n \t\t\t\t struct mlx5dr_action_remove_header_attr *attr,\n@@ -2175,8 +2216,9 @@ mlx5dr_action_create_pop_ipv6_route_ext_mhdr1(struct mlx5dr_action *action)\n \tpattern.data = cmd;\n \tpattern.sz = sizeof(cmd);\n \n-\treturn mlx5dr_action_create_modify_header(action->ctx, 1, &pattern,\n-\t\t\t\t\t\t 0, action->flags);\n+\treturn mlx5dr_action_create_modify_header_reparse(action->ctx, 1, &pattern, 0,\n+\t\t\t\t\t\t\t action->flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_ON);\n }\n \n static void *\n@@ -2222,8 +2264,9 @@ mlx5dr_action_create_pop_ipv6_route_ext_mhdr2(struct mlx5dr_action *action)\n \tpattern.data = cmd;\n \tpattern.sz = sizeof(cmd);\n \n-\treturn mlx5dr_action_create_modify_header(action->ctx, 1, &pattern,\n-\t\t\t\t\t\t 0, action->flags);\n+\treturn mlx5dr_action_create_modify_header_reparse(action->ctx, 1, &pattern, 0,\n+\t\t\t\t\t\t\t action->flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_ON);\n }\n \n static void *\n@@ -2249,8 +2292,9 @@ mlx5dr_action_create_pop_ipv6_route_ext_mhdr3(struct mlx5dr_action *action)\n \tpattern.data = (__be64 *)cmd;\n \tpattern.sz = sizeof(cmd);\n \n-\treturn mlx5dr_action_create_modify_header(action->ctx, 1, &pattern,\n-\t\t\t\t\t\t 0, action->flags);\n+\treturn mlx5dr_action_create_modify_header_reparse(action->ctx, 1, &pattern, 0,\n+\t\t\t\t\t\t\t action->flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_OFF);\n }\n \n static int\n@@ -2397,8 +2441,9 @@ mlx5dr_action_create_push_ipv6_route_ext(struct mlx5dr_action *action,\n \tinsert_hdr.hdr.sz = hdr->sz;\n \tinsert_hdr.hdr.data = header;\n \taction->ipv6_route_ext.action[0] =\n-\t\tmlx5dr_action_create_insert_header(action->ctx, 1, &insert_hdr,\n-\t\t\t\t\t\t bulk_size, action->flags);\n+\t\tmlx5dr_action_create_insert_header_reparse(action->ctx, 1, &insert_hdr,\n+\t\t\t\t\t\t\t bulk_size, action->flags,\n+\t\t\t\t\t\t\t MLX5DR_ACTION_STC_REPARSE_OFF);\n \taction->ipv6_route_ext.action[1] =\n \t\tmlx5dr_action_create_push_ipv6_route_ext_mhdr1(action);\n \taction->ipv6_route_ext.action[2] =\n@@ -2431,12 +2476,6 @@ mlx5dr_action_create_reformat_ipv6_ext(struct mlx5dr_context *ctx,\n \tstruct mlx5dr_action *action;\n \tint ret;\n \n-\tif (mlx5dr_context_cap_dynamic_reparse(ctx)) {\n-\t\tDR_LOG(ERR, \"IPv6 extension actions is not supported\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn NULL;\n-\t}\n-\n \tif (!mlx5dr_action_is_hws_flags(flags) ||\n \t ((flags & MLX5DR_ACTION_FLAG_SHARED) && log_bulk_size)) {\n \t\tDR_LOG(ERR, \"IPv6 extension flags don't fit HWS (flags: 0x%x)\", flags);\n@@ -2461,6 +2500,12 @@ mlx5dr_action_create_reformat_ipv6_ext(struct mlx5dr_context *ctx,\n \t\tret = mlx5dr_action_create_pop_ipv6_route_ext(action);\n \t\tbreak;\n \tcase MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:\n+\t\tif (!mlx5dr_context_cap_dynamic_reparse(ctx)) {\n+\t\t\tDR_LOG(ERR, \"IPv6 routing extension push actions is not supported\");\n+\t\t\trte_errno = ENOTSUP;\n+\t\t\tgoto free_action;\n+\t\t}\n+\n \t\tret = mlx5dr_action_create_push_ipv6_route_ext(action, hdr, log_bulk_size);\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h\nindex c12d4308c7..fad35a845b 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.h\n@@ -62,6 +62,12 @@ enum mlx5dr_action_setter_flag {\n \tASF_HIT = 1 << 7,\n };\n \n+enum mlx5dr_action_stc_reparse {\n+\tMLX5DR_ACTION_STC_REPARSE_DEFAULT,\n+\tMLX5DR_ACTION_STC_REPARSE_ON,\n+\tMLX5DR_ACTION_STC_REPARSE_OFF,\n+};\n+\n struct mlx5dr_action_default_stc {\n \tstruct mlx5dr_pool_chunk nop_ctr;\n \tstruct mlx5dr_pool_chunk nop_dw5;\n@@ -141,6 +147,7 @@ struct mlx5dr_action {\n \t\t\t\t\tuint8_t anchor;\n \t\t\t\t\tuint8_t offset;\n \t\t\t\t\tbool encap;\n+\t\t\t\t\tuint8_t require_reparse;\n \t\t\t\t} reformat;\n \t\t\t\tstruct {\n \t\t\t\t\tstruct mlx5dr_action\n", "prefixes": [ "v4", "13/13" ] }