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GET /api/patches/133587/?format=api
{ "id": 133587, "url": "http://patches.dpdk.org/api/patches/133587/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231029163202.216450-14-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-14-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-14-getelson@nvidia.com", "date": "2023-10-29T16:31:46", "name": "[14/30] net/mlx5: reuse reformat and modify header actions in a table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a0e1b864cfb1b76cd9ebb23440b2c57ae3657a00", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231029163202.216450-14-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patches.dpdk.org/api/series/30049/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patches.dpdk.org/series/30049/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133587/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133587/checks/", "tags": {}, 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Ovsiienko\n <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 14/30] net/mlx5: reuse reformat and modify header actions in a\n table", "Date": "Sun, 29 Oct 2023 18:31:46 +0200", "Message-ID": "<20231029163202.216450-14-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A100:EE_|SJ0PR12MB6782:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f190950a-1a86-4e16-b19a-08dbd89cbe7f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", 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SFS:(13230031)(4636009)(346002)(396003)(136003)(39860400002)(376002)(230922051799003)(82310400011)(451199024)(64100799003)(186009)(1800799009)(40470700004)(36840700001)(46966006)(40460700003)(36756003)(26005)(16526019)(6286002)(1076003)(83380400001)(7636003)(426003)(336012)(5660300002)(356005)(6666004)(7696005)(2616005)(107886003)(82740400003)(8936002)(8676002)(47076005)(54906003)(316002)(41300700001)(6916009)(36860700001)(55016003)(40480700001)(30864003)(70586007)(86362001)(478600001)(70206006)(2906002)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Oct 2023 16:33:12.3719 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f190950a-1a86-4e16-b19a-08dbd89cbe7f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A100.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB6782", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "If application defined several actions templates with non-shared\nreformat or modify headers actions AND used these templates to create\na table, HWS could share reformat or modify headers resources,\ninstead of creating a resource for each action template.\n\nThe patch activates HWS code in a way that provides reformat or\nmodify header resources sharing.\n\nThe patch updates modify field and raw encap template actions\nvalidations:\n- modify field does not allow empty action template masks.\n- raw encap added action template mask validation.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 8 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 3 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 583 ++++++++++++++++++++++++--------\n 3 files changed, 451 insertions(+), 143 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 64e2fc6f04..ddb3b7b6fd 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1368,7 +1368,9 @@ struct mlx5_hw_jump_action {\n struct mlx5_hw_encap_decap_action {\n \tstruct mlx5dr_action *action; /* Action object. */\n \t/* Is header_reformat action shared across flows in table. */\n-\tbool shared;\n+\tuint32_t shared:1;\n+\tuint32_t multi_pattern:1;\n+\tvolatile uint32_t *multi_pattern_refcnt;\n \tsize_t data_size; /* Action metadata size. */\n \tuint8_t data[]; /* Action data. */\n };\n@@ -1382,7 +1384,9 @@ struct mlx5_hw_modify_header_action {\n \t/* Modify header action position in action rule table. */\n \tuint16_t pos;\n \t/* Is MODIFY_HEADER action shared across flows in table. */\n-\tbool shared;\n+\tuint32_t shared:1;\n+\tuint32_t multi_pattern:1;\n+\tvolatile uint32_t *multi_pattern_refcnt;\n \t/* Amount of modification commands stored in the precompiled buffer. */\n \tuint32_t mhdr_cmds_num;\n \t/* Precompiled modification commands. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex bdc8d0076a..84b94a9815 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -4579,7 +4579,8 @@ flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,\n \t\t\t\t\t\t (void *)items->type,\n \t\t\t\t\t\t \"items total size is too big\"\n \t\t\t\t\t\t \" for encap action\");\n-\t\trte_memcpy((void *)&buf[temp_size], items->spec, len);\n+\t\tif (items->spec)\n+\t\t\trte_memcpy(&buf[temp_size], items->spec, len);\n \t\tswitch (items->type) {\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\t\teth = (struct rte_ether_hdr *)&buf[temp_size];\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 6fc649d736..84c78ba19c 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -71,6 +71,95 @@ struct mlx5_indlst_legacy {\n \tenum rte_flow_action_type legacy_type;\n };\n \n+#define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \\\n+(((const struct encap_type *)(ptr))->definition)\n+\n+struct mlx5_multi_pattern_ctx {\n+\tunion {\n+\t\tstruct mlx5dr_action_reformat_header reformat_hdr;\n+\t\tstruct mlx5dr_action_mh_pattern mh_pattern;\n+\t};\n+\tunion {\n+\t\t/* action template auxiliary structures for object destruction */\n+\t\tstruct mlx5_hw_encap_decap_action *encap;\n+\t\tstruct mlx5_hw_modify_header_action *mhdr;\n+\t};\n+\t/* multi pattern action */\n+\tstruct mlx5dr_rule_action *rule_action;\n+};\n+\n+#define MLX5_MULTIPATTERN_ENCAP_NUM 4\n+\n+struct mlx5_tbl_multi_pattern_ctx {\n+\tstruct {\n+\t\tuint32_t elements_num;\n+\t\tstruct mlx5_multi_pattern_ctx ctx[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];\n+\t} reformat[MLX5_MULTIPATTERN_ENCAP_NUM];\n+\n+\tstruct {\n+\t\tuint32_t elements_num;\n+\t\tstruct mlx5_multi_pattern_ctx ctx[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];\n+\t} mh;\n+};\n+\n+#define MLX5_EMPTY_MULTI_PATTERN_CTX {{{0,}},}\n+\n+static int\n+mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_template_table *tbl,\n+\t\t\t struct mlx5_tbl_multi_pattern_ctx *mpat,\n+\t\t\t struct rte_flow_error *error);\n+\n+static __rte_always_inline int\n+mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)\n+{\n+\tswitch (type) {\n+\tcase MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:\n+\t\treturn 0;\n+\tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:\n+\t\treturn 1;\n+\tcase MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:\n+\t\treturn 2;\n+\tcase MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:\n+\t\treturn 3;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn -1;\n+}\n+\n+static __rte_always_inline enum mlx5dr_action_type\n+mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)\n+{\n+\tswitch (ix) {\n+\tcase 0:\n+\t\treturn MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;\n+\tcase 1:\n+\t\treturn MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;\n+\tcase 2:\n+\t\treturn MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;\n+\tcase 3:\n+\t\treturn MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn MLX5DR_ACTION_TYP_MAX;\n+}\n+\n+static inline enum mlx5dr_table_type\n+get_mlx5dr_table_type(const struct rte_flow_attr *attr)\n+{\n+\tenum mlx5dr_table_type type;\n+\n+\tif (attr->transfer)\n+\t\ttype = MLX5DR_TABLE_TYPE_FDB;\n+\telse if (attr->egress)\n+\t\ttype = MLX5DR_TABLE_TYPE_NIC_TX;\n+\telse\n+\t\ttype = MLX5DR_TABLE_TYPE_NIC_RX;\n+\treturn type;\n+}\n+\n struct mlx5_mirror_clone {\n \tenum rte_flow_action_type type;\n \tvoid *action_ctx;\n@@ -462,6 +551,34 @@ flow_hw_ct_compile(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static void\n+flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)\n+{\n+\tif (encap_decap->multi_pattern) {\n+\t\tuint32_t refcnt = __atomic_sub_fetch(encap_decap->multi_pattern_refcnt,\n+\t\t\t\t\t\t 1, __ATOMIC_RELAXED);\n+\t\tif (refcnt)\n+\t\t\treturn;\n+\t\tmlx5_free((void *)(uintptr_t)encap_decap->multi_pattern_refcnt);\n+\t}\n+\tif (encap_decap->action)\n+\t\tmlx5dr_action_destroy(encap_decap->action);\n+}\n+\n+static void\n+flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)\n+{\n+\tif (mhdr->multi_pattern) {\n+\t\tuint32_t refcnt = __atomic_sub_fetch(mhdr->multi_pattern_refcnt,\n+\t\t\t\t\t\t 1, __ATOMIC_RELAXED);\n+\t\tif (refcnt)\n+\t\t\treturn;\n+\t\tmlx5_free((void *)(uintptr_t)mhdr->multi_pattern_refcnt);\n+\t}\n+\tif (mhdr->action)\n+\t\tmlx5dr_action_destroy(mhdr->action);\n+}\n+\n /**\n * Destroy DR actions created by action template.\n *\n@@ -503,14 +620,12 @@ __flow_hw_action_template_destroy(struct rte_eth_dev *dev,\n \t\tacts->tir = NULL;\n \t}\n \tif (acts->encap_decap) {\n-\t\tif (acts->encap_decap->action)\n-\t\t\tmlx5dr_action_destroy(acts->encap_decap->action);\n+\t\tflow_hw_template_destroy_reformat_action(acts->encap_decap);\n \t\tmlx5_free(acts->encap_decap);\n \t\tacts->encap_decap = NULL;\n \t}\n \tif (acts->mhdr) {\n-\t\tif (acts->mhdr->action)\n-\t\t\tmlx5dr_action_destroy(acts->mhdr->action);\n+\t\tflow_hw_template_destroy_mhdr_action(acts->mhdr);\n \t\tmlx5_free(acts->mhdr);\n \t\tacts->mhdr = NULL;\n \t}\n@@ -881,8 +996,6 @@ flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,\n \tif (v->src.field == RTE_FLOW_FIELD_VALUE) {\n \t\tuint32_t j;\n \n-\t\tif (m == NULL)\n-\t\t\treturn false;\n \t\tfor (j = 0; j < RTE_DIM(m->src.value); ++j) {\n \t\t\t/*\n \t\t\t * Immediate value is considered to be masked\n@@ -1630,6 +1743,137 @@ table_template_translate_indirect_list(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+static int\n+mlx5_tbl_translate_reformat(struct mlx5_priv *priv,\n+\t\t\t const struct rte_flow_template_table_attr *table_attr,\n+\t\t\t struct mlx5_hw_actions *acts,\n+\t\t\t struct rte_flow_actions_template *at,\n+\t\t\t const struct rte_flow_item *enc_item,\n+\t\t\t const struct rte_flow_item *enc_item_m,\n+\t\t\t uint8_t *encap_data, uint8_t *encap_data_m,\n+\t\t\t struct mlx5_tbl_multi_pattern_ctx *mp_ctx,\n+\t\t\t size_t data_size, uint16_t reformat_src,\n+\t\t\t enum mlx5dr_action_type refmt_type,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tint mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);\n+\tconst struct rte_flow_attr *attr = &table_attr->flow_attr;\n+\tenum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr);\n+\tstruct mlx5dr_action_reformat_header hdr;\n+\tuint8_t buf[MLX5_ENCAP_MAX_LEN];\n+\tbool shared_rfmt = false;\n+\tint ret;\n+\n+\tMLX5_ASSERT(at->reformat_off != UINT16_MAX);\n+\tif (enc_item) {\n+\t\tMLX5_ASSERT(!encap_data);\n+\t\tret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tencap_data = buf;\n+\t\tif (enc_item_m)\n+\t\t\tshared_rfmt = true;\n+\t} else if (encap_data && encap_data_m) {\n+\t\tshared_rfmt = true;\n+\t}\n+\tacts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,\n+\t\t\t\t\tsizeof(*acts->encap_decap) + data_size,\n+\t\t\t\t\t0, SOCKET_ID_ANY);\n+\tif (!acts->encap_decap)\n+\t\treturn rte_flow_error_set(error, ENOMEM,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL, \"no memory for reformat context\");\n+\thdr.sz = data_size;\n+\thdr.data = encap_data;\n+\tif (shared_rfmt || mp_reformat_ix < 0) {\n+\t\tuint16_t reformat_ix = at->reformat_off;\n+\t\tuint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |\n+\t\t\t\t MLX5DR_ACTION_FLAG_SHARED;\n+\n+\t\tacts->encap_decap->action =\n+\t\t\tmlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,\n+\t\t\t\t\t\t 1, &hdr, 0, flags);\n+\t\tif (!acts->encap_decap->action)\n+\t\t\treturn -rte_errno;\n+\t\tacts->rule_acts[reformat_ix].action = acts->encap_decap->action;\n+\t\tacts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;\n+\t\tacts->rule_acts[reformat_ix].reformat.offset = 0;\n+\t\tacts->encap_decap->shared = true;\n+\t} else {\n+\t\tuint32_t ix;\n+\t\ttypeof(mp_ctx->reformat[0]) *reformat_ctx = mp_ctx->reformat +\n+\t\t\t\t\t\t\t mp_reformat_ix;\n+\n+\t\tix = reformat_ctx->elements_num++;\n+\t\treformat_ctx->ctx[ix].reformat_hdr = hdr;\n+\t\treformat_ctx->ctx[ix].rule_action = &acts->rule_acts[at->reformat_off];\n+\t\treformat_ctx->ctx[ix].encap = acts->encap_decap;\n+\t\tacts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;\n+\t\tacts->encap_decap_pos = at->reformat_off;\n+\t\tacts->encap_decap->data_size = data_size;\n+\t\tret = __flow_hw_act_data_encap_append\n+\t\t\t(priv, acts, (at->actions + reformat_src)->type,\n+\t\t\t reformat_src, at->reformat_off, data_size);\n+\t\tif (ret)\n+\t\t\treturn -rte_errno;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,\n+\t\t\t\t const struct mlx5_flow_template_table_cfg *cfg,\n+\t\t\t\t struct mlx5_hw_actions *acts,\n+\t\t\t\t struct mlx5_tbl_multi_pattern_ctx *mp_ctx,\n+\t\t\t\t struct mlx5_hw_modify_header_action *mhdr,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_template_table_attr *table_attr = &cfg->attr;\n+\tconst struct rte_flow_attr *attr = &table_attr->flow_attr;\n+\tenum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr);\n+\tuint16_t mhdr_ix = mhdr->pos;\n+\tstruct mlx5dr_action_mh_pattern pattern = {\n+\t\t.sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num\n+\t};\n+\n+\tif (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {\n+\t\t__flow_hw_action_template_destroy(dev, acts);\n+\t\treturn -rte_errno;\n+\t}\n+\tacts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),\n+\t\t\t\t 0, SOCKET_ID_ANY);\n+\tif (!acts->mhdr)\n+\t\treturn rte_flow_error_set(error, ENOMEM,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL, \"translate modify_header: no memory for modify header context\");\n+\trte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));\n+\tpattern.data = (__be64 *)acts->mhdr->mhdr_cmds;\n+\tif (mhdr->shared) {\n+\t\tuint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |\n+\t\t\t\t MLX5DR_ACTION_FLAG_SHARED;\n+\n+\t\tacts->mhdr->action = mlx5dr_action_create_modify_header\n+\t\t\t\t\t\t(priv->dr_ctx, 1, &pattern, 0,\n+\t\t\t\t\t\t flags);\n+\t\tif (!acts->mhdr->action)\n+\t\t\treturn rte_flow_error_set(error, rte_errno,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t NULL, \"translate modify_header: failed to create DR action\");\n+\t\tacts->rule_acts[mhdr_ix].action = acts->mhdr->action;\n+\t} else {\n+\t\ttypeof(mp_ctx->mh) *mh = &mp_ctx->mh;\n+\t\tuint32_t idx = mh->elements_num;\n+\t\tstruct mlx5_multi_pattern_ctx *mh_ctx = mh->ctx + mh->elements_num++;\n+\n+\t\tmh_ctx->mh_pattern = pattern;\n+\t\tmh_ctx->mhdr = acts->mhdr;\n+\t\tmh_ctx->rule_action = &acts->rule_acts[mhdr_ix];\n+\t\tacts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Translate rte_flow actions to DR action.\n *\n@@ -1658,6 +1902,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t const struct mlx5_flow_template_table_cfg *cfg,\n \t\t\t struct mlx5_hw_actions *acts,\n \t\t\t struct rte_flow_actions_template *at,\n+\t\t\t struct mlx5_tbl_multi_pattern_ctx *mp_ctx,\n \t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -1820,32 +2065,26 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n \t\t\tMLX5_ASSERT(!reformat_used);\n-\t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n-\t\t\t\t actions->conf)->definition;\n+\t\t\tenc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,\n+\t\t\t\t\t\t\t actions->conf);\n \t\t\tif (masks->conf)\n-\t\t\t\tenc_item_m = ((const struct rte_flow_action_vxlan_encap *)\n-\t\t\t\t\t masks->conf)->definition;\n+\t\t\t\tenc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,\n+\t\t\t\t\t\t\t\t masks->conf);\n \t\t\treformat_used = true;\n \t\t\treformat_src = src_pos;\n \t\t\trefmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n \t\t\tMLX5_ASSERT(!reformat_used);\n-\t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n-\t\t\t\t actions->conf)->definition;\n+\t\t\tenc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,\n+\t\t\t\t\t\t\t actions->conf);\n \t\t\tif (masks->conf)\n-\t\t\t\tenc_item_m = ((const struct rte_flow_action_nvgre_encap *)\n-\t\t\t\t\t masks->conf)->definition;\n+\t\t\t\tenc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,\n+\t\t\t\t\t\t\t\t masks->conf);\n \t\t\treformat_used = true;\n \t\t\treformat_src = src_pos;\n \t\t\trefmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;\n \t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:\n-\t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:\n-\t\t\tMLX5_ASSERT(!reformat_used);\n-\t\t\treformat_used = true;\n-\t\t\trefmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;\n-\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n \t\t\traw_encap_data =\n \t\t\t\t(const struct rte_flow_action_raw_encap *)\n@@ -1869,6 +2108,12 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t}\n \t\t\treformat_src = src_pos;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:\n+\t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:\n+\t\t\tMLX5_ASSERT(!reformat_used);\n+\t\t\treformat_used = true;\n+\t\t\trefmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_DECAP:\n \t\t\treformat_used = true;\n \t\t\trefmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;\n@@ -2005,83 +2250,20 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \tif (mhdr.pos != UINT16_MAX) {\n-\t\tstruct mlx5dr_action_mh_pattern pattern;\n-\t\tuint32_t flags;\n-\t\tuint32_t bulk_size;\n-\t\tsize_t mhdr_len;\n-\n-\t\tif (flow_hw_validate_compiled_modify_field(dev, cfg, &mhdr, error)) {\n-\t\t\t__flow_hw_action_template_destroy(dev, acts);\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t\tacts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),\n-\t\t\t\t\t 0, SOCKET_ID_ANY);\n-\t\tif (!acts->mhdr)\n-\t\t\tgoto err;\n-\t\trte_memcpy(acts->mhdr, &mhdr, sizeof(*acts->mhdr));\n-\t\tmhdr_len = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num;\n-\t\tflags = mlx5_hw_act_flag[!!attr->group][type];\n-\t\tif (acts->mhdr->shared) {\n-\t\t\tflags |= MLX5DR_ACTION_FLAG_SHARED;\n-\t\t\tbulk_size = 0;\n-\t\t} else {\n-\t\t\tbulk_size = rte_log2_u32(table_attr->nb_flows);\n-\t\t}\n-\t\tpattern.data = (__be64 *)acts->mhdr->mhdr_cmds;\n-\t\tpattern.sz = mhdr_len;\n-\t\tacts->mhdr->action = mlx5dr_action_create_modify_header\n-\t\t\t\t(priv->dr_ctx, 1, &pattern,\n-\t\t\t\t bulk_size, flags);\n-\t\tif (!acts->mhdr->action)\n+\t\tret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx,\n+\t\t\t\t\t\t &mhdr, error);\n+\t\tif (ret)\n \t\t\tgoto err;\n-\t\tacts->rule_acts[acts->mhdr->pos].action = acts->mhdr->action;\n \t}\n \tif (reformat_used) {\n-\t\tstruct mlx5dr_action_reformat_header hdr;\n-\t\tuint8_t buf[MLX5_ENCAP_MAX_LEN];\n-\t\tbool shared_rfmt = true;\n-\n-\t\tMLX5_ASSERT(at->reformat_off != UINT16_MAX);\n-\t\tif (enc_item) {\n-\t\t\tMLX5_ASSERT(!encap_data);\n-\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &data_size, error))\n-\t\t\t\tgoto err;\n-\t\t\tencap_data = buf;\n-\t\t\tif (!enc_item_m)\n-\t\t\t\tshared_rfmt = false;\n-\t\t} else if (encap_data && !encap_data_m) {\n-\t\t\tshared_rfmt = false;\n-\t\t}\n-\t\tacts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,\n-\t\t\t\t sizeof(*acts->encap_decap) + data_size,\n-\t\t\t\t 0, SOCKET_ID_ANY);\n-\t\tif (!acts->encap_decap)\n-\t\t\tgoto err;\n-\t\tif (data_size) {\n-\t\t\tacts->encap_decap->data_size = data_size;\n-\t\t\tmemcpy(acts->encap_decap->data, encap_data, data_size);\n-\t\t}\n-\n-\t\thdr.sz = data_size;\n-\t\thdr.data = encap_data;\n-\t\tacts->encap_decap->action = mlx5dr_action_create_reformat\n-\t\t\t\t(priv->dr_ctx, refmt_type,\n-\t\t\t\t 1, &hdr,\n-\t\t\t\t shared_rfmt ? 0 : rte_log2_u32(table_attr->nb_flows),\n-\t\t\t\t mlx5_hw_act_flag[!!attr->group][type] |\n-\t\t\t\t (shared_rfmt ? MLX5DR_ACTION_FLAG_SHARED : 0));\n-\t\tif (!acts->encap_decap->action)\n-\t\t\tgoto err;\n-\t\tacts->rule_acts[at->reformat_off].action = acts->encap_decap->action;\n-\t\tacts->rule_acts[at->reformat_off].reformat.data = acts->encap_decap->data;\n-\t\tif (shared_rfmt)\n-\t\t\tacts->rule_acts[at->reformat_off].reformat.offset = 0;\n-\t\telse if (__flow_hw_act_data_encap_append(priv, acts,\n-\t\t\t\t (at->actions + reformat_src)->type,\n-\t\t\t\t reformat_src, at->reformat_off, data_size))\n+\t\tret = mlx5_tbl_translate_reformat(priv, table_attr, acts, at,\n+\t\t\t\t\t\t enc_item, enc_item_m,\n+\t\t\t\t\t\t encap_data, encap_data_m,\n+\t\t\t\t\t\t mp_ctx, data_size,\n+\t\t\t\t\t\t reformat_src,\n+\t\t\t\t\t\t refmt_type, error);\n+\t\tif (ret)\n \t\t\tgoto err;\n-\t\tacts->encap_decap->shared = shared_rfmt;\n-\t\tacts->encap_decap_pos = at->reformat_off;\n \t}\n \treturn 0;\n err:\n@@ -2110,15 +2292,20 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_template_table *tbl,\n \t\t\t struct rte_flow_error *error)\n {\n+\tint ret;\n \tuint32_t i;\n+\tstruct mlx5_tbl_multi_pattern_ctx mpat = MLX5_EMPTY_MULTI_PATTERN_CTX;\n \n \tfor (i = 0; i < tbl->nb_action_templates; i++) {\n \t\tif (__flow_hw_actions_translate(dev, &tbl->cfg,\n \t\t\t\t\t\t&tbl->ats[i].acts,\n \t\t\t\t\t\ttbl->ats[i].action_template,\n-\t\t\t\t\t\terror))\n+\t\t\t\t\t\t&mpat, error))\n \t\t\tgoto err;\n \t}\n+\tret = mlx5_tbl_multi_pattern_process(dev, tbl, &mpat, error);\n+\tif (ret)\n+\t\tgoto err;\n \treturn 0;\n err:\n \twhile (i--)\n@@ -3627,6 +3814,143 @@ flow_hw_q_flow_flush(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static int\n+mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_template_table *tbl,\n+\t\t\t struct mlx5_tbl_multi_pattern_ctx *mpat,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tuint32_t i;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;\n+\tconst struct rte_flow_attr *attr = &table_attr->flow_attr;\n+\tenum mlx5dr_table_type type = get_mlx5dr_table_type(attr);\n+\tuint32_t flags = mlx5_hw_act_flag[!!attr->group][type];\n+\tstruct mlx5dr_action *dr_action;\n+\tuint32_t bulk_size = rte_log2_u32(table_attr->nb_flows);\n+\n+\tfor (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {\n+\t\tuint32_t j;\n+\t\tuint32_t *reformat_refcnt;\n+\t\ttypeof(mpat->reformat[0]) *reformat = mpat->reformat + i;\n+\t\tstruct mlx5dr_action_reformat_header hdr[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];\n+\t\tenum mlx5dr_action_type reformat_type =\n+\t\t\tmlx5_multi_pattern_reformat_index_to_type(i);\n+\n+\t\tif (!reformat->elements_num)\n+\t\t\tcontinue;\n+\t\tfor (j = 0; j < reformat->elements_num; j++)\n+\t\t\thdr[j] = reformat->ctx[j].reformat_hdr;\n+\t\treformat_refcnt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(uint32_t), 0,\n+\t\t\t\t\t rte_socket_id());\n+\t\tif (!reformat_refcnt)\n+\t\t\treturn rte_flow_error_set(error, ENOMEM,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t NULL, \"failed to allocate multi-pattern encap counter\");\n+\t\t*reformat_refcnt = reformat->elements_num;\n+\t\tdr_action = mlx5dr_action_create_reformat\n+\t\t\t(priv->dr_ctx, reformat_type, reformat->elements_num, hdr,\n+\t\t\t bulk_size, flags);\n+\t\tif (!dr_action) {\n+\t\t\tmlx5_free(reformat_refcnt);\n+\t\t\treturn rte_flow_error_set(error, rte_errno,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t NULL,\n+\t\t\t\t\t\t \"failed to create multi-pattern encap action\");\n+\t\t}\n+\t\tfor (j = 0; j < reformat->elements_num; j++) {\n+\t\t\treformat->ctx[j].rule_action->action = dr_action;\n+\t\t\treformat->ctx[j].encap->action = dr_action;\n+\t\t\treformat->ctx[j].encap->multi_pattern = 1;\n+\t\t\treformat->ctx[j].encap->multi_pattern_refcnt = reformat_refcnt;\n+\t\t}\n+\t}\n+\tif (mpat->mh.elements_num) {\n+\t\ttypeof(mpat->mh) *mh = &mpat->mh;\n+\t\tstruct mlx5dr_action_mh_pattern pattern[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];\n+\t\tuint32_t *mh_refcnt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(uint32_t),\n+\t\t\t\t\t\t 0, rte_socket_id());\n+\n+\t\tif (!mh_refcnt)\n+\t\t\treturn rte_flow_error_set(error, ENOMEM,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t NULL, \"failed to allocate modify header counter\");\n+\t\t*mh_refcnt = mpat->mh.elements_num;\n+\t\tfor (i = 0; i < mpat->mh.elements_num; i++)\n+\t\t\tpattern[i] = mh->ctx[i].mh_pattern;\n+\t\tdr_action = mlx5dr_action_create_modify_header\n+\t\t\t(priv->dr_ctx, mpat->mh.elements_num, pattern,\n+\t\t\t bulk_size, flags);\n+\t\tif (!dr_action) {\n+\t\t\tmlx5_free(mh_refcnt);\n+\t\t\treturn rte_flow_error_set(error, rte_errno,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t NULL,\n+\t\t\t\t\t\t \"failed to create multi-pattern header modify action\");\n+\t\t}\n+\t\tfor (i = 0; i < mpat->mh.elements_num; i++) {\n+\t\t\tmh->ctx[i].rule_action->action = dr_action;\n+\t\t\tmh->ctx[i].mhdr->action = dr_action;\n+\t\t\tmh->ctx[i].mhdr->multi_pattern = 1;\n+\t\t\tmh->ctx[i].mhdr->multi_pattern_refcnt = mh_refcnt;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_hw_build_template_table(struct rte_eth_dev *dev,\n+\t\t\t uint8_t nb_action_templates,\n+\t\t\t struct rte_flow_actions_template *action_templates[],\n+\t\t\t struct mlx5dr_action_template *at[],\n+\t\t\t struct rte_flow_template_table *tbl,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tint ret;\n+\tuint8_t i;\n+\tstruct mlx5_tbl_multi_pattern_ctx mpat = MLX5_EMPTY_MULTI_PATTERN_CTX;\n+\n+\tfor (i = 0; i < nb_action_templates; i++) {\n+\t\tuint32_t refcnt = __atomic_add_fetch(&action_templates[i]->refcnt, 1,\n+\t\t\t\t\t\t __ATOMIC_RELAXED);\n+\n+\t\tif (refcnt <= 1) {\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t &action_templates[i], \"invalid AT refcount\");\n+\t\t\tgoto at_error;\n+\t\t}\n+\t\tat[i] = action_templates[i]->tmpl;\n+\t\ttbl->ats[i].action_template = action_templates[i];\n+\t\tLIST_INIT(&tbl->ats[i].acts.act_list);\n+\t\t/* do NOT translate table action if `dev` was not started */\n+\t\tif (!dev->data->dev_started)\n+\t\t\tcontinue;\n+\t\tret = __flow_hw_actions_translate(dev, &tbl->cfg,\n+\t\t\t\t\t\t &tbl->ats[i].acts,\n+\t\t\t\t\t\t action_templates[i],\n+\t\t\t\t\t\t &mpat, error);\n+\t\tif (ret) {\n+\t\t\ti++;\n+\t\t\tgoto at_error;\n+\t\t}\n+\t}\n+\ttbl->nb_action_templates = nb_action_templates;\n+\tret = mlx5_tbl_multi_pattern_process(dev, tbl, &mpat, error);\n+\tif (ret)\n+\t\tgoto at_error;\n+\treturn 0;\n+\n+at_error:\n+\twhile (i--) {\n+\t\t__flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);\n+\t\t__atomic_sub_fetch(&action_templates[i]->refcnt,\n+\t\t\t\t 1, __ATOMIC_RELAXED);\n+\t}\n+\treturn rte_errno;\n+}\n+\n /**\n * Create flow table.\n *\n@@ -3779,29 +4103,12 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t}\n \ttbl->nb_item_templates = nb_item_templates;\n \t/* Build the action template. */\n-\tfor (i = 0; i < nb_action_templates; i++) {\n-\t\tuint32_t ret;\n-\n-\t\tret = __atomic_fetch_add(&action_templates[i]->refcnt, 1,\n-\t\t\t\t\t __ATOMIC_RELAXED) + 1;\n-\t\tif (ret <= 1) {\n-\t\t\trte_errno = EINVAL;\n-\t\t\tgoto at_error;\n-\t\t}\n-\t\tat[i] = action_templates[i]->tmpl;\n-\t\ttbl->ats[i].action_template = action_templates[i];\n-\t\tLIST_INIT(&tbl->ats[i].acts.act_list);\n-\t\tif (!port_started)\n-\t\t\tcontinue;\n-\t\terr = __flow_hw_actions_translate(dev, &tbl->cfg,\n-\t\t\t\t\t\t &tbl->ats[i].acts,\n-\t\t\t\t\t\t action_templates[i], &sub_error);\n-\t\tif (err) {\n-\t\t\ti++;\n-\t\t\tgoto at_error;\n-\t\t}\n+\terr = mlx5_hw_build_template_table(dev, nb_action_templates,\n+\t\t\t\t\t action_templates, at, tbl, &sub_error);\n+\tif (err) {\n+\t\ti = nb_item_templates;\n+\t\tgoto it_error;\n \t}\n-\ttbl->nb_action_templates = nb_action_templates;\n \ttbl->matcher = mlx5dr_matcher_create\n \t\t(tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);\n \tif (!tbl->matcher)\n@@ -3815,7 +4122,7 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\tLIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);\n \treturn tbl;\n at_error:\n-\twhile (i--) {\n+\tfor (i = 0; i < nb_action_templates; i++) {\n \t\t__flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);\n \t\t__atomic_fetch_sub(&action_templates[i]->refcnt,\n \t\t\t\t 1, __ATOMIC_RELAXED);\n@@ -4058,6 +4365,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \tconst struct rte_flow_action_modify_field *mask_conf = mask->conf;\n \tint ret;\n \n+\tif (!mask_conf)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\t \"modify_field mask conf is missing\");\n \tif (action_conf->operation != mask_conf->operation)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n@@ -4434,16 +4745,25 @@ flow_hw_validate_action_indirect(struct rte_eth_dev *dev,\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-flow_hw_validate_action_raw_encap(struct rte_eth_dev *dev __rte_unused,\n-\t\t\t\t const struct rte_flow_action *action,\n+flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,\n+\t\t\t\t const struct rte_flow_action *mask,\n \t\t\t\t struct rte_flow_error *error)\n {\n-\tconst struct rte_flow_action_raw_encap *raw_encap_data = action->conf;\n+\tconst struct rte_flow_action_raw_encap *mask_conf = mask->conf;\n+\tconst struct rte_flow_action_raw_encap *action_conf = action->conf;\n \n-\tif (!raw_encap_data || !raw_encap_data->size || !raw_encap_data->data)\n+\tif (!mask_conf || !mask_conf->size)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, mask,\n+\t\t\t\t\t \"raw_encap: size must be masked\");\n+\tif (!action_conf || !action_conf->size)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, action,\n-\t\t\t\t\t \"invalid raw_encap_data\");\n+\t\t\t\t\t \"raw_encap: invalid action configuration\");\n+\tif (mask_conf->data && !action_conf->data)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\t \"raw_encap: masked data is missing\");\n \treturn 0;\n }\n \n@@ -4724,7 +5044,7 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,\n \t\t\taction_flags |= MLX5_FLOW_ACTION_DECAP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n-\t\t\tret = flow_hw_validate_action_raw_encap(dev, action, error);\n+\t\t\tret = flow_hw_validate_action_raw_encap(action, mask, error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_ENCAP;\n@@ -9599,20 +9919,6 @@ mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)\n \tmlx5_free(mirror);\n }\n \n-static inline enum mlx5dr_table_type\n-get_mlx5dr_table_type(const struct rte_flow_attr *attr)\n-{\n-\tenum mlx5dr_table_type type;\n-\n-\tif (attr->transfer)\n-\t\ttype = MLX5DR_TABLE_TYPE_FDB;\n-\telse if (attr->egress)\n-\t\ttype = MLX5DR_TABLE_TYPE_NIC_TX;\n-\telse\n-\t\ttype = MLX5DR_TABLE_TYPE_NIC_RX;\n-\treturn type;\n-}\n-\n static __rte_always_inline bool\n mlx5_mirror_terminal_action(const struct rte_flow_action *action)\n {\n@@ -9751,9 +10057,6 @@ mirror_format_port(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n-#define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \\\n-(((const struct encap_type *)(ptr))->definition)\n-\n static int\n hw_mirror_clone_reformat(const struct rte_flow_action *actions,\n \t\t\t struct mlx5dr_action_dest_attr *dest_attr,\n", "prefixes": [ "14/30" ] }