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GET /api/patches/133581/?format=api
{ "id": 133581, "url": "http://patches.dpdk.org/api/patches/133581/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231029163202.216450-8-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-8-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-8-getelson@nvidia.com", "date": "2023-10-29T16:31:40", "name": "[08/30] net/mlx5/hws: adding method to query rule hash", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "32d9467c0e63e9e3fa4036dcebb7de2c330d20a2", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231029163202.216450-8-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patches.dpdk.org/api/series/30049/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patches.dpdk.org/series/30049/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133581/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133581/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 864C243238;\n\tSun, 29 Oct 2023 17:33:31 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2C26D40DF5;\n\tSun, 29 Oct 2023 17:33:02 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2045.outbound.protection.outlook.com [40.107.93.45])\n by mails.dpdk.org (Postfix) with ESMTP id C7DBA40ECF\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>,\n \"Itamar Gozlan\" <igozlan@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n \"Viacheslav Ovsiienko\" <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 08/30] net/mlx5/hws: adding method to query rule hash", "Date": "Sun, 29 Oct 2023 18:31:40 +0200", "Message-ID": "<20231029163202.216450-8-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FC:EE_|SJ2PR12MB8925:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f3f46117-40fe-4fa4-2fde-08dbd89cb5f0", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2TZ/8dgh6RkdSo3f2aVBWVgxWCwHihYDSRvfeniNDtgpwWu94pqLQEw8Ntj5clum9s3Kpnu6aJyEXyh9lH8A2FvUTcw84t5pjIcgHKq2tC5Bj/R8vzlY3mPDPNAUcspqDh0UwYq5Bem+VK8ySM5kopvgC8oePFGfvlxIxupKux3gIGb6PDpry8ojNAwSHCH+F5Hdt7NbBoIW26Dr0qNWwjVBueHklHpHHuXtDnoOgxCXsrmeDqmSBiCE78yCFCRbUgQT7PhkxCwWI/DtmkYZ4UWMOfM7oX/+zReMI1nAlO4kACAHV6YYaD5s5iv5Vsh2R/EjIBk+pwDe5z3brJybPKMY1W9kfoMZ8y3XSA1uWD99iLbNdYzywrv2b2bJhoF7H6CgmvmFHRLRBCUnu21nDfFIg+ND7+XB/ELUQxj0LXemkT+9i5sBXxtvX+qKGN6krQbyVcO2QYVXv91y49anxhE0QD8fliwrnFVFy8UvdRSrOP/jn6DAf9dIEUAxagWJ0ON/CCLFT4MU3gXsm9GR+8kZXLGpwA5lnsAx7isFYSpSS4gy2VApmR5kVbkG9N3K7wQZhZGYSIAm6mZRri5l/02oWkqexW9fwP/pagG/pRMc3CBU4m3zZqkPaXDNSgJ8xg4yYlzT+ZfE4HmKEgz7ahLtrXG1g0+eFc2hfC2D2Dyu/jdcqz6TQiPZyex6ji0NnrvusF71VPpjLmCJRxLpP8p/w2JGjFbZANRmsUXiSH9A8vNAN3YjmX+E7Y9aOwRm", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8925", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Itamar Gozlan <igozlan@nvidia.com>\n\nAdd a method to the HW steering API that allows querying\nthe hash result for a given matcher and a set of items. This\ncan be used to predict the location of the rule in the hash table.\n\nSigned-off-by: Itamar Gozlan <igozlan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 8 +++-\n drivers/net/mlx5/hws/meson.build | 1 +\n drivers/net/mlx5/hws/mlx5dr.h | 26 +++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 ++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 3 +-\n drivers/net/mlx5/hws/mlx5dr_crc32.c | 61 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_crc32.h | 13 ++++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 1 +\n drivers/net/mlx5/hws/mlx5dr_rule.c | 37 ++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_rule.h | 1 +\n 10 files changed, 152 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_crc32.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_crc32.h", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex e13ca3cd22..19c6d0282b 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2279,6 +2279,9 @@ enum {\n \tMLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1,\n };\n \n+enum {\n+\tMLX5_FLOW_TABLE_HASH_TYPE_CRC32,\n+};\n /*\n * HCA Capabilities 2\n */\n@@ -2328,7 +2331,10 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 format_select_dw_gtpu_dw_2[0x8];\n \tu8 format_select_dw_gtpu_first_ext_dw_0[0x8];\n \tu8 generate_wqe_type[0x20];\n-\tu8 reserved_at_2c0[0x540];\n+\tu8 reserved_at_2c0[0x160];\n+\tu8 reserved_at_420[0x1c];\n+\tu8 flow_table_hash_type[0x4];\n+\tu8 reserved_at_440[0x3c0];\n };\n \n struct mlx5_ifc_esw_cap_bits {\ndiff --git a/drivers/net/mlx5/hws/meson.build b/drivers/net/mlx5/hws/meson.build\nindex 38776d5163..bbcc628557 100644\n--- a/drivers/net/mlx5/hws/meson.build\n+++ b/drivers/net/mlx5/hws/meson.build\n@@ -19,4 +19,5 @@ sources += files(\n 'mlx5dr_definer.c',\n 'mlx5dr_debug.c',\n 'mlx5dr_pat_arg.c',\n+ 'mlx5dr_crc32.c',\n )\ndiff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nindex 1995c55132..39d902e762 100644\n--- a/drivers/net/mlx5/hws/mlx5dr.h\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -118,6 +118,11 @@ enum mlx5dr_matcher_distribute_mode {\n \tMLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR = 0x1,\n };\n \n+enum mlx5dr_rule_hash_calc_mode {\n+\tMLX5DR_RULE_HASH_CALC_MODE_RAW,\n+\tMLX5DR_RULE_HASH_CALC_MODE_IDX,\n+};\n+\n struct mlx5dr_matcher_attr {\n \t/* Processing priority inside table */\n \tuint32_t priority;\n@@ -430,6 +435,27 @@ int mlx5dr_rule_action_update(struct mlx5dr_rule *rule_handle,\n \t\t\t struct mlx5dr_rule_action rule_actions[],\n \t\t\t struct mlx5dr_rule_attr *attr);\n \n+/* Calculate hash for a given set of items, which indicates rule location in\n+ * the hash table.\n+ *\n+ * @param[in] matcher\n+ *\tThe matcher of the created rule.\n+ * @param[in] items\n+ *\tMatching pattern item definition.\n+ * @param[in] mt_idx\n+ *\tMatch template index that the match was created with.\n+ * @param[in] mode\n+ *\tHash calculation mode\n+ * @param[in, out] ret_hash\n+ *\tReturned calculated hash result\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_rule_hash_calculate(struct mlx5dr_matcher *matcher,\n+\t\t\t const struct rte_flow_item items[],\n+\t\t\t uint8_t mt_idx,\n+\t\t\t enum mlx5dr_rule_hash_calc_mode mode,\n+\t\t\t uint32_t *ret_hash);\n+\n /* Create direct rule drop action.\n *\n * @param[in] ctx\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex 781de40c02..c52cdd0767 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -1154,6 +1154,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,\n \t\t\t\t (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&\n \t\t\t\t (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);\n \n+\tcaps->flow_table_hash_type = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.cmd_hca_cap_2.flow_table_hash_type);\n+\n \tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |\n \t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex 28e5ea4726..03db62e2e2 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -217,10 +217,11 @@ struct mlx5dr_cmd_query_caps {\n \tuint8_t rtc_log_depth_max;\n \tuint8_t format_select_gtpu_dw_0;\n \tuint8_t format_select_gtpu_dw_1;\n+\tuint8_t flow_table_hash_type;\n \tuint8_t format_select_gtpu_dw_2;\n \tuint8_t format_select_gtpu_ext_dw_0;\n-\tuint32_t linear_match_definer;\n \tuint8_t access_index_mode;\n+\tuint32_t linear_match_definer;\n \tbool full_dw_jumbo_support;\n \tbool rtc_hash_split_table;\n \tbool rtc_linear_lookup_table;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_crc32.c b/drivers/net/mlx5/hws/mlx5dr_crc32.c\nnew file mode 100644\nindex 0000000000..9c454eda0c\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_crc32.c\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+uint32_t dr_ste_crc_tab32[] = {\n+\t0x0, 0x77073096, 0xee0e612c, 0x990951ba, 0x76dc419, 0x706af48f,\n+\t0xe963a535, 0x9e6495a3, 0xedb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,\n+\t0x9b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,\n+\t0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,\n+\t0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,\n+\t0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,\n+\t0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,\n+\t0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,\n+\t0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,\n+\t0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,\n+\t0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x1db7106,\n+\t0x98d220bc, 0xefd5102a, 0x71b18589, 0x6b6b51f, 0x9fbfe4a5, 0xe8b8d433,\n+\t0x7807c9a2, 0xf00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x86d3d2d,\n+\t0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,\n+\t0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,\n+\t0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,\n+\t0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,\n+\t0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,\n+\t0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,\n+\t0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,\n+\t0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,\n+\t0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x3b6e20c, 0x74b1d29a,\n+\t0xead54739, 0x9dd277af, 0x4db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,\n+\t0xd6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0xa00ae27, 0x7d079eb1,\n+\t0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,\n+\t0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,\n+\t0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,\n+\t0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,\n+\t0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,\n+\t0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,\n+\t0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,\n+\t0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,\n+\t0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x26d930a, 0x9c0906a9, 0xeb0e363f,\n+\t0x72076785, 0x5005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0xcb61b38,\n+\t0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0xbdbdf21, 0x86d3d2d4, 0xf1d4e242,\n+\t0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,\n+\t0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,\n+\t0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,\n+\t0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,\n+\t0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,\n+\t0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,\n+\t0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,\n+\t0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d\n+};\n+\n+uint32_t mlx5dr_crc32_calc(uint8_t *p, size_t len)\n+{\n+\tuint32_t crc = 0;\n+\n+\twhile (len--)\n+\t\tcrc = (crc >> 8) ^ dr_ste_crc_tab32[(crc ^ *p++) & 255];\n+\n+\treturn rte_be_to_cpu_32(crc);\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_crc32.h b/drivers/net/mlx5/hws/mlx5dr_crc32.h\nnew file mode 100644\nindex 0000000000..9aab9e06ca\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_crc32.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_CRC32_C_\n+#define MLX5DR_CRC32_C_\n+\n+/* Ethernet AUTODIN II CRC32 (little-endian)\n+ * CRC32_POLY 0xedb88320\n+ */\n+uint32_t mlx5dr_crc32_calc(uint8_t *p, size_t len);\n+\n+#endif /* MLX5DR_CRC32_C_ */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h\nindex 3770d28e62..021d599a56 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_internal.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_internal.h\n@@ -38,6 +38,7 @@\n #include \"mlx5dr_matcher.h\"\n #include \"mlx5dr_debug.h\"\n #include \"mlx5dr_pat_arg.h\"\n+#include \"mlx5dr_crc32.h\"\n \n #define DW_SIZE\t\t4\n #define BITS_IN_BYTE\t8\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c\nindex 931c68b160..980a99b226 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c\n@@ -770,3 +770,40 @@ size_t mlx5dr_rule_get_handle_size(void)\n {\n \treturn sizeof(struct mlx5dr_rule);\n }\n+\n+int mlx5dr_rule_hash_calculate(struct mlx5dr_matcher *matcher,\n+\t\t\t const struct rte_flow_item items[],\n+\t\t\t uint8_t mt_idx,\n+\t\t\t enum mlx5dr_rule_hash_calc_mode mode,\n+\t\t\t uint32_t *ret_hash)\n+{\n+\tuint8_t tag[MLX5DR_STE_SZ] = {0};\n+\tstruct mlx5dr_match_template *mt;\n+\n+\tif (!matcher || !matcher->mt) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tmt = &matcher->mt[mt_idx];\n+\n+\tif (mlx5dr_matcher_req_fw_wqe(matcher) ||\n+\t mlx5dr_table_is_root(matcher->tbl) ||\n+\t matcher->tbl->ctx->caps->access_index_mode == MLX5DR_MATCHER_INSERT_BY_HASH ||\n+\t matcher->tbl->ctx->caps->flow_table_hash_type != MLX5_FLOW_TABLE_HASH_TYPE_CRC32) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tmlx5dr_definer_create_tag(items, mt->fc, mt->fc_sz, tag);\n+\tif (mlx5dr_matcher_mt_is_jumbo(mt))\n+\t\t*ret_hash = mlx5dr_crc32_calc(tag, MLX5DR_JUMBO_TAG_SZ);\n+\telse\n+\t\t*ret_hash = mlx5dr_crc32_calc(tag + MLX5DR_ACTIONS_SZ,\n+\t\t\t\t\t MLX5DR_MATCH_TAG_SZ);\n+\n+\tif (mode == MLX5DR_RULE_HASH_CALC_MODE_IDX)\n+\t\t*ret_hash = *ret_hash & (BIT(matcher->attr.rule.num_log) - 1);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.h b/drivers/net/mlx5/hws/mlx5dr_rule.h\nindex 886cf77992..f7d97eead5 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.h\n@@ -10,6 +10,7 @@ enum {\n \tMLX5DR_ACTIONS_SZ = 12,\n \tMLX5DR_MATCH_TAG_SZ = 32,\n \tMLX5DR_JUMBO_TAG_SZ = 44,\n+\tMLX5DR_STE_SZ = 64,\n };\n \n enum mlx5dr_rule_status {\n", "prefixes": [ "08/30" ] }