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GET /api/patches/133516/?format=api
{ "id": 133516, "url": "http://patches.dpdk.org/api/patches/133516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231027220343.499706-2-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231027220343.499706-2-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231027220343.499706-2-nicolas.chautru@intel.com", "date": "2023-10-27T22:03:42", "name": "[v3,1/2] baseband/acc: support ACC100 deRM corner case SDK", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4a2df550b1059c439f0c246c8f6f87cc5239cf3d", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231027220343.499706-2-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 30033, "url": "http://patches.dpdk.org/api/series/30033/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30033", "date": "2023-10-27T22:03:41", "name": "FlexRAN SDK update for 23.11", "version": 3, "mbox": "http://patches.dpdk.org/series/30033/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133516/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133516/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2BE2D4321A;\n\tSat, 28 Oct 2023 00:10:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 86EC3406FF;\n\tSat, 28 Oct 2023 00:10:30 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 3374D40267\n for <dev@dpdk.org>; Sat, 28 Oct 2023 00:10:26 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Oct 2023 15:10:24 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by fmsmga001.fm.intel.com with ESMTP; 27 Oct 2023 15:07:54 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1698444626; x=1729980626;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=6FkJUPW1qH1xnZwcRyLNhHC+jrl7NHWuCPb2xtpLhv8=;\n b=lWcwVRjepNQ1gxmR9lsmPUorZzr1faoAPLGOoy6Z3zhNZof+Hj62E80P\n 0HHHTH8NbgaLanTRW2KCSRORzrkRrWyxJoZM179drSizE4GU7C9/GrvBn\n oMgAhJKinwDZcEM/b2S8JE0CtfHj8cWxwDgZbDaZQeRU5ZpYOsWn+/UsJ\n NufQRF5DpE29qD9ZsIKLEL+ma2c6JrU8TQ9fALeKljVwtJuBb2z0j6Upu\n RBCqj93Dw7Tb1LVRNK7EkXX+9eky2RJmqfWbhrlWXIrtrh1hwGDV0Zp6g\n iUxw5JSxrf0KdLvpTfFXJ8kCTSTzqUntZSR4wiZzhJjovKbiYhC3PENTu A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10876\"; a=\"385065058\"", "E=Sophos;i=\"6.03,257,1694761200\"; d=\"scan'208\";a=\"385065058\"", "E=McAfee;i=\"6600,9927,10876\"; a=\"903399572\"", "E=Sophos;i=\"6.03,257,1694761200\"; d=\"scan'208\";a=\"903399572\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v3 1/2] baseband/acc: support ACC100 deRM corner case SDK", "Date": "Fri, 27 Oct 2023 22:03:42 +0000", "Message-Id": "<20231027220343.499706-2-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231027220343.499706-1-nicolas.chautru@intel.com>", "References": "<20231027220343.499706-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hernan Vargas <hernan.vargas@intel.com>\n\nImplement de-ratematch pre-processing for ACC100 SW corner cases.\nSome specific 5GUL FEC corner cases may cause unintended back pressure\nand in some cases a potential stability issue on the ACC100.\nThe PMD can detect such code block configuration and issue an info\nmessage to the user.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/meson.build | 21 ++++++++++\n drivers/baseband/acc/rte_acc100_pmd.c | 59 +++++++++++++++++++++++++--\n 2 files changed, 76 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build\nindex 27a654b501..449d1e176c 100644\n--- a/drivers/baseband/acc/meson.build\n+++ b/drivers/baseband/acc/meson.build\n@@ -1,6 +1,27 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2020 Intel Corporation\n \n+# check for FlexRAN SDK libraries\n+dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false)\n+\n+if dep_dec5g.found()\n+ ext_deps += cc.find_library('stdc++', required: true)\n+ ext_deps += cc.find_library('irc', required: true)\n+ ext_deps += cc.find_library('imf', required: true)\n+ ext_deps += cc.find_library('ipps', required: true)\n+ ext_deps += cc.find_library('svml', required: true)\n+ ext_deps += dep_dec5g\n+ ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_turbo', required: true)\n+ ext_deps += dependency('flexran_sdk_crc', required: true)\n+ ext_deps += dependency('flexran_sdk_rate_matching', required: true)\n+ ext_deps += dependency('flexran_sdk_common', required: true)\n+ cflags += ['-DRTE_BBDEV_SDK_AVX2']\n+ cflags += ['-DRTE_BBDEV_SDK_AVX512']\n+endif\n+\n deps += ['bus_pci']\n \n sources = files('rte_acc100_pmd.c', 'rte_vrb_pmd.c')\ndiff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex 8a9c296b01..292537e24d 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -22,6 +22,10 @@\n #include \"acc101_pmd.h\"\n #include \"vrb_cfg.h\"\n \n+#ifdef RTE_BBDEV_SDK_AVX512\n+#include <phy_rate_dematching_5gnr.h>\n+#endif\n+\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);\n #else\n@@ -3058,7 +3062,8 @@ derm_workaround_recommended(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_q\n /** Enqueue one decode operations for ACC100 device in CB mode */\n static inline int\n enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n-\t\tuint16_t total_enqueued_cbs, bool same_op)\n+\t\tuint16_t total_enqueued_cbs, bool same_op,\n+\t\tstruct rte_bbdev_queue_data *q_data)\n {\n \tint ret;\n \tif (unlikely(check_bit(op->ldpc_dec.op_flags,\n@@ -3113,8 +3118,54 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tstruct acc_fcw_ld *fcw;\n \t\tuint32_t seg_total_left;\n \n-\t\tif (derm_workaround_recommended(&op->ldpc_dec, q))\n-\t\t\trte_bbdev_log(INFO, \"Corner case may require deRM pre-processing\");\n+\t\tif (derm_workaround_recommended(&op->ldpc_dec, q)) {\n+\t\t\t#ifdef RTE_BBDEV_SDK_AVX512\n+\t\t\tstruct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;\n+\t\t\tstruct bblib_rate_dematching_5gnr_request derm_req;\n+\t\t\tstruct bblib_rate_dematching_5gnr_response derm_resp;\n+\t\t\tuint8_t *in;\n+\n+\t\t\t/* Checking input size is matching with E */\n+\t\t\tif (dec->input.data->data_len < (dec->cb_params.e % 65536)) {\n+\t\t\t\trte_bbdev_log(ERR, \"deRM: Input size mismatch\");\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\t\t\t/* Run first deRM processing in SW */\n+\t\t\tin = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset);\n+\t\t\tderm_req.p_in = (int8_t *) in;\n+\t\t\tderm_req.p_harq = (int8_t *) q->derm_buffer;\n+\t\t\tderm_req.base_graph = dec->basegraph;\n+\t\t\tderm_req.zc = dec->z_c;\n+\t\t\tderm_req.ncb = dec->n_cb;\n+\t\t\tderm_req.e = dec->cb_params.e;\n+\t\t\tif (derm_req.e > ACC_MAX_E) {\n+\t\t\t\trte_bbdev_log(WARNING,\n+\t\t\t\t\t\t\"deRM: E %d > %d max\",\n+\t\t\t\t\t\tderm_req.e, ACC_MAX_E);\n+\t\t\t\tderm_req.e = ACC_MAX_E;\n+\t\t\t}\n+\t\t\tderm_req.k0 = 0; /* Actual output from SDK */\n+\t\t\tderm_req.isretx = false;\n+\t\t\tderm_req.rvid = dec->rv_index;\n+\t\t\tderm_req.modulation_order = dec->q_m;\n+\t\t\tderm_req.start_null_index =\n+\t\t\t\t\t(dec->basegraph == 1 ? 22 : 10)\n+\t\t\t\t\t* dec->z_c - 2 * dec->z_c\n+\t\t\t\t\t- dec->n_filler;\n+\t\t\tderm_req.num_of_null = dec->n_filler;\n+\t\t\tbblib_rate_dematching_5gnr(&derm_req, &derm_resp);\n+\t\t\t/* Force back the HW DeRM */\n+\t\t\tdec->q_m = 1;\n+\t\t\tdec->cb_params.e = dec->n_cb - dec->n_filler;\n+\t\t\tdec->rv_index = 0;\n+\t\t\trte_memcpy(in, q->derm_buffer, dec->cb_params.e);\n+\t\t\t/* Capture counter when pre-processing is used */\n+\t\t\tq_data->queue_stats.enqueue_warn_count++;\n+\t\t\t#else\n+\t\t\tRTE_SET_USED(q_data);\n+\t\t\trte_bbdev_log(INFO, \"Corner case may require deRM pre-processing in SDK\");\n+\t\t\t#endif\n+\t\t}\n \n \t\tfcw = &desc->req.fcw_ld;\n \t\tq->d->fcw_ld_fill(op, fcw, harq_layout);\n@@ -3647,7 +3698,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,\n \t\t\tops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m,\n \t\t\tops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e,\n \t\t\tsame_op);\n-\t\tret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op);\n+\t\tret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data);\n \t\tif (ret < 0) {\n \t\t\tacc_enqueue_invalid(q_data);\n \t\t\tbreak;\n", "prefixes": [ "v3", "1/2" ] }