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GET /api/patches/133381/?format=api
{ "id": 133381, "url": "http://patches.dpdk.org/api/patches/133381/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/9571524d259f454ef7ed73ce1c8c28905ed93190.1698307299.git.gmuthukrishn@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<9571524d259f454ef7ed73ce1c8c28905ed93190.1698307299.git.gmuthukrishn@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/9571524d259f454ef7ed73ce1c8c28905ed93190.1698307299.git.gmuthukrishn@marvell.com", "date": "2023-10-26T08:15:12", "name": "[v1,4/4] crypto/cnxk: add ECDH support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7e0681ca98ff455a04103598cbdec2988106f80d", "submitter": { "id": 2301, "url": "http://patches.dpdk.org/api/people/2301/?format=api", "name": "Gowrishankar Muthukrishnan", "email": "gmuthukrishn@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/9571524d259f454ef7ed73ce1c8c28905ed93190.1698307299.git.gmuthukrishn@marvell.com/mbox/", "series": [ { "id": 29995, "url": "http://patches.dpdk.org/api/series/29995/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29995", "date": "2023-10-26T08:15:08", "name": "test/cryptodev: add ECDH tests", "version": 1, "mbox": "http://patches.dpdk.org/series/29995/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133381/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133381/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 039AA43206;\n\tThu, 26 Oct 2023 10:15:58 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E89CF42DEA;\n\tThu, 26 Oct 2023 10:15:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E897140E5E\n for <dev@dpdk.org>; Thu, 26 Oct 2023 10:15:31 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39Q70U2f020548; Thu, 26 Oct 2023 01:15:31 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3txcsr1b2w-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 26 Oct 2023 01:15:31 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 26 Oct 2023 01:15:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 26 Oct 2023 01:15:29 -0700", "from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34])\n by maili.marvell.com (Postfix) with ESMTP id 3E7693F704D;\n Thu, 26 Oct 2023 01:15:26 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=+zPf4ZqF/mZideugJtnQVj4WbdbJK3vFMH7ZcLLi7FQ=;\n b=Ih51esZpsC79arQdpyY6IkfkHZ+arP7TDRyZ4PVY37plQlrfzBWWcyDobHfEJx734xKU\n WV+qKLJgWh7MajNMk5FwQNY0cZBOqHBUT5BZjuSXbq4vMipN7MOXYmRljR0Wo/fQL07E\n DGlbctioPDvYgw2yQkH0zd3D4MkdXdduhJWbmdXbb2qxz4TgY5l1SGtOwuTUR1DrvOBE\n M251WZfKtHWpBerkAT37Bs+SYYrXycMHH9bH0xk/np71tGxGyWo9na1p76S8H+vL1GIL\n Xzw78tyEkanV5Wprp10u12P5VK1Bw/rC52b51rhmueK2f7VCv/6vzOiJx0esZRG5EeZu gw==", "From": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<anoobj@marvell.com>, Akhil Goyal <gakhil@marvell.com>, Fan Zhang\n <fanzhang.oss@gmail.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>", "Subject": "[PATCH v1 4/4] crypto/cnxk: add ECDH support", "Date": "Thu, 26 Oct 2023 13:45:12 +0530", "Message-ID": "\n <9571524d259f454ef7ed73ce1c8c28905ed93190.1698307299.git.gmuthukrishn@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<cover.1698307299.git.gmuthukrishn@marvell.com>", "References": "<cover.1698307299.git.gmuthukrishn@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "ITxEJqKfIURVRIMI3VIYg-wyGiub8Ian", "X-Proofpoint-GUID": "ITxEJqKfIURVRIMI3VIYg-wyGiub8Ian", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-26_05,2023-10-25_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add ECDH support in CNXK PMD.\n\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 1 +\n doc/guides/cryptodevs/features/cn9k.ini | 1 +\n drivers/common/cnxk/roc_ae.h | 7 +\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 12 ++\n drivers/crypto/cnxk/cnxk_ae.h | 143 ++++++++++++++++--\n drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +-\n .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 14 ++\n 7 files changed, 165 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex 4f542c6038..ea8a22eb46 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -102,6 +102,7 @@ DSA =\n Modular Exponentiation = Y\n Modular Inversion =\n Diffie-hellman =\n+ECDH = Y\n ECDSA = Y\n ECPM = Y\n SM2 = Y\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex bf0e1a98b2..d70771d9bd 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -96,6 +96,7 @@ DSA =\n Modular Exponentiation = Y\n Modular Inversion =\n Diffie-hellman =\n+ECDH = Y\n ECDSA = Y\n ECPM = Y\n \ndiff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h\nindex eaf12ab254..a9a08d9fb9 100644\n--- a/drivers/common/cnxk/roc_ae.h\n+++ b/drivers/common/cnxk/roc_ae.h\n@@ -8,9 +8,11 @@\n #include \"roc_platform.h\"\n \n /* AE opcodes */\n+#define ROC_AE_MAJOR_OP_RANDOM\t 0x32\n #define ROC_AE_MAJOR_OP_MODEX\t 0x03\n #define ROC_AE_MAJOR_OP_EC\t 0x04\n #define ROC_AE_MAJOR_OP_ECC\t 0x05\n+#define ROC_AE_MINOR_OP_RANDOM\t 0x00\n #define ROC_AE_MINOR_OP_MODEX\t 0x01\n #define ROC_AE_MINOR_OP_PKCS_ENC 0x02\n #define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03\n@@ -46,6 +48,11 @@ typedef enum {\n #define ROC_AE_EC_PARAM1_NIST (0 << 6)\n #define ROC_AE_EC_PARAM1_NONNIST (1 << 6)\n \n+typedef enum {\n+\tROC_AE_ERR_ECC_PAI = 0x0b,\n+\tROC_AE_ERR_ECC_POINT_NOT_ON_CURVE = 0x11\n+} roc_ae_error_code;\n+\n /* Prime and order fields of built-in elliptic curves */\n struct roc_ae_ec_group {\n \tstruct {\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 5f181e8839..997110e3d3 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -860,6 +860,18 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n \t\t}\n \n \t\treturn;\n+\t} else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC &&\n+\t\t\t cop->sess_type == RTE_CRYPTO_OP_WITH_SESSION &&\n+\t\t\t cop->asym->ecdh.ke_type == RTE_CRYPTO_ASYM_KE_PUB_KEY_VERIFY) {\n+\t\tif (likely(compcode == CPT_COMP_GOOD)) {\n+\t\t\tif (uc_compcode == ROC_AE_ERR_ECC_POINT_NOT_ON_CURVE) {\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\t\treturn;\n+\t\t\t} else if (uc_compcode == ROC_AE_ERR_ECC_PAI) {\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n \t}\n \n \tif (likely(compcode == CPT_COMP_GOOD)) {\ndiff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h\nindex f05ae4f4a1..ea11e093bf 100644\n--- a/drivers/crypto/cnxk/cnxk_ae.h\n+++ b/drivers/crypto/cnxk/cnxk_ae.h\n@@ -236,6 +236,7 @@ cnxk_ae_fill_session_parameters(struct cnxk_ae_sess *sess,\n \t\tbreak;\n \tcase RTE_CRYPTO_ASYM_XFORM_ECDSA:\n \t\t/* Fall through */\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECDH:\n \tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n \tcase RTE_CRYPTO_ASYM_XFORM_ECFPM:\n \tcase RTE_CRYPTO_ASYM_XFORM_SM2:\n@@ -920,7 +921,7 @@ cnxk_ae_enqueue_sm2_op(struct rte_crypto_op *op,\n }\n \n static __rte_always_inline int\n-cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n+cnxk_ae_ecfpm_prep(rte_crypto_param *scalar,\n \t\t struct roc_ae_buf_ptr *meta_buf, uint64_t *fpm_iova,\n \t\t struct roc_ae_ec_group *ec_grp, uint8_t curveid,\n \t\t struct cpt_inst_s *inst)\n@@ -939,7 +940,7 @@ cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tinst->dptr = (uintptr_t)dptr;\n \n \tp_align = RTE_ALIGN_CEIL(prime_len, 8);\n-\tscalar_align = RTE_ALIGN_CEIL(ecpm->scalar.length, 8);\n+\tscalar_align = RTE_ALIGN_CEIL(scalar->length, 8);\n \n \t/*\n \t * Set dlen = sum(ROUNDUP8(input point(x and y coordinates), prime,\n@@ -954,7 +955,7 @@ cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tdptr += sizeof(fpm_table_iova);\n \n \t/* Copy scalar, prime */\n-\tmemcpy(dptr, ecpm->scalar.data, ecpm->scalar.length);\n+\tmemcpy(dptr, scalar->data, scalar->length);\n \tdptr += scalar_align;\n \tmemcpy(dptr, ec_grp->prime.data, ec_grp->prime.length);\n \tdptr += p_align;\n@@ -968,7 +969,7 @@ cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tw4.s.opcode_minor = ROC_AE_MINOR_OP_ECC_FPM;\n \n \tw4.s.param1 = curveid | (1 << 8);\n-\tw4.s.param2 = ecpm->scalar.length;\n+\tw4.s.param2 = scalar->length;\n \tw4.s.dlen = dlen;\n \n \tinst->w4.u64 = w4.u64;\n@@ -978,13 +979,13 @@ cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n }\n \n static __rte_always_inline int\n-cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n+cnxk_ae_ecpm_prep(rte_crypto_param *scalar, struct rte_crypto_ec_point *p,\n \t\t struct roc_ae_buf_ptr *meta_buf,\n \t\t struct roc_ae_ec_group *ec_grp, uint8_t curveid,\n \t\t struct cpt_inst_s *inst)\n {\n-\tuint16_t x1_len = ecpm->p.x.length;\n-\tuint16_t y1_len = ecpm->p.y.length;\n+\tuint16_t x1_len = p->x.length;\n+\tuint16_t y1_len = p->y.length;\n \tuint16_t scalar_align, p_align;\n \tuint16_t x1_offset, y1_offset;\n \tuint16_t dlen, prime_len;\n@@ -998,7 +999,7 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tinst->dptr = (uintptr_t)dptr;\n \n \tp_align = RTE_ALIGN_CEIL(prime_len, 8);\n-\tscalar_align = RTE_ALIGN_CEIL(ecpm->scalar.length, 8);\n+\tscalar_align = RTE_ALIGN_CEIL(scalar->length, 8);\n \n \t/*\n \t * Set dlen = sum(ROUNDUP8(input point(x and y coordinates), prime,\n@@ -1013,11 +1014,11 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tmemset(dptr, 0, dlen);\n \n \t/* Copy input point, scalar, prime */\n-\tmemcpy(dptr + x1_offset, ecpm->p.x.data, x1_len);\n+\tmemcpy(dptr + x1_offset, p->x.data, x1_len);\n \tdptr += p_align;\n-\tmemcpy(dptr + y1_offset, ecpm->p.y.data, y1_len);\n+\tmemcpy(dptr + y1_offset, p->y.data, y1_len);\n \tdptr += p_align;\n-\tmemcpy(dptr, ecpm->scalar.data, ecpm->scalar.length);\n+\tmemcpy(dptr, scalar->data, scalar->length);\n \tdptr += scalar_align;\n \tmemcpy(dptr, ec_grp->prime.data, ec_grp->prime.length);\n \tdptr += p_align;\n@@ -1031,7 +1032,7 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \tw4.s.opcode_minor = ROC_AE_MINOR_OP_ECC_UMP;\n \n \tw4.s.param1 = curveid;\n-\tw4.s.param2 = ecpm->scalar.length;\n+\tw4.s.param2 = scalar->length;\n \tw4.s.dlen = dlen;\n \n \tinst->w4.u64 = w4.u64;\n@@ -1040,6 +1041,78 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,\n \treturn 0;\n }\n \n+static __rte_always_inline int\n+cnxk_ae_random_prep(uint16_t len, struct roc_ae_buf_ptr *meta_buf,\n+\t\t struct cpt_inst_s *inst)\n+{\n+\tunion cpt_inst_w4 w4;\n+\tuint8_t *dptr;\n+\n+\t/* Input buffer */\n+\tdptr = meta_buf->vaddr;\n+\tinst->dptr = (uintptr_t)dptr;\n+\n+\t/* Setup opcodes */\n+\tw4.s.opcode_major = ROC_AE_MAJOR_OP_RANDOM;\n+\tw4.s.opcode_minor = ROC_AE_MINOR_OP_RANDOM;\n+\n+\tw4.s.param1 = len;\n+\tw4.s.param2 = 0;\n+\tw4.s.dlen = 0;\n+\n+\tinst->w4.u64 = w4.u64;\n+\tinst->rptr = (uintptr_t)dptr;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int __rte_hot\n+cnxk_ae_enqueue_ecdh_op(struct rte_crypto_op *op,\n+\t\t\t struct roc_ae_buf_ptr *meta_buf,\n+\t\t\t struct cnxk_ae_sess *sess, uint64_t *fpm_iova,\n+\t\t\t struct roc_ae_ec_group **ec_grp,\n+\t\t\t struct cpt_inst_s *inst)\n+{\n+\tstruct rte_crypto_ecdh_op_param *ecdh = &op->asym->ecdh;\n+\tuint8_t curveid = sess->ec_ctx.curveid;\n+\tstruct rte_crypto_ec_point point;\n+\trte_crypto_uint scalar;\n+\tint ret = 0;\n+\n+\tswitch (ecdh->ke_type) {\n+\tcase RTE_CRYPTO_ASYM_KE_PRIV_KEY_GENERATE:\n+\t\tcnxk_ae_random_prep(ecdh->priv_key.length, meta_buf, inst);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_PUB_KEY_GENERATE:\n+\t\tscalar.data = sess->ec_ctx.pkey.data;\n+\t\tscalar.length = sess->ec_ctx.pkey.length;\n+\t\tcnxk_ae_ecfpm_prep(&scalar, meta_buf, fpm_iova, ec_grp[curveid],\n+\t\t\tcurveid, inst);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_PUB_KEY_VERIFY:\n+\t\tscalar.data = ec_grp[curveid]->order.data;\n+\t\tscalar.length = ec_grp[curveid]->order.length;\n+\t\tcnxk_ae_ecpm_prep(&scalar, &ecdh->pub_key, meta_buf,\n+\t\t\tec_grp[curveid], curveid, inst);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_SHARED_SECRET_COMPUTE:\n+\t\tscalar.data = sess->ec_ctx.pkey.data;\n+\t\tscalar.length = sess->ec_ctx.pkey.length;\n+\t\tpoint.x.data = sess->ec_ctx.q.x.data;\n+\t\tpoint.x.length = sess->ec_ctx.q.x.length;\n+\t\tpoint.y.data = sess->ec_ctx.q.y.data;\n+\t\tpoint.y.length = sess->ec_ctx.q.y.length;\n+\t\tcnxk_ae_ecpm_prep(&scalar, &point, meta_buf,\n+\t\t\tec_grp[curveid], curveid, inst);\n+\t\tbreak;\n+\tdefault:\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\tret = -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static __rte_always_inline void\n cnxk_ae_dequeue_rsa_op(struct rte_crypto_op *cop, uint8_t *rptr,\n \t\t struct rte_crypto_rsa_xform *rsa_ctx)\n@@ -1143,6 +1216,37 @@ cnxk_ae_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm, uint8_t *rptr,\n \tecpm->r.y.length = prime_len;\n }\n \n+static __rte_always_inline void\n+cnxk_ae_dequeue_ecdh_op(struct rte_crypto_ecdh_op_param *ecdh, uint8_t *rptr,\n+\t\t\tstruct roc_ae_ec_ctx *ec,\n+\t\t\tstruct roc_ae_ec_group **ec_grp)\n+{\n+\tint prime_len = ec_grp[ec->curveid]->prime.length;\n+\n+\tswitch (ecdh->ke_type) {\n+\tcase RTE_CRYPTO_ASYM_KE_PRIV_KEY_GENERATE:\n+\t\tmemcpy(ecdh->priv_key.data, rptr, prime_len);\n+\t\tecdh->priv_key.length = prime_len;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_PUB_KEY_GENERATE:\n+\t\tmemcpy(ecdh->pub_key.x.data, rptr, prime_len);\n+\t\tmemcpy(ecdh->pub_key.y.data, rptr + RTE_ALIGN_CEIL(prime_len, 8), prime_len);\n+\t\tecdh->pub_key.x.length = prime_len;\n+\t\tecdh->pub_key.y.length = prime_len;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_PUB_KEY_VERIFY:\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_KE_SHARED_SECRET_COMPUTE:\n+\t\tmemcpy(ecdh->shared_secret.x.data, rptr, prime_len);\n+\t\tmemcpy(ecdh->shared_secret.y.data, rptr + RTE_ALIGN_CEIL(prime_len, 8), prime_len);\n+\t\tecdh->shared_secret.x.length = prime_len;\n+\t\tecdh->shared_secret.y.length = prime_len;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n static __rte_always_inline void *\n cnxk_ae_alloc_meta(struct roc_ae_buf_ptr *buf,\n \t\t struct rte_mempool *cpt_meta_pool,\n@@ -1206,20 +1310,27 @@ cnxk_ae_enqueue(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \t\t\tgoto req_fail;\n \t\tbreak;\n \tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n-\t\tret = cnxk_ae_ecpm_prep(&asym_op->ecpm, &meta_buf,\n+\t\tret = cnxk_ae_ecpm_prep(&asym_op->ecpm.scalar, &asym_op->ecpm.p, &meta_buf,\n \t\t\t\t\tsess->ec_grp[sess->ec_ctx.curveid],\n \t\t\t\t\tsess->ec_ctx.curveid, inst);\n \t\tif (unlikely(ret))\n \t\t\tgoto req_fail;\n \t\tbreak;\n \tcase RTE_CRYPTO_ASYM_XFORM_ECFPM:\n-\t\tret = cnxk_ae_ecfpm_prep(&asym_op->ecpm, &meta_buf,\n+\t\tret = cnxk_ae_ecfpm_prep(&asym_op->ecpm.scalar, &meta_buf,\n \t\t\t\t\t sess->cnxk_fpm_iova,\n \t\t\t\t\t sess->ec_grp[sess->ec_ctx.curveid],\n \t\t\t\t\t sess->ec_ctx.curveid, inst);\n \t\tif (unlikely(ret))\n \t\t\tgoto req_fail;\n \t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECDH:\n+\t\tret = cnxk_ae_enqueue_ecdh_op(op, &meta_buf, sess,\n+\t\t\t\t\t sess->cnxk_fpm_iova,\n+\t\t\t\t\t sess->ec_grp, inst);\n+\t\tif (unlikely(ret))\n+\t\t\tgoto req_fail;\n+\t\tbreak;\n \tdefault:\n \t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n \t\tret = -EINVAL;\n@@ -1262,6 +1373,10 @@ cnxk_ae_post_process(struct rte_crypto_op *cop, struct cnxk_ae_sess *sess,\n \t\tcnxk_ae_dequeue_ecpm_op(&op->ecpm, rptr, &sess->ec_ctx,\n \t\t\t\t\tsess->ec_grp);\n \t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECDH:\n+\t\tcnxk_ae_dequeue_ecdh_op(&op->ecdh, rptr, &sess->ec_ctx,\n+\t\t\t\t\tsess->ec_grp);\n+\t\tbreak;\n \tdefault:\n \t\tcop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n \t\tbreak;\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h\nindex 9a321aa8c9..d0ad881f2f 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h\n@@ -10,7 +10,7 @@\n \n #include \"roc_cpt.h\"\n \n-#define CNXK_CPT_MAX_CAPS\t 54\n+#define CNXK_CPT_MAX_CAPS\t 55\n #define CNXK_SEC_CRYPTO_MAX_CAPS 16\n #define CNXK_SEC_MAX_CAPS\t 9\n #define CNXK_AE_EC_ID_MAX\t 9\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\nindex b4864f66bf..2676b52832 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n@@ -92,6 +92,20 @@ static const struct rte_cryptodev_capabilities caps_mul[] = {\n \t\t\t},\n \t\t}\n \t},\n+\t{\t/* ECDH */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n+\t\t{.asym = {\n+\t\t\t.xform_capa = {\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDH,\n+\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_KE_PRIV_KEY_GENERATE) |\n+\t\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_KE_PUB_KEY_GENERATE) |\n+\t\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_KE_PUB_KEY_VERIFY) |\n+\t\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_KE_SHARED_SECRET_COMPUTE)\n+\t\t\t\t\t\t),\n+\t\t\t\t}\n+\t\t\t},\n+\t\t}\n+\t},\n };\n \n static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {\n", "prefixes": [ "v1", "4/4" ] }