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{
    "id": 133353,
    "url": "http://patches.dpdk.org/api/patches/133353/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231026064324.177531-15-chaoyong.he@corigine.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
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        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20231026064324.177531-15-chaoyong.he@corigine.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20231026064324.177531-15-chaoyong.he@corigine.com",
    "date": "2023-10-26T06:43:13",
    "name": "[v3,14/25] drivers: add the nfp common module",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "d74655c4a296b1ff9aac8b18b049bc8d437becb3",
    "submitter": {
        "id": 2554,
        "url": "http://patches.dpdk.org/api/people/2554/?format=api",
        "name": "Chaoyong He",
        "email": "chaoyong.he@corigine.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231026064324.177531-15-chaoyong.he@corigine.com/mbox/",
    "series": [
        {
            "id": 29991,
            "url": "http://patches.dpdk.org/api/series/29991/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29991",
            "date": "2023-10-26T06:42:59",
            "name": "add the NFP vDPA PMD",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/29991/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/133353/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/133353/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Chaoyong He <chaoyong.he@corigine.com>",
        "To": "dev@dpdk.org",
        "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>",
        "Subject": "[PATCH v3 14/25] drivers: add the nfp common module",
        "Date": "Thu, 26 Oct 2023 14:43:13 +0800",
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    "content": "Add the nfp common module in the nfp common library.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Long Wu <long.wu@corigine.com>\nReviewed-by: Peng Zhang <peng.zhang@corigine.com>\n---\n drivers/common/nfp/meson.build   |   3 +-\n drivers/common/nfp/nfp_common.c  | 177 +++++++++++++++++++++++\n drivers/common/nfp/nfp_common.h  | 232 +++++++++++++++++++++++++++++++\n drivers/common/nfp/version.map   |   6 +\n drivers/net/nfp/nfp_ethdev.c     |   4 +-\n drivers/net/nfp/nfp_ethdev_vf.c  |  16 +--\n drivers/net/nfp/nfp_net_common.c | 159 +--------------------\n drivers/net/nfp/nfp_net_common.h | 206 +--------------------------\n 8 files changed, 423 insertions(+), 380 deletions(-)\n create mode 100644 drivers/common/nfp/nfp_common.c\n create mode 100644 drivers/common/nfp/nfp_common.h",
    "diff": "diff --git a/drivers/common/nfp/meson.build b/drivers/common/nfp/meson.build\nindex cda5a930c7..cca7fb7796 100644\n--- a/drivers/common/nfp/meson.build\n+++ b/drivers/common/nfp/meson.build\n@@ -7,8 +7,9 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n endif\n \n sources = files(\n+        'nfp_common.c',\n         'nfp_common_log.c',\n         'nfp_common_pci.c',\n )\n \n-deps += ['bus_pci']\n+deps += ['bus_pci', 'net']\ndiff --git a/drivers/common/nfp/nfp_common.c b/drivers/common/nfp/nfp_common.c\nnew file mode 100644\nindex 0000000000..1a98326980\n--- /dev/null\n+++ b/drivers/common/nfp/nfp_common.c\n@@ -0,0 +1,177 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Corigine, Inc.\n+ * All rights reserved.\n+ */\n+\n+#include \"nfp_common.h\"\n+\n+#include \"nfp_common_log.h\"\n+\n+/*\n+ * This is used by the reconfig protocol. It sets the maximum time waiting in\n+ * milliseconds before a reconfig timeout happens.\n+ */\n+#define NFP_NET_POLL_TIMEOUT    5000\n+\n+int\n+nfp_reconfig_real(struct nfp_hw *hw,\n+\t\tuint32_t update)\n+{\n+\tuint32_t cnt;\n+\tuint32_t new;\n+\tstruct timespec wait;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Writing to the configuration queue (%p)...\",\n+\t\t\thw->qcp_cfg);\n+\n+\tif (hw->qcp_cfg == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Bad configuration queue pointer\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\tnfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);\n+\n+\twait.tv_sec = 0;\n+\twait.tv_nsec = 1000000; /* 1ms */\n+\n+\tPMD_DRV_LOG(DEBUG, \"Polling for update ack...\");\n+\n+\t/* Poll update field, waiting for NFP to ack the config */\n+\tfor (cnt = 0; ; cnt++) {\n+\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n+\t\tif (new == 0)\n+\t\t\tbreak;\n+\n+\t\tif ((new & NFP_NET_CFG_UPDATE_ERR) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Reconfig error: %#08x\", new);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tif (cnt >= NFP_NET_POLL_TIMEOUT) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Reconfig timeout for %#08x after %u ms\",\n+\t\t\t\t\tupdate, cnt);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tnanosleep(&wait, 0); /* waiting for a 1ms */\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"Ack DONE\");\n+\treturn 0;\n+}\n+\n+/**\n+ * Reconfigure the NIC.\n+ *\n+ * Write the update word to the BAR and ping the reconfig queue. Then poll\n+ * until the firmware has acknowledged the update by zeroing the update word.\n+ *\n+ * @param hw\n+ *   Device to reconfigure.\n+ * @param ctrl\n+ *   The value for the ctrl field in the BAR config.\n+ * @param update\n+ *   The value for the update field in the BAR config.\n+ *\n+ * @return\n+ *   - (0) if OK to reconfigure the device.\n+ *   - (-EIO) if I/O err and fail to reconfigure the device.\n+ */\n+int\n+nfp_reconfig(struct nfp_hw *hw,\n+\t\tuint32_t ctrl,\n+\t\tuint32_t update)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->reconfig_lock);\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n+\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\n+\trte_wmb();\n+\n+\tret = nfp_reconfig_real(hw, update);\n+\n+\trte_spinlock_unlock(&hw->reconfig_lock);\n+\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Error nfp reconfig: ctrl=%#08x update=%#08x\",\n+\t\t\t\tctrl, update);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Reconfigure the NIC for the extend ctrl BAR.\n+ *\n+ * Write the update word to the BAR and ping the reconfig queue. Then poll\n+ * until the firmware has acknowledged the update by zeroing the update word.\n+ *\n+ * @param hw\n+ *   Device to reconfigure.\n+ * @param ctrl_ext\n+ *   The value for the first word of extend ctrl field in the BAR config.\n+ * @param update\n+ *   The value for the update field in the BAR config.\n+ *\n+ * @return\n+ *   - (0) if OK to reconfigure the device.\n+ *   - (-EIO) if I/O err and fail to reconfigure the device.\n+ */\n+int\n+nfp_ext_reconfig(struct nfp_hw *hw,\n+\t\tuint32_t ctrl_ext,\n+\t\tuint32_t update)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->reconfig_lock);\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL_WORD1, ctrl_ext);\n+\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\n+\trte_wmb();\n+\n+\tret = nfp_reconfig_real(hw, update);\n+\n+\trte_spinlock_unlock(&hw->reconfig_lock);\n+\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Error nfp ext reconfig: ctrl_ext=%#08x update=%#08x\",\n+\t\t\t\tctrl_ext, update);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+nfp_read_mac(struct nfp_hw *hw)\n+{\n+\tuint32_t tmp;\n+\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));\n+\tmemcpy(&hw->mac_addr.addr_bytes[0], &tmp, 4);\n+\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));\n+\tmemcpy(&hw->mac_addr.addr_bytes[4], &tmp, 2);\n+}\n+\n+void\n+nfp_write_mac(struct nfp_hw *hw,\n+\t\tuint8_t *mac)\n+{\n+\tuint32_t mac0;\n+\tuint16_t mac1;\n+\n+\tmac0 = *(uint32_t *)mac;\n+\tnn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);\n+\n+\tmac += 4;\n+\tmac1 = *(uint16_t *)mac;\n+\tnn_writew(rte_cpu_to_be_16(mac1),\n+\t\t\thw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);\n+}\ndiff --git a/drivers/common/nfp/nfp_common.h b/drivers/common/nfp/nfp_common.h\nnew file mode 100644\nindex 0000000000..5615cde6af\n--- /dev/null\n+++ b/drivers/common/nfp/nfp_common.h\n@@ -0,0 +1,232 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Corigine, Inc.\n+ * All rights reserved.\n+ */\n+\n+#ifndef __NFP_COMMON_H__\n+#define __NFP_COMMON_H__\n+\n+#include <rte_byteorder.h>\n+#include <rte_ether.h>\n+#include <rte_io.h>\n+#include <rte_spinlock.h>\n+\n+#include \"nfp_common_ctrl.h\"\n+\n+#define NFP_QCP_QUEUE_ADDR_SZ   (0x800)\n+\n+/* Macros for accessing the Queue Controller Peripheral 'CSRs' */\n+#define NFP_QCP_QUEUE_OFF(_x)                 ((_x) * 0x800)\n+#define NFP_QCP_QUEUE_ADD_RPTR                  0x0000\n+#define NFP_QCP_QUEUE_ADD_WPTR                  0x0004\n+#define NFP_QCP_QUEUE_STS_LO                    0x0008\n+#define NFP_QCP_QUEUE_STS_LO_READPTR_MASK     (0x3ffff)\n+#define NFP_QCP_QUEUE_STS_HI                    0x000c\n+#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK    (0x3ffff)\n+\n+/* Read or Write Pointer of a queue */\n+enum nfp_qcp_ptr {\n+\tNFP_QCP_READ_PTR = 0,\n+\tNFP_QCP_WRITE_PTR\n+};\n+\n+struct nfp_hw {\n+\tuint8_t *ctrl_bar;\n+\tuint8_t *qcp_cfg;\n+\tuint32_t cap;\n+\tuint32_t cap_ext;\n+\tuint32_t ctrl;\n+\tuint32_t ctrl_ext;\n+\trte_spinlock_t reconfig_lock;\n+\tstruct rte_ether_addr mac_addr;\n+};\n+\n+static inline uint8_t\n+nn_readb(volatile const void *addr)\n+{\n+\treturn rte_read8(addr);\n+}\n+\n+static inline void\n+nn_writeb(uint8_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write8(val, addr);\n+}\n+\n+static inline uint32_t\n+nn_readl(volatile const void *addr)\n+{\n+\treturn rte_read32(addr);\n+}\n+\n+static inline void\n+nn_writel(uint32_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write32(val, addr);\n+}\n+\n+static inline uint16_t\n+nn_readw(volatile const void *addr)\n+{\n+\treturn rte_read16(addr);\n+}\n+\n+static inline void\n+nn_writew(uint16_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write16(val, addr);\n+}\n+\n+static inline uint64_t\n+nn_readq(volatile void *addr)\n+{\n+\tuint32_t low;\n+\tuint32_t high;\n+\tconst volatile uint32_t *p = addr;\n+\n+\thigh = nn_readl((volatile const void *)(p + 1));\n+\tlow = nn_readl((volatile const void *)p);\n+\n+\treturn low + ((uint64_t)high << 32);\n+}\n+\n+static inline void\n+nn_writeq(uint64_t val,\n+\t\tvolatile void *addr)\n+{\n+\tnn_writel(val >> 32, (volatile char *)addr + 4);\n+\tnn_writel(val, addr);\n+}\n+\n+static inline uint8_t\n+nn_cfg_readb(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn nn_readb(hw->ctrl_bar + off);\n+}\n+\n+static inline void\n+nn_cfg_writeb(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint8_t val)\n+{\n+\tnn_writeb(val, hw->ctrl_bar + off);\n+}\n+\n+static inline uint16_t\n+nn_cfg_readw(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writew(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint16_t val)\n+{\n+\tnn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off);\n+}\n+\n+static inline uint32_t\n+nn_cfg_readl(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writel(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint32_t val)\n+{\n+\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n+}\n+\n+static inline uint64_t\n+nn_cfg_readq(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writeq(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint64_t val)\n+{\n+\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n+}\n+\n+/**\n+ * Add the value to the selected pointer of a queue.\n+ *\n+ * @param queue\n+ *   Base address for queue structure\n+ * @param ptr\n+ *   Add to the read or write pointer\n+ * @param val\n+ *   Value to add to the queue pointer\n+ */\n+static inline void\n+nfp_qcp_ptr_add(uint8_t *queue,\n+\t\tenum nfp_qcp_ptr ptr,\n+\t\tuint32_t val)\n+{\n+\tuint32_t off;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_ADD_RPTR;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_ADD_WPTR;\n+\n+\tnn_writel(rte_cpu_to_le_32(val), queue + off);\n+}\n+\n+/**\n+ * Read the current read/write pointer value for a queue.\n+ *\n+ * @param queue\n+ *   Base address for queue structure\n+ * @param ptr\n+ *   Read or Write pointer\n+ */\n+static inline uint32_t\n+nfp_qcp_read(uint8_t *queue,\n+\t\tenum nfp_qcp_ptr ptr)\n+{\n+\tuint32_t off;\n+\tuint32_t val;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_STS_LO;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_STS_HI;\n+\n+\tval = rte_cpu_to_le_32(nn_readl(queue + off));\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\treturn val & NFP_QCP_QUEUE_STS_LO_READPTR_MASK;\n+\telse\n+\t\treturn val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK;\n+}\n+\n+__rte_internal\n+int nfp_reconfig_real(struct nfp_hw *hw, uint32_t update);\n+\n+__rte_internal\n+int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update);\n+\n+__rte_internal\n+int nfp_ext_reconfig(struct nfp_hw *hw, uint32_t ctrl_ext, uint32_t update);\n+\n+__rte_internal\n+void nfp_read_mac(struct nfp_hw *hw);\n+\n+__rte_internal\n+void nfp_write_mac(struct nfp_hw *hw, uint8_t *mac);\n+\n+#endif/* __NFP_COMMON_H__ */\ndiff --git a/drivers/common/nfp/version.map b/drivers/common/nfp/version.map\nindex 25e48c39d6..f6a54a97cd 100644\n--- a/drivers/common/nfp/version.map\n+++ b/drivers/common/nfp/version.map\n@@ -3,5 +3,11 @@ INTERNAL {\n \n \tnfp_class_driver_register;\n \n+\tnfp_reconfig;\n+\tnfp_ext_reconfig;\n+\tnfp_reconfig_real;\n+\tnfp_read_mac;\n+\tnfp_write_mac;\n+\n \tlocal: *;\n };\ndiff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c\nindex 3d4b78fbf1..76317925ec 100644\n--- a/drivers/net/nfp/nfp_ethdev.c\n+++ b/drivers/net/nfp/nfp_ethdev.c\n@@ -600,13 +600,13 @@ nfp_net_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \tnfp_net_pf_read_mac(app_fw_nic, port);\n-\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \n \tif (rte_is_valid_assigned_ether_addr(&hw->mac_addr) == 0) {\n \t\tPMD_INIT_LOG(INFO, \"Using random mac address for port %d\", port);\n \t\t/* Using random mac addresses for VFs */\n \t\trte_eth_random_addr(&hw->mac_addr.addr_bytes[0]);\n-\t\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\t\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \t}\n \n \t/* Copying mac address to DPDK eth_dev struct */\ndiff --git a/drivers/net/nfp/nfp_ethdev_vf.c b/drivers/net/nfp/nfp_ethdev_vf.c\nindex 049728d30c..b9cfb48021 100644\n--- a/drivers/net/nfp/nfp_ethdev_vf.c\n+++ b/drivers/net/nfp/nfp_ethdev_vf.c\n@@ -15,18 +15,6 @@\n #include \"nfp_logs.h\"\n #include \"nfp_net_common.h\"\n \n-static void\n-nfp_netvf_read_mac(struct nfp_hw *hw)\n-{\n-\tuint32_t tmp;\n-\n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));\n-\tmemcpy(&hw->mac_addr.addr_bytes[0], &tmp, 4);\n-\n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));\n-\tmemcpy(&hw->mac_addr.addr_bytes[4], &tmp, 2);\n-}\n-\n static int\n nfp_netvf_start(struct rte_eth_dev *dev)\n {\n@@ -334,12 +322,12 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \t\tgoto dev_err_ctrl_map;\n \t}\n \n-\tnfp_netvf_read_mac(hw);\n+\tnfp_read_mac(hw);\n \tif (rte_is_valid_assigned_ether_addr(&hw->mac_addr) == 0) {\n \t\tPMD_INIT_LOG(INFO, \"Using random mac address for port %hu\", port);\n \t\t/* Using random mac addresses for VFs */\n \t\trte_eth_random_addr(&hw->mac_addr.addr_bytes[0]);\n-\t\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\t\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \t}\n \n \t/* Copying mac address to DPDK eth_dev struct */\ndiff --git a/drivers/net/nfp/nfp_net_common.c b/drivers/net/nfp/nfp_net_common.c\nindex 01574de963..711532b466 100644\n--- a/drivers/net/nfp/nfp_net_common.c\n+++ b/drivers/net/nfp/nfp_net_common.c\n@@ -19,12 +19,6 @@\n #define NFP_TX_MAX_SEG       UINT8_MAX\n #define NFP_TX_MAX_MTU_SEG   8\n \n-/*\n- * This is used by the reconfig protocol. It sets the maximum time waiting in\n- * milliseconds before a reconfig timeout happens.\n- */\n-#define NFP_NET_POLL_TIMEOUT    5000\n-\n #define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */\n #define NFP_NET_LINK_UP_CHECK_TIMEOUT   1000 /* ms */\n \n@@ -198,141 +192,6 @@ nfp_net_notify_port_speed(struct nfp_net_hw *hw,\n /* The length of firmware version string */\n #define FW_VER_LEN        32\n \n-static int\n-nfp_reconfig_real(struct nfp_hw *hw,\n-\t\tuint32_t update)\n-{\n-\tuint32_t cnt;\n-\tuint32_t new;\n-\tstruct timespec wait;\n-\n-\tPMD_DRV_LOG(DEBUG, \"Writing to the configuration queue (%p)...\",\n-\t\t\thw->qcp_cfg);\n-\n-\tif (hw->qcp_cfg == NULL) {\n-\t\tPMD_DRV_LOG(ERR, \"Bad configuration queue pointer\");\n-\t\treturn -ENXIO;\n-\t}\n-\n-\tnfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);\n-\n-\twait.tv_sec = 0;\n-\twait.tv_nsec = 1000000; /* 1ms */\n-\n-\tPMD_DRV_LOG(DEBUG, \"Polling for update ack...\");\n-\n-\t/* Poll update field, waiting for NFP to ack the config */\n-\tfor (cnt = 0; ; cnt++) {\n-\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n-\t\tif (new == 0)\n-\t\t\tbreak;\n-\n-\t\tif ((new & NFP_NET_CFG_UPDATE_ERR) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Reconfig error: %#08x\", new);\n-\t\t\treturn -1;\n-\t\t}\n-\n-\t\tif (cnt >= NFP_NET_POLL_TIMEOUT) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Reconfig timeout for %#08x after %u ms\",\n-\t\t\t\t\tupdate, cnt);\n-\t\t\treturn -EIO;\n-\t\t}\n-\n-\t\tnanosleep(&wait, 0); /* Waiting for a 1ms */\n-\t}\n-\n-\tPMD_DRV_LOG(DEBUG, \"Ack DONE\");\n-\treturn 0;\n-}\n-\n-/**\n- * Reconfigure the NIC.\n- *\n- * Write the update word to the BAR and ping the reconfig queue. Then poll\n- * until the firmware has acknowledged the update by zeroing the update word.\n- *\n- * @param hw\n- *   Device to reconfigure.\n- * @param ctrl\n- *   The value for the ctrl field in the BAR config.\n- * @param update\n- *   The value for the update field in the BAR config.\n- *\n- * @return\n- *   - (0) if OK to reconfigure the device.\n- *   - (-EIO) if I/O err and fail to reconfigure the device.\n- */\n-int\n-nfp_reconfig(struct nfp_hw *hw,\n-\t\tuint32_t ctrl,\n-\t\tuint32_t update)\n-{\n-\tint ret;\n-\n-\trte_spinlock_lock(&hw->reconfig_lock);\n-\n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n-\n-\trte_wmb();\n-\n-\tret = nfp_reconfig_real(hw, update);\n-\n-\trte_spinlock_unlock(&hw->reconfig_lock);\n-\n-\tif (ret != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"Error nfp reconfig: ctrl=%#08x update=%#08x\",\n-\t\t\t\tctrl, update);\n-\t\treturn -EIO;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/**\n- * Reconfigure the NIC for the extend ctrl BAR.\n- *\n- * Write the update word to the BAR and ping the reconfig queue. Then poll\n- * until the firmware has acknowledged the update by zeroing the update word.\n- *\n- * @param hw\n- *   Device to reconfigure.\n- * @param ctrl_ext\n- *   The value for the first word of extend ctrl field in the BAR config.\n- * @param update\n- *   The value for the update field in the BAR config.\n- *\n- * @return\n- *   - (0) if OK to reconfigure the device.\n- *   - (-EIO) if I/O err and fail to reconfigure the device.\n- */\n-int\n-nfp_ext_reconfig(struct nfp_hw *hw,\n-\t\tuint32_t ctrl_ext,\n-\t\tuint32_t update)\n-{\n-\tint ret;\n-\n-\trte_spinlock_lock(&hw->reconfig_lock);\n-\n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL_WORD1, ctrl_ext);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n-\n-\trte_wmb();\n-\n-\tret = nfp_reconfig_real(hw, update);\n-\n-\trte_spinlock_unlock(&hw->reconfig_lock);\n-\n-\tif (ret != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"Error nfp ext reconfig: ctrl_ext=%#08x update=%#08x\",\n-\t\t\t\tctrl_ext, update);\n-\t\treturn -EIO;\n-\t}\n-\n-\treturn 0;\n-}\n-\n /**\n  * Reconfigure the firmware via the mailbox\n  *\n@@ -531,22 +390,6 @@ nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)\n \thw->super.qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;\n }\n \n-void\n-nfp_net_write_mac(struct nfp_hw *hw,\n-\t\tuint8_t *mac)\n-{\n-\tuint32_t mac0;\n-\tuint16_t mac1;\n-\n-\tmac0 = *(uint32_t *)mac;\n-\tnn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);\n-\n-\tmac += 4;\n-\tmac1 = *(uint16_t *)mac;\n-\tnn_writew(rte_cpu_to_be_16(mac1),\n-\t\t\thw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);\n-}\n-\n int\n nfp_net_set_mac_addr(struct rte_eth_dev *dev,\n \t\tstruct rte_ether_addr *mac_addr)\n@@ -565,7 +408,7 @@ nfp_net_set_mac_addr(struct rte_eth_dev *dev,\n \t}\n \n \t/* Writing new MAC to the specific port BAR address */\n-\tnfp_net_write_mac(hw, (uint8_t *)mac_addr);\n+\tnfp_write_mac(hw, (uint8_t *)mac_addr);\n \n \tupdate = NFP_NET_CFG_UPDATE_MACADDR;\n \tctrl = hw->ctrl;\ndiff --git a/drivers/net/nfp/nfp_net_common.h b/drivers/net/nfp/nfp_net_common.h\nindex e997756091..9461440d0b 100644\n--- a/drivers/net/nfp/nfp_net_common.h\n+++ b/drivers/net/nfp/nfp_net_common.h\n@@ -8,21 +8,12 @@\n \n #include <bus_pci_driver.h>\n #include <ethdev_driver.h>\n-#include <rte_io.h>\n+#include <nfp_common.h>\n #include <rte_spinlock.h>\n \n #include \"nfp_net_ctrl.h\"\n #include \"nfpcore/nfp_dev.h\"\n \n-/* Macros for accessing the Queue Controller Peripheral 'CSRs' */\n-#define NFP_QCP_QUEUE_OFF(_x)                 ((_x) * 0x800)\n-#define NFP_QCP_QUEUE_ADD_RPTR                  0x0000\n-#define NFP_QCP_QUEUE_ADD_WPTR                  0x0004\n-#define NFP_QCP_QUEUE_STS_LO                    0x0008\n-#define NFP_QCP_QUEUE_STS_LO_READPTR_MASK     (0x3ffff)\n-#define NFP_QCP_QUEUE_STS_HI                    0x000c\n-#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK    (0x3ffff)\n-\n /* Interrupt definitions */\n #define NFP_NET_IRQ_LSC_IDX             0\n \n@@ -42,8 +33,6 @@\n /* Alignment for dma zones */\n #define NFP_MEMZONE_ALIGN       128\n \n-#define NFP_QCP_QUEUE_ADDR_SZ   (0x800)\n-\n /* Number of supported physical ports */\n #define NFP_MAX_PHYPORTS        12\n \n@@ -53,12 +42,6 @@ enum nfp_app_fw_id {\n \tNFP_APP_FW_FLOWER_NIC             = 0x3,\n };\n \n-/* Read or Write Pointer of a queue */\n-enum nfp_qcp_ptr {\n-\tNFP_QCP_READ_PTR = 0,\n-\tNFP_QCP_WRITE_PTR\n-};\n-\n enum nfp_net_meta_format {\n \tNFP_NET_METAFORMAT_SINGLE,\n \tNFP_NET_METAFORMAT_CHAINED,\n@@ -112,17 +95,6 @@ struct nfp_app_fw_nic {\n \tuint8_t total_phyports;\n };\n \n-struct nfp_hw {\n-\tuint8_t *ctrl_bar;\n-\tuint8_t *qcp_cfg;\n-\tuint32_t cap;\n-\tuint32_t cap_ext;\n-\tuint32_t ctrl;\n-\tuint32_t ctrl_ext;\n-\trte_spinlock_t reconfig_lock;\n-\tstruct rte_ether_addr mac_addr;\n-};\n-\n struct nfp_net_hw {\n \t/** The parent class */\n \tstruct nfp_hw super;\n@@ -184,179 +156,6 @@ struct nfp_net_adapter {\n \tstruct nfp_net_hw hw;\n };\n \n-static inline uint8_t\n-nn_readb(volatile const void *addr)\n-{\n-\treturn rte_read8(addr);\n-}\n-\n-static inline void\n-nn_writeb(uint8_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write8(val, addr);\n-}\n-\n-static inline uint32_t\n-nn_readl(volatile const void *addr)\n-{\n-\treturn rte_read32(addr);\n-}\n-\n-static inline void\n-nn_writel(uint32_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write32(val, addr);\n-}\n-\n-static inline uint16_t\n-nn_readw(volatile const void *addr)\n-{\n-\treturn rte_read16(addr);\n-}\n-\n-static inline void\n-nn_writew(uint16_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write16(val, addr);\n-}\n-\n-static inline uint64_t\n-nn_readq(volatile void *addr)\n-{\n-\tuint32_t low;\n-\tuint32_t high;\n-\tconst volatile uint32_t *p = addr;\n-\n-\thigh = nn_readl((volatile const void *)(p + 1));\n-\tlow = nn_readl((volatile const void *)p);\n-\n-\treturn low + ((uint64_t)high << 32);\n-}\n-\n-static inline void\n-nn_writeq(uint64_t val,\n-\t\tvolatile void *addr)\n-{\n-\tnn_writel(val >> 32, (volatile char *)addr + 4);\n-\tnn_writel(val, addr);\n-}\n-\n-static inline uint8_t\n-nn_cfg_readb(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn nn_readb(hw->ctrl_bar + off);\n-}\n-\n-static inline void\n-nn_cfg_writeb(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint8_t val)\n-{\n-\tnn_writeb(val, hw->ctrl_bar + off);\n-}\n-\n-static inline uint16_t\n-nn_cfg_readw(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writew(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint16_t val)\n-{\n-\tnn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off);\n-}\n-\n-static inline uint32_t\n-nn_cfg_readl(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writel(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint32_t val)\n-{\n-\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n-}\n-\n-static inline uint64_t\n-nn_cfg_readq(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writeq(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint64_t val)\n-{\n-\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n-}\n-\n-/**\n- * Add the value to the selected pointer of a queue.\n- *\n- * @param queue\n- *   Base address for queue structure\n- * @param ptr\n- *   Add to the read or write pointer\n- * @param val\n- *   Value to add to the queue pointer\n- */\n-static inline void\n-nfp_qcp_ptr_add(uint8_t *queue,\n-\t\tenum nfp_qcp_ptr ptr,\n-\t\tuint32_t val)\n-{\n-\tuint32_t off;\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\toff = NFP_QCP_QUEUE_ADD_RPTR;\n-\telse\n-\t\toff = NFP_QCP_QUEUE_ADD_WPTR;\n-\n-\tnn_writel(rte_cpu_to_le_32(val), queue + off);\n-}\n-\n-/**\n- * Read the current read/write pointer value for a queue.\n- *\n- * @param queue\n- *   Base address for queue structure\n- * @param ptr\n- *   Read or Write pointer\n- */\n-static inline uint32_t\n-nfp_qcp_read(uint8_t *queue,\n-\t\tenum nfp_qcp_ptr ptr)\n-{\n-\tuint32_t off;\n-\tuint32_t val;\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\toff = NFP_QCP_QUEUE_STS_LO;\n-\telse\n-\t\toff = NFP_QCP_QUEUE_STS_HI;\n-\n-\tval = rte_cpu_to_le_32(nn_readl(queue + off));\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\treturn val & NFP_QCP_QUEUE_STS_LO_READPTR_MASK;\n-\telse\n-\t\treturn val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK;\n-}\n-\n static inline uint32_t\n nfp_qcp_queue_offset(const struct nfp_dev_info *dev_info,\n \t\tuint16_t queue)\n@@ -366,8 +165,6 @@ nfp_qcp_queue_offset(const struct nfp_dev_info *dev_info,\n }\n \n /* Prototypes for common NFP functions */\n-int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update);\n-int nfp_ext_reconfig(struct nfp_hw *hw, uint32_t ctrl_ext, uint32_t update);\n int nfp_net_mbox_reconfig(struct nfp_net_hw *hw, uint32_t mbox_cmd);\n int nfp_net_configure(struct rte_eth_dev *dev);\n int nfp_net_common_init(struct rte_pci_device *pci_dev, struct nfp_net_hw *hw);\n@@ -375,7 +172,6 @@ void nfp_net_log_device_information(const struct nfp_net_hw *hw);\n void nfp_net_enable_queues(struct rte_eth_dev *dev);\n void nfp_net_disable_queues(struct rte_eth_dev *dev);\n void nfp_net_params_setup(struct nfp_net_hw *hw);\n-void nfp_net_write_mac(struct nfp_hw *hw, uint8_t *mac);\n int nfp_net_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);\n int nfp_configure_rx_interrupt(struct rte_eth_dev *dev,\n \t\tstruct rte_intr_handle *intr_handle);\n",
    "prefixes": [
        "v3",
        "14/25"
    ]
}