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GET /api/patches/133261/?format=api
{ "id": 133261, "url": "http://patches.dpdk.org/api/patches/133261/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231024102128.16832-2-shaibran@amazon.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231024102128.16832-2-shaibran@amazon.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231024102128.16832-2-shaibran@amazon.com", "date": "2023-10-24T10:21:24", "name": "[1/5] net/ena: hal upgrade", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "43f7b58fb56c926506d052bb2f88ac5ffac8eee9", "submitter": { "id": 2930, "url": "http://patches.dpdk.org/api/people/2930/?format=api", "name": "Brandes, Shai", "email": "shaibran@amazon.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231024102128.16832-2-shaibran@amazon.com/mbox/", "series": [ { "id": 29965, "url": "http://patches.dpdk.org/api/series/29965/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29965", "date": "2023-10-24T10:21:23", "name": "net/ena: v2.8.0 driver release", "version": 1, "mbox": "http://patches.dpdk.org/series/29965/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133261/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133261/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17EC0431EF;\n\tTue, 24 Oct 2023 12:21:51 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 02BC640EA5;\n\tTue, 24 Oct 2023 12:21:51 +0200 (CEST)", "from smtp-fw-6001.amazon.com (smtp-fw-6001.amazon.com\n [52.95.48.154])\n by mails.dpdk.org (Postfix) with ESMTP id 770F9406FF\n for <dev@dpdk.org>; Tue, 24 Oct 2023 12:21:49 +0200 (CEST)", "from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO\n email-inbound-relay-pdx-2c-m6i4x-8c5b1df3.us-west-2.amazon.com) ([10.43.8.2])\n by smtp-border-fw-6001.iad6.amazon.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 10:21:49 +0000", "from smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev\n (pdx2-ws-svc-p26-lb5-vlan3.pdx.amazon.com [10.39.38.70])\n by email-inbound-relay-pdx-2c-m6i4x-8c5b1df3.us-west-2.amazon.com (Postfix)\n with ESMTPS id 9C08F40D6A; Tue, 24 Oct 2023 10:21:47 +0000 (UTC)", "from EX19MTAEUA002.ant.amazon.com [10.0.10.100:25988]\n by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.0.200:2525]\n with esmtp (Farcaster)\n id e07b889a-3932-4563-8d29-bf5d4168cf9b;\n Tue, 24 Oct 2023 10:21:45 +0000 (UTC)", "from EX19D011EUB003.ant.amazon.com (10.252.51.108) by\n EX19MTAEUA002.ant.amazon.com (10.252.50.124) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1118.39; Tue, 24 Oct 2023 10:21:38 +0000", "from EX19MTAUWB001.ant.amazon.com (10.250.64.248) by\n EX19D011EUB003.ant.amazon.com (10.252.51.108) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1118.39; Tue, 24 Oct 2023 10:21:37 +0000", "from HFA15-CG15235BS.amazon.com (10.85.143.172) by\n mail-relay.amazon.com (10.250.64.254) with Microsoft SMTP Server id\n 15.2.1118.39 via Frontend Transport; Tue, 24 Oct 2023 10:21:35 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209;\n t=1698142910; x=1729678910;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version;\n bh=XDurN/Uyquuiys75UshG9zPxN5e01kJOVn4s/3bFOxc=;\n b=G+VGWK/COtdVVrvkdmoLoOmDZt2QqcfnUxlBfL5qNwdu1qp8NQssx06/\n XZSE14XsbgODYzMZV2RDg5sQkP3xT3aagQecieb/7QrNwbNDvp5OIpUC2\n PYv+OvkQqCxMdPu4uxZZmNL1Sn7mEF8lukb38ztiLDa0qY+yuLNGZPE2M 0=;", "X-IronPort-AV": "E=Sophos;i=\"6.03,247,1694736000\"; d=\"scan'208\";a=\"366000704\"", "X-Farcaster-Flow-ID": "e07b889a-3932-4563-8d29-bf5d4168cf9b", "From": "<shaibran@amazon.com>", "To": "<ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>, Michal Krawczyk\n <mk@semihalf.com>, Evgeny Schemeilin <evgenys@amazon.com>, Igor Chauskin\n <igorch@amazon.com>, Ron Beider <rbeider@amazon.com>", "Subject": "[PATCH 1/5] net/ena: hal upgrade", "Date": "Tue, 24 Oct 2023 13:21:24 +0300", "Message-ID": "<20231024102128.16832-2-shaibran@amazon.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20231024102128.16832-1-shaibran@amazon.com>", "References": "<20231024102128.16832-1-shaibran@amazon.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shai Brandes <shaibran@amazon.com>\n\nENA maintains a HAL that is shared by all supported host drivers.\nMain features introduced to the HAL:\n[1] Reworked the mechanism that queries the performance metrics\n from the device.\n[2] Added support for a new metric that allows monitoring the\n available tracked connections.\n[3] Added support for a new statistic that counts RX drops due\n to insufficient buffers provided by host.\n[4] Added support for Scalable Reliable Datagram (SRD) metrics\n from ENA Express.\n[5] Added support for querying the LLQ entry size recommendation\n from the device.\n[6] Added support for PTP hardware clock (PHC) feature that\n provides enhanced accuracy (Not supported by the driver).\n[7] Added support for new reset reasons for a suspected CPU\n starvation and for completion descriptor inconsistency.\n[8] Aligned all return error code to a common notation.\n[9] Removed an obsolete queue tail pointer update API.\n\nSigned-off-by: Shai Brandes <shaibran@amazon.com>\nReviewed-by: Amit Bernstein <amitbern@amazon.com>\n---\n doc/guides/rel_notes/release_23_11.rst | 4 +\n drivers/net/ena/base/ena_com.c | 499 +++++++++++++++---\n drivers/net/ena/base/ena_com.h | 197 ++++++-\n .../net/ena/base/ena_defs/ena_admin_defs.h | 198 ++++++-\n .../net/ena/base/ena_defs/ena_eth_io_defs.h | 18 +-\n drivers/net/ena/base/ena_defs/ena_gen_info.h | 4 +-\n drivers/net/ena/base/ena_defs/ena_regs_defs.h | 12 +\n drivers/net/ena/base/ena_eth_com.c | 45 +-\n drivers/net/ena/base/ena_eth_com.h | 30 +-\n drivers/net/ena/base/ena_plat.h | 8 +-\n drivers/net/ena/base/ena_plat_dpdk.h | 49 +-\n drivers/net/ena/ena_ethdev.c | 16 +-\n 12 files changed, 915 insertions(+), 165 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 0a6fc76a9d..e3b0ba58c9 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -144,6 +144,10 @@ New Features\n \n * Added support for Network Service Header (NSH) flow matching.\n \n+* **Updated Amazon Elastic Network Adapter ena net driver.**\n+\n+ * Upgraded ENA HAL to latest version.\n+\n * **Updated Solarflare net driver.**\n \n * Added support for transfer flow action ``INDIRECT`` with subtype ``VXLAN_ENCAP``.\ndiff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c\nindex 5ca36ab6d9..5308e3a0d7 100644\n--- a/drivers/net/ena/base/ena_com.c\n+++ b/drivers/net/ena/base/ena_com.c\n@@ -38,6 +38,12 @@\n \n #define ENA_MAX_ADMIN_POLL_US 5000\n \n+/* PHC definitions */\n+#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 20\n+#define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000\n+#define ENA_PHC_TIMESTAMP_ERROR 0xFFFFFFFFFFFFFFFF\n+#define ENA_PHC_REQ_ID_OFFSET 0xDEAD\n+\n /*****************************************************************************/\n /*****************************************************************************/\n /*****************************************************************************/\n@@ -70,7 +76,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,\n \t\t\t\t dma_addr_t addr)\n {\n \tif ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {\n-\t\tena_trc_err(ena_dev, \"DMA address has more bits than the device supports\\n\");\n+\t\tena_trc_err(ena_dev, \"DMA address has more bits that the device supports\\n\");\n \t\treturn ENA_COM_INVAL;\n \t}\n \n@@ -360,7 +366,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,\n \t\t\tENA_COM_BOUNCE_BUFFER_CNTRL_CNT;\n \t\tio_sq->bounce_buf_ctrl.next_to_use = 0;\n \n-\t\tsize = io_sq->bounce_buf_ctrl.buffer_size *\n+\t\tsize = (size_t)io_sq->bounce_buf_ctrl.buffer_size *\n \t\t\tio_sq->bounce_buf_ctrl.buffers_num;\n \n \t\tENA_MEM_ALLOC_NODE(ena_dev->dmadev,\n@@ -658,7 +664,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t} else {\n \t\tena_trc_err(ena_dev, \"Invalid header location control, supported: 0x%x\\n\",\n \t\t\t supported_feat);\n-\t\treturn -EINVAL;\n+\t\treturn ENA_COM_INVAL;\n \t}\n \n \tif (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {\n@@ -673,7 +679,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t\t\t} else {\n \t\t\t\tena_trc_err(ena_dev, \"Invalid desc_stride_ctrl, supported: 0x%x\\n\",\n \t\t\t\t\t supported_feat);\n-\t\t\t\treturn -EINVAL;\n+\t\t\t\treturn ENA_COM_INVAL;\n \t\t\t}\n \n \t\t\tena_trc_err(ena_dev, \"Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\\n\",\n@@ -702,7 +708,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t\t} else {\n \t\t\tena_trc_err(ena_dev, \"Invalid entry_size_ctrl, supported: 0x%x\\n\",\n \t\t\t\t supported_feat);\n-\t\t\treturn -EINVAL;\n+\t\t\treturn ENA_COM_INVAL;\n \t\t}\n \n \t\tena_trc_err(ena_dev, \"Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\\n\",\n@@ -716,7 +722,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t\t */\n \t\tena_trc_err(ena_dev, \"Illegal entry size %d\\n\",\n \t\t\t llq_info->desc_list_entry_size);\n-\t\treturn -EINVAL;\n+\t\treturn ENA_COM_INVAL;\n \t}\n \n \tif (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)\n@@ -740,7 +746,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t\t} else {\n \t\t\tena_trc_err(ena_dev, \"Invalid descs_num_before_header, supported: 0x%x\\n\",\n \t\t\t\t supported_feat);\n-\t\t\treturn -EINVAL;\n+\t\t\treturn ENA_COM_INVAL;\n \t\t}\n \n \t\tena_trc_err(ena_dev, \"Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\\n\",\n@@ -858,7 +864,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n \t}\n \n \tif (unlikely(i == timeout)) {\n-\t\tena_trc_err(ena_dev, \"Reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\\n\",\n+\t\tena_trc_err(ena_dev, \"Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\\n\",\n \t\t\t mmio_read->seq_num,\n \t\t\t offset,\n \t\t\t read_resp->req_id,\n@@ -1296,9 +1302,6 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,\n \t\t(uintptr_t)cmd_completion.sq_doorbell_offset);\n \n \tif (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {\n-\t\tio_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar\n-\t\t\t\t+ cmd_completion.llq_headers_offset);\n-\n \t\tio_sq->desc_addr.pbuf_dev_addr =\n \t\t\t(u8 __iomem *)((uintptr_t)ena_dev->mem_bar +\n \t\t\tcmd_completion.llq_descriptors_offset);\n@@ -1373,16 +1376,17 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,\n \tcomp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,\n \t\t\t\t\t comp, comp_size);\n \tif (IS_ERR(comp_ctx)) {\n-\t\tif (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))\n+\t\tret = PTR_ERR(comp_ctx);\n+\t\tif (ret == ENA_COM_NO_DEVICE)\n \t\t\tena_trc_dbg(admin_queue->ena_dev,\n-\t\t\t\t \"Failed to submit command [%ld]\\n\",\n-\t\t\t\t PTR_ERR(comp_ctx));\n+\t\t\t\t \"Failed to submit command [%d]\\n\",\n+\t\t\t\t ret);\n \t\telse\n \t\t\tena_trc_err(admin_queue->ena_dev,\n-\t\t\t\t \"Failed to submit command [%ld]\\n\",\n-\t\t\t\t PTR_ERR(comp_ctx));\n+\t\t\t\t \"Failed to submit command [%d]\\n\",\n+\t\t\t\t ret);\n \n-\t\treturn (int)PTR_ERR(comp_ctx);\n+\t\treturn ret;\n \t}\n \n \tret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);\n@@ -1440,11 +1444,6 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev,\n \tio_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +\n \t\tcmd_completion.cq_interrupt_unmask_register_offset);\n \n-\tif (cmd_completion.cq_head_db_register_offset)\n-\t\tio_cq->cq_head_db_reg =\n-\t\t\t(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +\n-\t\t\tcmd_completion.cq_head_db_register_offset);\n-\n \tif (cmd_completion.numa_node_register_offset)\n \t\tio_cq->numa_node_cfg_reg =\n \t\t\t(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +\n@@ -1740,6 +1739,220 @@ void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,\n \tena_dev->admin_queue.auto_polling = polling;\n }\n \n+bool ena_com_phc_supported(struct ena_com_dev *ena_dev)\n+{\n+\treturn ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_PHC_CONFIG);\n+}\n+\n+int ena_com_phc_init(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_com_phc_info *phc = &ena_dev->phc;\n+\n+\tmemset(phc, 0x0, sizeof(*phc));\n+\n+\t/* Allocate shared mem used PHC timestamp retrieved from device */\n+\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n+\t\t\t sizeof(*phc->virt_addr),\n+\t\t\t phc->virt_addr,\n+\t\t\t phc->phys_addr,\n+\t\t\t phc->mem_handle);\n+\tif (unlikely(!phc->virt_addr))\n+\t\treturn ENA_COM_NO_MEM;\n+\n+\tENA_SPINLOCK_INIT(phc->lock);\n+\n+\tphc->virt_addr->req_id = 0;\n+\tphc->virt_addr->timestamp = 0;\n+\n+\treturn 0;\n+}\n+\n+int ena_com_phc_config(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_com_phc_info *phc = &ena_dev->phc;\n+\tstruct ena_admin_get_feat_resp get_feat_resp;\n+\tstruct ena_admin_set_feat_resp set_feat_resp;\n+\tstruct ena_admin_set_feat_cmd set_feat_cmd;\n+\tint ret = 0;\n+\n+\t/* Get device PHC default configuration */\n+\tret = ena_com_get_feature(ena_dev, &get_feat_resp, ENA_ADMIN_PHC_CONFIG, 0);\n+\tif (unlikely(ret)) {\n+\t\tena_trc_err(ena_dev, \"Failed to get PHC feature configuration, error: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Suporting only readless PHC retrieval */\n+\tif (get_feat_resp.u.phc.type != ENA_ADMIN_PHC_TYPE_READLESS) {\n+\t\tena_trc_err(ena_dev, \"Unsupprted PHC type, error: %d\\n\", ENA_COM_UNSUPPORTED);\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n+\n+\t/* Update PHC doorbell offset according to device value, used to write req_id to PHC bar */\n+\tphc->doorbell_offset = get_feat_resp.u.phc.doorbell_offset;\n+\n+\t/* Update PHC expire timeout according to device or default driver value */\n+\tphc->expire_timeout_usec = (get_feat_resp.u.phc.expire_timeout_usec) ?\n+\t\t\t\t get_feat_resp.u.phc.expire_timeout_usec :\n+\t\t\t\t ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC;\n+\n+\t/* Update PHC block timeout according to device or default driver value */\n+\tphc->block_timeout_usec = (get_feat_resp.u.phc.block_timeout_usec) ?\n+\t\t\t\t get_feat_resp.u.phc.block_timeout_usec :\n+\t\t\t\t ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC;\n+\n+\t/* Sanity check - expire timeout must not be above skip timeout */\n+\tif (phc->expire_timeout_usec > phc->block_timeout_usec)\n+\t\tphc->expire_timeout_usec = phc->block_timeout_usec;\n+\n+\t/* Prepare PHC feature command with PHC output address */\n+\tmemset(&set_feat_cmd, 0x0, sizeof(set_feat_cmd));\n+\tset_feat_cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;\n+\tset_feat_cmd.feat_common.feature_id = ENA_ADMIN_PHC_CONFIG;\n+\tset_feat_cmd.u.phc.output_length = sizeof(*phc->virt_addr);\n+\tret = ena_com_mem_addr_set(ena_dev, &set_feat_cmd.u.phc.output_address, phc->phys_addr);\n+\tif (unlikely(ret)) {\n+\t\tena_trc_err(ena_dev, \"Failed setting PHC output address, error: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Send PHC feature command to the device */\n+\tret = ena_com_execute_admin_command(&ena_dev->admin_queue,\n+\t\t\t\t\t (struct ena_admin_aq_entry *)&set_feat_cmd,\n+\t\t\t\t\t sizeof(set_feat_cmd),\n+\t\t\t\t\t (struct ena_admin_acq_entry *)&set_feat_resp,\n+\t\t\t\t\t sizeof(set_feat_resp));\n+\n+\tif (unlikely(ret)) {\n+\t\tena_trc_err(ena_dev, \"Failed to enable PHC, error: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tphc->active = true;\n+\tena_trc_dbg(ena_dev, \"PHC is active in the device\\n\");\n+\n+\treturn ret;\n+}\n+\n+void ena_com_phc_destroy(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_com_phc_info *phc = &ena_dev->phc;\n+\n+\tphc->active = false;\n+\n+\t/* In case PHC is not supported by the device, silently exiting */\n+\tif (!phc->virt_addr)\n+\t\treturn;\n+\n+\tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n+\t\t\t sizeof(*phc->virt_addr),\n+\t\t\t phc->virt_addr,\n+\t\t\t phc->phys_addr,\n+\t\t\t phc->mem_handle);\n+\tphc->virt_addr = NULL;\n+\n+\tENA_SPINLOCK_DESTROY(phc->lock);\n+}\n+\n+int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp)\n+{\n+\tvolatile struct ena_admin_phc_resp *read_resp = ena_dev->phc.virt_addr;\n+\tstruct ena_com_phc_info *phc = &ena_dev->phc;\n+\tena_time_high_res_t initial_time = ENA_TIME_INIT_HIGH_RES();\n+\tstatic ena_time_high_res_t start_time;\n+\tunsigned long flags = 0;\n+\tena_time_high_res_t expire_time;\n+\tena_time_high_res_t block_time;\n+\tint ret = ENA_COM_OK;\n+\n+\tif (!phc->active) {\n+\t\tena_trc_err(ena_dev, \"PHC feature is not active in the device\\n\");\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n+\n+\tENA_SPINLOCK_LOCK(phc->lock, flags);\n+\n+\t/* Check if PHC is in blocked state */\n+\tif (unlikely(ENA_TIME_COMPARE_HIGH_RES(start_time, initial_time))) {\n+\t\t/* Check if blocking time expired */\n+\t\tblock_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->block_timeout_usec);\n+\t\tif (!ENA_TIME_EXPIRE_HIGH_RES(block_time)) {\n+\t\t\t/* PHC is still in blocked state, skip PHC request */\n+\t\t\tphc->stats.phc_skp++;\n+\t\t\tret = ENA_COM_DEVICE_BUSY;\n+\t\t\tgoto skip;\n+\t\t}\n+\n+\t\t/* PHC is in active state, update statistics according to req_id and timestamp */\n+\t\tif ((READ_ONCE16(read_resp->req_id) != phc->req_id) ||\n+\t\t\t\tread_resp->timestamp == ENA_PHC_TIMESTAMP_ERROR)\n+\t\t\t/* Device didn't update req_id during blocking time or timestamp is invalid,\n+\t\t\t * this indicates on a device error\n+\t\t\t */\n+\t\t\tphc->stats.phc_err++;\n+\t\telse\n+\t\t\t/* Device updated req_id during blocking time with valid timestamp */\n+\t\t\tphc->stats.phc_exp++;\n+\t}\n+\n+\t/* Setting relative timeouts */\n+\tstart_time = ENA_GET_SYSTEM_TIME_HIGH_RES();\n+\tblock_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->block_timeout_usec);\n+\texpire_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->expire_timeout_usec);\n+\n+\t/* We expect the device to return this req_id once the new PHC timestamp is updated */\n+\tphc->req_id++;\n+\n+\t/* Initialize PHC shared memory with different req_id value to be able to identify once the\n+\t * device changes it to req_id\n+\t */\n+\tread_resp->req_id = phc->req_id + ENA_PHC_REQ_ID_OFFSET;\n+\n+\t/* Writing req_id to PHC bar */\n+\tENA_REG_WRITE32(ena_dev->bus, phc->req_id, ena_dev->reg_bar + phc->doorbell_offset);\n+\n+\t/* Stalling until the device updates req_id */\n+\twhile (1) {\n+\t\tif (unlikely(ENA_TIME_EXPIRE_HIGH_RES(expire_time))) {\n+\t\t\t/* Gave up waiting for updated req_id, PHC enters into blocked state until\n+\t\t\t * passing blocking time\n+\t\t\t */\n+\t\t\tret = ENA_COM_DEVICE_BUSY;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Check if req_id was updated by the device */\n+\t\tif (READ_ONCE16(read_resp->req_id) != phc->req_id) {\n+\t\t\t/* req_id was not updated by the device, check again on next loop */\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* req_id was updated which indicates that PHC timestamp was updated too */\n+\t\t*timestamp = read_resp->timestamp;\n+\n+\t\t/* PHC timestamp validty check */\n+\t\tif (unlikely(*timestamp == ENA_PHC_TIMESTAMP_ERROR)) {\n+\t\t\t/* Retrieved invalid PHC timestamp, PHC enters into blocked state until\n+\t\t\t * passing blocking time\n+\t\t\t */\n+\t\t\tret = ENA_COM_DEVICE_BUSY;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Retrieved valid PHC timestamp */\n+\t\tphc->stats.phc_cnt++;\n+\n+\t\t/* This indicates PHC state is active */\n+\t\tstart_time = initial_time;\n+\t\tbreak;\n+\t}\n+\n+skip:\n+\tENA_SPINLOCK_UNLOCK(phc->lock, flags);\n+\n+\treturn ret;\n+}\n+\n int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;\n@@ -1974,6 +2187,55 @@ int ena_com_get_link_params(struct ena_com_dev *ena_dev,\n \treturn ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);\n }\n \n+static int ena_get_dev_stats(struct ena_com_dev *ena_dev,\n+\t\t\t struct ena_com_stats_ctx *ctx,\n+\t\t\t enum ena_admin_get_stats_type type)\n+{\n+\tstruct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;\n+\tstruct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;\n+\tstruct ena_com_admin_queue *admin_queue;\n+\tint ret;\n+\n+\tadmin_queue = &ena_dev->admin_queue;\n+\n+\tget_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;\n+\tget_cmd->aq_common_descriptor.flags = 0;\n+\tget_cmd->type = type;\n+\n+\tret = ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t (struct ena_admin_aq_entry *)get_cmd,\n+\t\t\t\t\t sizeof(*get_cmd),\n+\t\t\t\t\t (struct ena_admin_acq_entry *)get_resp,\n+\t\t\t\t\t sizeof(*get_resp));\n+\n+\tif (unlikely(ret))\n+\t\tena_trc_err(ena_dev, \"Failed to get stats. error: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static void ena_com_set_supported_customer_metrics(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_customer_metrics *customer_metrics;\n+\tstruct ena_com_stats_ctx ctx;\n+\tint ret;\n+\n+\tcustomer_metrics = &ena_dev->customer_metrics;\n+\tif (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {\n+\t\tcustomer_metrics->supported_metrics = ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK;\n+\t\treturn;\n+\t}\n+\n+\tmemset(&ctx, 0x0, sizeof(ctx));\n+\tctx.get_cmd.requested_metrics = ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK;\n+\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);\n+\tif (likely(ret == 0))\n+\t\tcustomer_metrics->supported_metrics =\n+\t\t\tctx.get_resp.u.customer_metrics.reported_metrics;\n+\telse\n+\t\tena_trc_err(ena_dev, \"Failed to query customer metrics support. error: %d\\n\", ret);\n+}\n+\n int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \t\t\t struct ena_com_dev_get_features_ctx *get_feat_ctx)\n {\n@@ -1989,6 +2251,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \t sizeof(get_resp.u.dev_attr));\n \n \tena_dev->supported_features = get_resp.u.dev_attr.supported_features;\n+\tena_dev->capabilities = get_resp.u.dev_attr.capabilities;\n \n \tif (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {\n \t\trc = ena_com_get_feature(ena_dev, &get_resp,\n@@ -1998,7 +2261,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \t\t\treturn rc;\n \n \t\tif (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)\n-\t\t\treturn -EINVAL;\n+\t\t\treturn ENA_COM_INVAL;\n \n \t\tmemcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,\n \t\t sizeof(get_resp.u.max_queue_ext));\n@@ -2045,7 +2308,8 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \telse\n \t\treturn rc;\n \n-\trc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);\n+\trc = ena_com_get_feature(ena_dev, &get_resp,\n+\t\t\t\t ENA_ADMIN_LLQ, ENA_ADMIN_LLQ_FEATURE_VERSION_1);\n \tif (!rc)\n \t\tmemcpy(&get_feat_ctx->llq, &get_resp.u.llq,\n \t\t sizeof(get_resp.u.llq));\n@@ -2054,6 +2318,8 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \telse\n \t\treturn rc;\n \n+\tena_com_set_supported_customer_metrics(ena_dev);\n+\n \treturn 0;\n }\n \n@@ -2105,8 +2371,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)\n \n \t\ttimestamp = (u64)aenq_common->timestamp_low |\n \t\t\t((u64)aenq_common->timestamp_high << 32);\n-\t\tENA_TOUCH(timestamp); /* In case debug is disabled */\n-\t\tena_trc_dbg(ena_dev, \"AENQ! Group[%x] Syndrome[%x] timestamp: [%\" ENA_PRIu64 \"s]\\n\",\n+\n+\t\tena_trc_dbg(ena_dev, \"AENQ! Group[%x] Syndrome[%x] timestamp: [%\" ENA_PRIU64 \"s]\\n\",\n \t\t\t aenq_common->group,\n \t\t\t aenq_common->syndrome,\n \t\t\t timestamp);\n@@ -2145,6 +2411,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)\n int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n \t\t enum ena_regs_reset_reason_types reset_reason)\n {\n+\tu32 reset_reason_msb, reset_reason_lsb;\n \tu32 stat, timeout, cap, reset_val;\n \tint rc;\n \n@@ -2171,8 +2438,28 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n \n \t/* start reset */\n \treset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;\n-\treset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &\n-\t\t\tENA_REGS_DEV_CTL_RESET_REASON_MASK;\n+\n+\t/* For backward compatibility, device will interpret\n+\t * bits 24-27 as MSB, bits 28-31 as LSB\n+\t */\n+\treset_reason_lsb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_LSB_MASK,\n+\t\t\t\t\t ENA_RESET_REASON_LSB_OFFSET);\n+\n+\treset_reason_msb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_MSB_MASK,\n+\t\t\t\t\t ENA_RESET_REASON_MSB_OFFSET);\n+\n+\treset_val |= reset_reason_lsb << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT;\n+\n+\tif (ena_com_get_cap(ena_dev, ENA_ADMIN_EXTENDED_RESET_REASONS)) {\n+\t\treset_val |= reset_reason_msb << ENA_REGS_DEV_CTL_RESET_REASON_EXT_SHIFT;\n+\t} else if (reset_reason_msb) {\n+\t\t/* In case the device does not support intended\n+\t\t * extended reset reason fallback to generic\n+\t\t */\n+\t\treset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;\n+\t\treset_val |= (ENA_REGS_RESET_GENERIC << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &\n+\t\t\t ENA_REGS_DEV_CTL_RESET_REASON_MASK;\n+\t}\n \tENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);\n \n \t/* Write again the MMIO read request address */\n@@ -2204,44 +2491,42 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n \treturn 0;\n }\n \n-static int ena_get_dev_stats(struct ena_com_dev *ena_dev,\n-\t\t\t struct ena_com_stats_ctx *ctx,\n-\t\t\t enum ena_admin_get_stats_type type)\n+int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,\n+\t\t\t struct ena_admin_eni_stats *stats)\n {\n-\tstruct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;\n-\tstruct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;\n-\tstruct ena_com_admin_queue *admin_queue;\n+\tstruct ena_com_stats_ctx ctx;\n \tint ret;\n \n-\tadmin_queue = &ena_dev->admin_queue;\n-\n-\tget_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;\n-\tget_cmd->aq_common_descriptor.flags = 0;\n-\tget_cmd->type = type;\n-\n-\tret = ena_com_execute_admin_command(admin_queue,\n-\t\t\t\t\t (struct ena_admin_aq_entry *)get_cmd,\n-\t\t\t\t\t sizeof(*get_cmd),\n-\t\t\t\t\t (struct ena_admin_acq_entry *)get_resp,\n-\t\t\t\t\t sizeof(*get_resp));\n+\tif (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) {\n+\t\tena_trc_err(ena_dev, \"Capability %d isn't supported\\n\", ENA_ADMIN_ENI_STATS);\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n \n-\tif (unlikely(ret))\n-\t\tena_trc_err(ena_dev, \"Failed to get stats. error: %d\\n\", ret);\n+\tmemset(&ctx, 0x0, sizeof(ctx));\n+\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);\n+\tif (likely(ret == 0))\n+\t\tmemcpy(stats, &ctx.get_resp.u.eni_stats,\n+\t\t sizeof(ctx.get_resp.u.eni_stats));\n \n \treturn ret;\n }\n \n-int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,\n-\t\t\t struct ena_admin_eni_stats *stats)\n+int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev,\n+\t\t\t struct ena_admin_ena_srd_info *info)\n {\n \tstruct ena_com_stats_ctx ctx;\n \tint ret;\n \n+\tif (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENA_SRD_INFO)) {\n+\t\tena_trc_err(ena_dev, \"Capability %d isn't supported\\n\", ENA_ADMIN_ENA_SRD_INFO);\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n+\n \tmemset(&ctx, 0x0, sizeof(ctx));\n-\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);\n+\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENA_SRD);\n \tif (likely(ret == 0))\n-\t\tmemcpy(stats, &ctx.get_resp.u.eni_stats,\n-\t\t sizeof(ctx.get_resp.u.eni_stats));\n+\t\tmemcpy(info, &ctx.get_resp.u.ena_srd_info,\n+\t\t sizeof(ctx.get_resp.u.ena_srd_info));\n \n \treturn ret;\n }\n@@ -2261,7 +2546,49 @@ int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,\n \treturn ret;\n }\n \n-int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)\n+int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len)\n+{\n+\tstruct ena_admin_aq_get_stats_cmd *get_cmd;\n+\tstruct ena_com_stats_ctx ctx;\n+\tint ret;\n+\n+\tif (unlikely(len > ena_dev->customer_metrics.buffer_len)) {\n+\t\tena_trc_err(ena_dev, \"Invalid buffer size %u. The given buffer is too big.\\n\", len);\n+\t\treturn ENA_COM_INVAL;\n+\t}\n+\n+\tif (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {\n+\t\tena_trc_err(ena_dev, \"Capability %d not supported.\\n\", ENA_ADMIN_CUSTOMER_METRICS);\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n+\n+\tif (!ena_dev->customer_metrics.supported_metrics) {\n+\t\tena_trc_err(ena_dev, \"No supported customer metrics.\\n\");\n+\t\treturn ENA_COM_UNSUPPORTED;\n+\t}\n+\n+\tget_cmd = &ctx.get_cmd;\n+\tmemset(&ctx, 0x0, sizeof(ctx));\n+\tret = ena_com_mem_addr_set(ena_dev,\n+\t\t&get_cmd->u.control_buffer.address,\n+\t\tena_dev->customer_metrics.buffer_dma_addr);\n+\tif (unlikely(ret)) {\n+\t\tena_trc_err(ena_dev, \"Memory address set failed.\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tget_cmd->u.control_buffer.length = ena_dev->customer_metrics.buffer_len;\n+\tget_cmd->requested_metrics = ena_dev->customer_metrics.supported_metrics;\n+\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);\n+\tif (likely(ret == 0))\n+\t\tmemcpy(buffer, ena_dev->customer_metrics.buffer_virt_addr, len);\n+\telse\n+\t\tena_trc_err(ena_dev, \"Failed to get customer metrics. error: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu)\n {\n \tstruct ena_com_admin_queue *admin_queue;\n \tstruct ena_admin_set_feat_cmd cmd;\n@@ -2279,7 +2606,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)\n \tcmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;\n \tcmd.aq_common_descriptor.flags = 0;\n \tcmd.feat_common.feature_id = ENA_ADMIN_MTU;\n-\tcmd.u.mtu.mtu = (u32)mtu;\n+\tcmd.u.mtu.mtu = mtu;\n \n \tret = ena_com_execute_admin_command(admin_queue,\n \t\t\t\t\t (struct ena_admin_aq_entry *)&cmd,\n@@ -2400,27 +2727,17 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,\n \t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n-\tswitch (func) {\n-\tcase ENA_ADMIN_TOEPLITZ:\n-\t\tif (key) {\n-\t\t\tif (key_len != sizeof(hash_key->key)) {\n-\t\t\t\tena_trc_err(ena_dev, \"key len (%hu) doesn't equal the supported size (%zu)\\n\",\n-\t\t\t\t\t key_len, sizeof(hash_key->key));\n-\t\t\t\treturn ENA_COM_INVAL;\n-\t\t\t}\n-\t\t\tmemcpy(hash_key->key, key, key_len);\n-\t\t\trss->hash_init_val = init_val;\n-\t\t\thash_key->key_parts = key_len / sizeof(hash_key->key[0]);\n+\tif (func == ENA_ADMIN_TOEPLITZ && key) {\n+\t\tif (key_len != sizeof(hash_key->key)) {\n+\t\t\tena_trc_err(ena_dev, \"key len (%u) doesn't equal the supported size (%zu)\\n\",\n+\t\t\t\t key_len, sizeof(hash_key->key));\n+\t\t\treturn ENA_COM_INVAL;\n \t\t}\n-\t\tbreak;\n-\tcase ENA_ADMIN_CRC32:\n-\t\trss->hash_init_val = init_val;\n-\t\tbreak;\n-\tdefault:\n-\t\tena_trc_err(ena_dev, \"Invalid hash function (%d)\\n\", func);\n-\t\treturn ENA_COM_INVAL;\n+\t\tmemcpy(hash_key->key, key, key_len);\n+\t\thash_key->key_parts = key_len / sizeof(hash_key->key[0]);\n \t}\n \n+\trss->hash_init_val = init_val;\n \told_func = rss->hash_func;\n \trss->hash_func = func;\n \trc = ena_com_set_hash_function(ena_dev);\n@@ -2690,7 +3007,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)\n \t\treturn ret;\n \t}\n \n-\tcmd.control_buffer.length = (u32)(1ULL << rss->tbl_log_size) *\n+\tcmd.control_buffer.length = (1ULL << rss->tbl_log_size) *\n \t\tsizeof(struct ena_admin_rss_ind_table_entry);\n \n \tret = ena_com_execute_admin_command(admin_queue,\n@@ -2712,7 +3029,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)\n \tu32 tbl_size;\n \tint i, rc;\n \n-\ttbl_size = (u32)(1ULL << rss->tbl_log_size) *\n+\ttbl_size = (1ULL << rss->tbl_log_size) *\n \t\tsizeof(struct ena_admin_rss_ind_table_entry);\n \n \trc = ena_com_get_feature_ex(ena_dev, &get_resp,\n@@ -2814,6 +3131,23 @@ int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,\n \treturn 0;\n }\n \n+int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;\n+\n+\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n+\t\t\t customer_metrics->buffer_len,\n+\t\t\t customer_metrics->buffer_virt_addr,\n+\t\t\t customer_metrics->buffer_dma_addr,\n+\t\t\t customer_metrics->buffer_dma_handle);\n+\tif (unlikely(customer_metrics->buffer_virt_addr == NULL))\n+\t\treturn ENA_COM_NO_MEM;\n+\n+\tcustomer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE;\n+\n+\treturn 0;\n+}\n+\n void ena_com_delete_host_info(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_host_attribute *host_attr = &ena_dev->host_attr;\n@@ -2842,6 +3176,21 @@ void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)\n \t}\n }\n \n+void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev)\n+{\n+\tstruct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;\n+\n+\tif (customer_metrics->buffer_virt_addr) {\n+\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n+\t\t\t\t customer_metrics->buffer_len,\n+\t\t\t\t customer_metrics->buffer_virt_addr,\n+\t\t\t\t customer_metrics->buffer_dma_addr,\n+\t\t\t\t customer_metrics->buffer_dma_handle);\n+\t\tcustomer_metrics->buffer_virt_addr = NULL;\n+\t\tcustomer_metrics->buffer_len = 0;\n+\t}\n+}\n+\n int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_host_attribute *host_attr = &ena_dev->host_attr;\n@@ -2996,7 +3345,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,\n \n \tif (unlikely(ena_dev->tx_max_header_size == 0)) {\n \t\tena_trc_err(ena_dev, \"The size of the LLQ entry is smaller than needed\\n\");\n-\t\treturn -EINVAL;\n+\t\treturn ENA_COM_INVAL;\n \t}\n \n \tena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;\ndiff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h\nindex ca84e2e8bc..cd054595d7 100644\n--- a/drivers/net/ena/base/ena_com.h\n+++ b/drivers/net/ena/base/ena_com.h\n@@ -23,19 +23,27 @@\n #define ADMIN_CQ_SIZE(depth)\t((depth) * sizeof(struct ena_admin_acq_entry))\n #define ADMIN_AENQ_SIZE(depth)\t((depth) * sizeof(struct ena_admin_aenq_entry))\n \n-#define ENA_CDESC_RING_SIZE_ALIGNMENT\t(1 << 12) /* 4K */\n+/* Macros used to extract LSB/MSB from the\n+ * enums defining the reset reasons\n+ */\n+#define ENA_RESET_REASON_LSB_OFFSET\t\t\t 0\n+#define ENA_RESET_REASON_LSB_MASK\t\t\t 0xf\n+#define ENA_RESET_REASON_MSB_OFFSET\t\t\t 4\n+#define ENA_RESET_REASON_MSB_MASK\t\t\t 0xf0\n+\n+#define ENA_CUSTOMER_METRICS_BUFFER_SIZE 512\n \n /*****************************************************************************/\n /*****************************************************************************/\n /* ENA adaptive interrupt moderation settings */\n \n #define ENA_INTR_INITIAL_TX_INTERVAL_USECS ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT\n-#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0\n+#define ENA_INTR_INITIAL_RX_INTERVAL_USECS ENA_INTR_INITIAL_RX_INTERVAL_USECS_PLAT\n #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1\n \n #define ENA_HASH_KEY_SIZE 40\n \n-#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF\n+#define ENA_HW_HINTS_NO_TIMEOUT\t0xFFFF\n \n #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1\n \n@@ -94,8 +102,6 @@ struct ena_com_io_cq {\n \t/* Interrupt unmask register */\n \tu32 __iomem *unmask_reg;\n \n-\t/* The completion queue head doorbell register */\n-\tu32 __iomem *cq_head_db_reg;\n \n \t/* numa configuration register (for TPH) */\n \tu32 __iomem *numa_node_cfg_reg;\n@@ -103,13 +109,13 @@ struct ena_com_io_cq {\n \t/* The value to write to the above register to unmask\n \t * the interrupt of this queue\n \t */\n-\tu32 msix_vector;\n+\tu32 msix_vector ____cacheline_aligned;\n \n \tenum queue_direction direction;\n \n \t/* holds the number of cdesc of the current packet */\n \tu16 cur_rx_pkt_cdesc_count;\n-\t/* save the firt cdesc idx of the current packet */\n+\t/* save the first cdesc idx of the current packet */\n \tu16 cur_rx_pkt_cdesc_start_idx;\n \n \tu16 q_depth;\n@@ -119,7 +125,6 @@ struct ena_com_io_cq {\n \t/* Device queue index */\n \tu16 idx;\n \tu16 head;\n-\tu16 last_head_update;\n \tu8 phase;\n \tu8 cdesc_entry_size_in_bytes;\n \n@@ -144,7 +149,6 @@ struct ena_com_io_sq {\n \tvoid *bus;\n \n \tu32 __iomem *db_addr;\n-\tu8 __iomem *header_addr;\n \n \tenum queue_direction direction;\n \tenum ena_admin_placement_policy_type mem_queue_type;\n@@ -201,6 +205,13 @@ struct ena_com_stats_admin {\n \tu64 no_completion;\n };\n \n+struct ena_com_stats_phc {\n+\tu64 phc_cnt;\n+\tu64 phc_exp;\n+\tu64 phc_skp;\n+\tu64 phc_err;\n+};\n+\n struct ena_com_admin_queue {\n \tvoid *q_dmadev;\n \tvoid *bus;\n@@ -255,6 +266,46 @@ struct ena_com_mmio_read {\n \tena_spinlock_t lock;\n };\n \n+/* PTP hardware clock (PHC) MMIO read data info */\n+struct ena_com_phc_info {\n+\t/* Internal PHC statistics */\n+\tstruct ena_com_stats_phc stats;\n+\n+\t/* PHC shared memory - virtual address */\n+\tstruct ena_admin_phc_resp *virt_addr;\n+\n+\t/* Spin lock to ensure a single outstanding PHC read */\n+\tena_spinlock_t lock;\n+\n+\t/* PHC doorbell address as an offset to PCIe MMIO REG BAR */\n+\tu32 doorbell_offset;\n+\n+\t/* Shared memory read expire timeout (usec)\n+\t * Max time for valid PHC retrieval, passing this threshold will fail the get time request\n+\t * and block new PHC requests for block_timeout_usec in order to prevent floods on busy\n+\t * device\n+\t */\n+\tu32 expire_timeout_usec;\n+\n+\t/* Shared memory read abort timeout (usec)\n+\t * PHC requests block period, blocking starts once PHC request expired in order to prevent\n+\t * floods on busy device, any PHC requests during block period will be skipped\n+\t */\n+\tu32 block_timeout_usec;\n+\n+\t/* Request id sent to the device */\n+\tu16 req_id;\n+\n+\t/* True if PHC is active in the device */\n+\tbool active;\n+\n+\t/* PHC shared memory - memory handle */\n+\tena_mem_handle_t mem_handle;\n+\n+\t/* PHC shared memory - physical address */\n+\tdma_addr_t phys_addr;\n+};\n+\n struct ena_rss {\n \t/* Indirect table */\n \tu16 *host_rss_ind_tbl;\n@@ -277,6 +328,17 @@ struct ena_rss {\n \n };\n \n+struct ena_customer_metrics {\n+\t/* in correlation with ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK\n+\t * and ena_admin_customer_metrics_id\n+\t */\n+\tuint64_t supported_metrics;\n+\tdma_addr_t buffer_dma_addr;\n+\tvoid *buffer_virt_addr;\n+\tena_mem_handle_t buffer_dma_handle;\n+\tu32 buffer_len;\n+};\n+\n struct ena_host_attribute {\n \t/* Debug area */\n \tu8 *debug_area_virt_addr;\n@@ -307,10 +369,14 @@ struct ena_com_dev {\n \tu16 stats_func; /* Selected function for extended statistic dump */\n \tu16 stats_queue; /* Selected queue for extended statistic dump */\n \n+\tu32 ena_min_poll_delay_us;\n+\n \tstruct ena_com_mmio_read mmio_read;\n+\tstruct ena_com_phc_info phc;\n \n \tstruct ena_rss rss;\n \tu32 supported_features;\n+\tu32 capabilities;\n \tu32 dma_addr_bits;\n \n \tstruct ena_host_attribute host_attr;\n@@ -327,7 +393,7 @@ struct ena_com_dev {\n \n \tstruct ena_com_llq_info llq_info;\n \n-\tu32 ena_min_poll_delay_us;\n+\tstruct ena_customer_metrics customer_metrics;\n };\n \n struct ena_com_dev_get_features_ctx {\n@@ -375,6 +441,40 @@ extern \"C\" {\n */\n int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);\n \n+/* ena_com_phc_init - Allocate and initialize PHC feature\n+ * @ena_dev: ENA communication layer struct\n+ * @note: This method assumes PHC is supported by the device\n+ * @return - 0 on success, negative value on failure\n+ */\n+int ena_com_phc_init(struct ena_com_dev *ena_dev);\n+\n+/* ena_com_phc_supported - Return if PHC feature is supported by the device\n+ * @ena_dev: ENA communication layer struct\n+ * @note: This method must be called after getting supported features\n+ * @return - supported or not\n+ */\n+bool ena_com_phc_supported(struct ena_com_dev *ena_dev);\n+\n+/* ena_com_phc_config - Configure PHC feature\n+ * @ena_dev: ENA communication layer struct\n+ * Configure PHC feature in driver and device\n+ * @note: This method assumes PHC is supported by the device\n+ * @return - 0 on success, negative value on failure\n+ */\n+int ena_com_phc_config(struct ena_com_dev *ena_dev);\n+\n+/* ena_com_phc_destroy - Destroy PHC feature\n+ * @ena_dev: ENA communication layer struct\n+ */\n+void ena_com_phc_destroy(struct ena_com_dev *ena_dev);\n+\n+/* ena_com_phc_get - Retrieve PHC timestamp\n+ * @ena_dev: ENA communication layer struct\n+ * @timestamp: Retrieve PHC timestamp\n+ * @return - 0 on success, negative value on failure\n+ */\n+int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp);\n+\n /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism\n * @ena_dev: ENA communication layer struct\n * @readless_supported: readless mode (enable/disable)\n@@ -611,13 +711,31 @@ int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,\n int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,\n \t\t\t struct ena_admin_eni_stats *stats);\n \n+/* ena_com_get_ena_srd_info - Get ENA SRD network interface statistics\n+ * @ena_dev: ENA communication layer struct\n+ * @info: ena srd stats and flags\n+ *\n+ * @return: 0 on Success and negative value otherwise.\n+ */\n+int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev,\n+\t\t\t struct ena_admin_ena_srd_info *info);\n+\n+/* ena_com_get_customer_metrics - Get customer metrics for network interface\n+ * @ena_dev: ENA communication layer struct\n+ * @buffer: buffer for returned customer metrics\n+ * @len: size of the buffer\n+ *\n+ * @return: 0 on Success and negative value otherwise.\n+ */\n+int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len);\n+\n /* ena_com_set_dev_mtu - Configure the device mtu.\n * @ena_dev: ENA communication layer struct\n * @mtu: mtu value\n *\n * @return: 0 on Success and negative value otherwise.\n */\n-int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);\n+int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu);\n \n /* ena_com_get_offload_settings - Retrieve the device offloads capabilities\n * @ena_dev: ENA communication layer struct\n@@ -821,6 +939,13 @@ int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);\n int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,\n \t\t\t\tu32 debug_area_size);\n \n+/* ena_com_allocate_customer_metrics_buffer - Allocate customer metrics resources.\n+ * @ena_dev: ENA communication layer struct\n+ *\n+ * @return: 0 on Success and negative value otherwise.\n+ */\n+int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev);\n+\n /* ena_com_delete_debug_area - Free the debug area resources.\n * @ena_dev: ENA communication layer struct\n *\n@@ -835,6 +960,13 @@ void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);\n */\n void ena_com_delete_host_info(struct ena_com_dev *ena_dev);\n \n+/* ena_com_delete_customer_metrics_buffer - Free the customer metrics resources.\n+ * @ena_dev: ENA communication layer struct\n+ *\n+ * Free the allocated customer metrics area.\n+ */\n+void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev);\n+\n /* ena_com_set_host_attributes - Update the device with the host\n * attributes (debug area and host info) base address.\n * @ena_dev: ENA communication layer struct\n@@ -979,18 +1111,55 @@ static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_d\n \tena_dev->adaptive_coalescing = false;\n }\n \n+/* ena_com_get_cap - query whether device supports a capability.\n+ * @ena_dev: ENA communication layer struct\n+ * @cap_id: enum value representing the capability\n+ *\n+ * @return - true if capability is supported or false otherwise\n+ */\n+static inline bool ena_com_get_cap(struct ena_com_dev *ena_dev,\n+\t\t\t\t enum ena_admin_aq_caps_id cap_id)\n+{\n+\treturn !!(ena_dev->capabilities & BIT(cap_id));\n+}\n+\n+/* ena_com_get_customer_metric_support - query whether device supports a given customer metric.\n+ * @ena_dev: ENA communication layer struct\n+ * @metric_id: enum value representing the customer metric\n+ *\n+ * @return - true if customer metric is supported or false otherwise\n+ */\n+static inline bool ena_com_get_customer_metric_support(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t enum ena_admin_customer_metrics_id metric_id)\n+{\n+\treturn !!(ena_dev->customer_metrics.supported_metrics & BIT64(metric_id));\n+}\n+\n+/* ena_com_get_customer_metric_count - return the number of supported customer metrics.\n+ * @ena_dev: ENA communication layer struct\n+ *\n+ * @return - the number of supported customer metrics\n+ */\n+static inline int ena_com_get_customer_metric_count(struct ena_com_dev *ena_dev)\n+{\n+\treturn ENA_BITS_PER_U64(ena_dev->customer_metrics.supported_metrics);\n+}\n+\n /* ena_com_update_intr_reg - Prepare interrupt register\n * @intr_reg: interrupt register to update.\n * @rx_delay_interval: Rx interval in usecs\n * @tx_delay_interval: Tx interval in usecs\n * @unmask: unmask enable/disable\n+ * @no_moderation_update: 0 - Indicates that any of the TX/RX intervals was\n+ * updated, 1 - otherwise\n *\n * Prepare interrupt update register with the supplied parameters.\n */\n static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,\n \t\t\t\t\t u32 rx_delay_interval,\n \t\t\t\t\t u32 tx_delay_interval,\n-\t\t\t\t\t bool unmask)\n+\t\t\t\t\t bool unmask,\n+\t\t\t\t\t bool no_moderation_update)\n {\n \tintr_reg->intr_control = 0;\n \tintr_reg->intr_control |= rx_delay_interval &\n@@ -1002,6 +1171,10 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,\n \n \tif (unmask)\n \t\tintr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;\n+\n+\tintr_reg->intr_control |=\n+\t\t(((u32)no_moderation_update) << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) &\n+\t\t\tENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK;\n }\n \n static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)\ndiff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h\nindex 56768e1a1b..fa43e22918 100644\n--- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h\n@@ -5,8 +5,26 @@\n #ifndef _ENA_ADMIN_H_\n #define _ENA_ADMIN_H_\n \n+#define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32\n+#define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32\n+\n #define ENA_ADMIN_RSS_KEY_PARTS 10\n \n+#define ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 0x3F\n+#define ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK 0x1F\n+\n+ /* customer metrics - in correlation with\n+ * ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK\n+ */\n+enum ena_admin_customer_metrics_id {\n+\tENA_ADMIN_BW_IN_ALLOWANCE_EXCEEDED = 0,\n+\tENA_ADMIN_BW_OUT_ALLOWANCE_EXCEEDED = 1,\n+\tENA_ADMIN_PPS_ALLOWANCE_EXCEEDED = 2,\n+\tENA_ADMIN_CONNTRACK_ALLOWANCE_EXCEEDED = 3,\n+\tENA_ADMIN_LINKLOCAL_ALLOWANCE_EXCEEDED = 4,\n+\tENA_ADMIN_CONNTRACK_ALLOWANCE_AVAILABLE = 5,\n+};\n+\n enum ena_admin_aq_opcode {\n \tENA_ADMIN_CREATE_SQ = 1,\n \tENA_ADMIN_DESTROY_SQ = 2,\n@@ -47,9 +65,27 @@ enum ena_admin_aq_feature_id {\n \tENA_ADMIN_AENQ_CONFIG = 26,\n \tENA_ADMIN_LINK_CONFIG = 27,\n \tENA_ADMIN_HOST_ATTR_CONFIG = 28,\n+\tENA_ADMIN_PHC_CONFIG = 29,\n \tENA_ADMIN_FEATURES_OPCODE_NUM = 32,\n };\n \n+/* feature version for the set/get ENA_ADMIN_LLQ feature admin commands */\n+enum ena_admin_llq_feature_version {\n+\t/* legacy base version in older drivers */\n+\tENA_ADMIN_LLQ_FEATURE_VERSION_0_LEGACY = 0,\n+\t/* support entry_size recommendation by device */\n+\tENA_ADMIN_LLQ_FEATURE_VERSION_1 = 1,\n+};\n+\n+/* device capabilities */\n+enum ena_admin_aq_caps_id {\n+\tENA_ADMIN_ENI_STATS = 0,\n+\t/* ENA SRD customer metrics */\n+\tENA_ADMIN_ENA_SRD_INFO = 1,\n+\tENA_ADMIN_CUSTOMER_METRICS = 2,\n+\tENA_ADMIN_EXTENDED_RESET_REASONS\t = 3,\n+};\n+\n enum ena_admin_placement_policy_type {\n \t/* descriptors and headers are in host memory */\n \tENA_ADMIN_PLACEMENT_POLICY_HOST = 1,\n@@ -96,6 +132,10 @@ enum ena_admin_get_stats_type {\n \tENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,\n \t/* extra HW stats for specific network interface */\n \tENA_ADMIN_GET_STATS_TYPE_ENI = 2,\n+\t/* extra HW stats for ENA SRD */\n+\tENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3,\n+\tENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS = 4,\n+\n };\n \n enum ena_admin_get_stats_scope {\n@@ -103,6 +143,20 @@ enum ena_admin_get_stats_scope {\n \tENA_ADMIN_ETH_TRAFFIC = 1,\n };\n \n+enum ena_admin_get_phc_type {\n+\tENA_ADMIN_PHC_TYPE_READLESS = 0,\n+};\n+\n+/* ENA SRD configuration for ENI */\n+enum ena_admin_ena_srd_flags {\n+\t/* Feature enabled */\n+\tENA_ADMIN_ENA_SRD_ENABLED = BIT(0),\n+\t/* UDP support enabled */\n+\tENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1),\n+\t/* Bypass Rx UDP ordering */\n+\tENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2),\n+};\n+\n struct ena_admin_aq_common_desc {\n \t/* 11:0 : command_id\n \t * 15:12 : reserved12\n@@ -360,6 +414,9 @@ struct ena_admin_aq_get_stats_cmd {\n \t * stats of other device\n \t */\n \tuint16_t device_id;\n+\n+\t/* a bitmap representing the requested metric values */\n+\tuint64_t requested_metrics;\n };\n \n /* Basic Statistics Command. */\n@@ -387,6 +444,10 @@ struct ena_admin_basic_stats {\n \tuint32_t tx_drops_low;\n \n \tuint32_t tx_drops_high;\n+\n+\tuint32_t rx_overruns_low;\n+\n+\tuint32_t rx_overruns_high;\n };\n \n /* ENI Statistics Command. */\n@@ -416,6 +477,40 @@ struct ena_admin_eni_stats {\n \tuint64_t linklocal_allowance_exceeded;\n };\n \n+struct ena_admin_ena_srd_stats {\n+\t/* Number of packets transmitted over ENA SRD */\n+\tuint64_t ena_srd_tx_pkts;\n+\n+\t/* Number of packets transmitted or could have been\n+\t * transmitted over ENA SRD\n+\t */\n+\tuint64_t ena_srd_eligible_tx_pkts;\n+\n+\t/* Number of packets received over ENA SRD */\n+\tuint64_t ena_srd_rx_pkts;\n+\n+\t/* Percentage of the ENA SRD resources that is in use */\n+\tuint64_t ena_srd_resource_utilization;\n+};\n+\n+/* ENA SRD Statistics Command */\n+struct ena_admin_ena_srd_info {\n+\t/* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for\n+\t * details\n+\t */\n+\tuint64_t flags;\n+\n+\tstruct ena_admin_ena_srd_stats ena_srd_stats;\n+};\n+\n+/* Customer Metrics Command. */\n+struct ena_admin_customer_metrics {\n+\t/* A bitmap representing the reported customer metrics according to\n+\t * the order they are reported\n+\t */\n+\tuint64_t reported_metrics;\n+};\n+\n struct ena_admin_acq_get_stats_resp {\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n@@ -425,6 +520,10 @@ struct ena_admin_acq_get_stats_resp {\n \t\tstruct ena_admin_basic_stats basic_stats;\n \n \t\tstruct ena_admin_eni_stats eni_stats;\n+\n+\t\tstruct ena_admin_ena_srd_info ena_srd_info;\n+\n+\t\tstruct ena_admin_customer_metrics customer_metrics;\n \t} u;\n };\n \n@@ -457,7 +556,10 @@ struct ena_admin_device_attr_feature_desc {\n \t */\n \tuint32_t supported_features;\n \n-\tuint32_t reserved3;\n+\t/* bitmap of ena_admin_aq_caps_id, which represents device\n+\t * capabilities.\n+\t */\n+\tuint32_t capabilities;\n \n \t/* Indicates how many bits are used physical address access. */\n \tuint32_t phys_addr_width;\n@@ -578,8 +680,17 @@ struct ena_admin_feature_llq_desc {\n \t/* the stride control the driver selected to use */\n \tuint16_t descriptors_stride_ctrl_enabled;\n \n+\t/* feature version of device resp to either GET/SET commands. */\n+\tuint8_t feature_version;\n+\n+\t/* llq entry size recommended by the device,\n+\t * values correlated to enum ena_admin_llq_ring_entry_size.\n+\t * used only for GET command.\n+\t */\n+\tuint8_t entry_size_recommended;\n+\n \t/* reserved */\n-\tuint32_t reserved1;\n+\tuint8_t reserved1[2];\n \n \t/* accelerated low latency queues requirement. driver needs to\n \t * support those requirements in order to use accelerated llq\n@@ -822,7 +933,8 @@ enum ena_admin_os_type {\n \tENA_ADMIN_OS_FREEBSD = 4,\n \tENA_ADMIN_OS_IPXE = 5,\n \tENA_ADMIN_OS_ESXI = 6,\n-\tENA_ADMIN_OS_GROUPS_NUM = 6,\n+\tENA_ADMIN_OS_MACOS = 7,\n+\tENA_ADMIN_OS_GROUPS_NUM = 7,\n };\n \n struct ena_admin_host_info {\n@@ -871,7 +983,9 @@ struct ena_admin_host_info {\n \t * 2 : interrupt_moderation\n \t * 3 : rx_buf_mirroring\n \t * 4 : rss_configurable_function_key\n-\t * 31:5 : reserved\n+\t * 5 : reserved\n+\t * 6 : rx_page_reuse\n+\t * 31:7 : reserved\n \t */\n \tuint32_t driver_supported_features;\n };\n@@ -956,6 +1070,43 @@ struct ena_admin_queue_ext_feature_desc {\n \t};\n };\n \n+struct ena_admin_feature_phc_desc {\n+\t/* PHC type as defined in enum ena_admin_get_phc_type,\n+\t * used only for GET command.\n+\t */\n+\tuint8_t type;\n+\n+\t/* Reserved - MBZ */\n+\tuint8_t reserved1[3];\n+\n+\t/* PHC doorbell address as an offset to PCIe MMIO REG BAR,\n+\t * used only for GET command.\n+\t */\n+\tuint32_t doorbell_offset;\n+\n+\t/* Max time for valid PHC retrieval, passing this threshold will\n+\t * fail the get-time request and block PHC requests for\n+\t * block_timeout_usec, used only for GET command.\n+\t */\n+\tuint32_t expire_timeout_usec;\n+\n+\t/* PHC requests block period, blocking starts if PHC request expired\n+\t * in order to prevent floods on busy device,\n+\t * used only for GET command.\n+\t */\n+\tuint32_t block_timeout_usec;\n+\n+\t/* Shared PHC physical address (ena_admin_phc_resp),\n+\t * used only for SET command.\n+\t */\n+\tstruct ena_common_mem_addr output_address;\n+\n+\t/* Shared PHC Size (ena_admin_phc_resp),\n+\t * used only for SET command.\n+\t */\n+\tuint32_t output_length;\n+};\n+\n struct ena_admin_get_feat_resp {\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n@@ -986,6 +1137,8 @@ struct ena_admin_get_feat_resp {\n \n \t\tstruct ena_admin_ena_hw_hints hw_hints;\n \n+\t\tstruct ena_admin_feature_phc_desc phc;\n+\n \t\tstruct ena_admin_get_extra_properties_strings_desc extra_properties_strings;\n \n \t\tstruct ena_admin_get_extra_properties_flags_desc extra_properties_flags;\n@@ -1022,6 +1175,9 @@ struct ena_admin_set_feat_cmd {\n \n \t\t/* LLQ configuration */\n \t\tstruct ena_admin_feature_llq_desc llq;\n+\n+\t\t/* PHC configuration */\n+\t\tstruct ena_admin_feature_phc_desc phc;\n \t} u;\n };\n \n@@ -1057,12 +1213,11 @@ enum ena_admin_aenq_group {\n \tENA_ADMIN_WARNING = 2,\n \tENA_ADMIN_NOTIFICATION = 3,\n \tENA_ADMIN_KEEP_ALIVE = 4,\n-\tENA_ADMIN_AENQ_GROUPS_NUM = 5,\n+\tENA_ADMIN_REFRESH_CAPABILITIES = 5,\n+\tENA_ADMIN_AENQ_GROUPS_NUM = 6,\n };\n \n enum ena_admin_aenq_notification_syndrome {\n-\tENA_ADMIN_SUSPEND = 0,\n-\tENA_ADMIN_RESUME = 1,\n \tENA_ADMIN_UPDATE_HINTS = 2,\n };\n \n@@ -1090,6 +1245,10 @@ struct ena_admin_aenq_keep_alive_desc {\n \tuint32_t tx_drops_low;\n \n \tuint32_t tx_drops_high;\n+\n+\tuint32_t rx_overruns_low;\n+\n+\tuint32_t rx_overruns_high;\n };\n \n struct ena_admin_ena_mmio_req_read_less_resp {\n@@ -1101,6 +1260,16 @@ struct ena_admin_ena_mmio_req_read_less_resp {\n \tuint32_t reg_val;\n };\n \n+struct ena_admin_phc_resp {\n+\tuint16_t req_id;\n+\n+\tuint8_t reserved1[6];\n+\n+\tuint64_t timestamp;\n+\n+\tuint8_t reserved2[48];\n+};\n+\n /* aq_common_desc */\n #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)\n #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)\n@@ -1197,6 +1366,8 @@ struct ena_admin_ena_mmio_req_read_less_resp {\n #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)\n #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4\n #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)\n+#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6\n+#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)\n \n /* feature_rss_ind_table */\n #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)\n@@ -1658,6 +1829,19 @@ static inline void set_ena_admin_host_info_rss_configurable_function_key(struct\n \tp->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;\n }\n \n+static inline uint32_t get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info *p)\n+{\n+\treturn (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK) >>\n+\t\t\tENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT;\n+}\n+\n+static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info *p,\n+\t\t\t\t\t\t\t\t uint32_t val)\n+{\n+\tp->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT) &\n+\t\t\tENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK;\n+}\n+\n static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)\n {\n \treturn p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;\ndiff --git a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\nindex 2b934fff08..2107d17fdf 100644\n--- a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\n@@ -261,7 +261,8 @@ struct ena_eth_io_intr_reg {\n \t/* 14:0 : rx_intr_delay\n \t * 29:15 : tx_intr_delay\n \t * 30 : intr_unmask\n-\t * 31 : reserved\n+\t * 31 : no_moderation_update - 0 - moderation\n+\t * updated, 1 - moderation not updated\n \t */\n \tuint32_t intr_control;\n };\n@@ -381,6 +382,8 @@ struct ena_eth_io_numa_node_cfg_reg {\n #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)\n #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30\n #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)\n+#define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT 31\n+#define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK BIT(31)\n \n /* numa_node_cfg_reg */\n #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)\n@@ -918,6 +921,19 @@ static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_re\n \tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;\n }\n \n+static inline uint32_t get_ena_eth_io_intr_reg_no_mod_update(const struct ena_eth_io_intr_reg *p)\n+{\n+\treturn (p->intr_control & ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK) >>\n+\t\t\tENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT;\n+}\n+\n+static inline void set_ena_eth_io_intr_reg_no_mod_update(struct ena_eth_io_intr_reg *p,\n+\t\t\t\t\t\t\t\t\t uint32_t val)\n+{\n+\tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) &\n+\t\t\tENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK;\n+}\n+\n static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p)\n {\n \treturn p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;\ndiff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h\nindex 49895108d5..fc62201ccf 100644\n--- a/drivers/net/ena/base/ena_defs/ena_gen_info.h\n+++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h\n@@ -2,5 +2,5 @@\n * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.\n * All rights reserved.\n */\n-#define\tENA_GEN_DATE\t\"Fri Sep 18 17:09:00 IDT 2020\"\n-#define\tENA_GEN_COMMIT\t\"0f80d82\"\n+#define\tENA_GEN_DATE\t\"Thu 14 Apr 2022 12:50:30 PM IDT\"\n+#define\tENA_GEN_COMMIT\t\"35388392\"\ndiff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h\nindex 639cd98c0a..6a33f74812 100644\n--- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h\n@@ -21,6 +21,8 @@ enum ena_regs_reset_reason_types {\n \tENA_REGS_RESET_USER_TRIGGER = 12,\n \tENA_REGS_RESET_GENERIC = 13,\n \tENA_REGS_RESET_MISS_INTERRUPT = 14,\n+\tENA_REGS_RESET_SUSPECTED_POLL_STARVATION = 15,\n+\tENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED\t = 16,\n \tENA_REGS_RESET_LAST,\n };\n \n@@ -52,6 +54,11 @@ enum ena_regs_reset_reason_types {\n #define ENA_REGS_MMIO_RESP_HI_OFF 0x64\n #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68\n \n+/* phc_registers offsets */\n+\n+/* 100 base */\n+#define ENA_REGS_PHC_DB_OFF 0x100\n+\n /* version register */\n #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff\n #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8\n@@ -98,6 +105,8 @@ enum ena_regs_reset_reason_types {\n #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4\n #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3\n #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8\n+#define ENA_REGS_DEV_CTL_RESET_REASON_EXT_SHIFT 24\n+#define ENA_REGS_DEV_CTL_RESET_REASON_EXT_MASK 0xf000000\n #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28\n #define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000\n \n@@ -128,4 +137,7 @@ enum ena_regs_reset_reason_types {\n #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16\n #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000\n \n+/* phc_db_req_id register */\n+#define ENA_REGS_PHC_DB_REQ_ID_MASK 0xffff\n+\n #endif /* _ENA_REGS_H_ */\ndiff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c\nindex 92a9a10a9e..32090259cd 100644\n--- a/drivers/net/ena/base/ena_eth_com.c\n+++ b/drivers/net/ena/base/ena_eth_com.c\n@@ -150,7 +150,7 @@ static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)\n \t\treturn ENA_COM_OK;\n \n \t/* bounce buffer was used, so write it and get a new one */\n-\tif (pkt_ctrl->idx) {\n+\tif (likely(pkt_ctrl->idx)) {\n \t\trc = ena_com_write_bounce_buffer_to_dev(io_sq,\n \t\t\t\t\t\t\tpkt_ctrl->curr_bounce_buf);\n \t\tif (unlikely(rc)) {\n@@ -232,30 +232,43 @@ static struct ena_eth_io_rx_cdesc_base *\n \t\tidx * io_cq->cdesc_entry_size_in_bytes);\n }\n \n-static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n-\t\t\t\t\t u16 *first_cdesc_idx)\n+static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n+\t\t\t\t u16 *first_cdesc_idx,\n+\t\t\t\t u16 *num_descs)\n {\n+\tu16 count = io_cq->cur_rx_pkt_cdesc_count, head_masked;\n \tstruct ena_eth_io_rx_cdesc_base *cdesc;\n-\tu16 count = 0, head_masked;\n \tu32 last = 0;\n \n \tdo {\n+\t\tu32 status;\n+\n \t\tcdesc = ena_com_get_next_rx_cdesc(io_cq);\n \t\tif (!cdesc)\n \t\t\tbreak;\n+\t\tstatus = READ_ONCE32(cdesc->status);\n \n \t\tena_com_cq_inc_head(io_cq);\n+\t\tif (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >>\n+\t\t ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) {\n+\t\t\tstruct ena_com_dev *dev = ena_com_io_cq_to_ena_dev(io_cq);\n+\n+\t\t\tena_trc_err(dev,\n+\t\t\t\t \"First bit is on in descriptor #%d on q_id: %d, req_id: %u\\n\",\n+\t\t\t\t count, io_cq->qid, cdesc->req_id);\n+\t\t\treturn ENA_COM_FAULT;\n+\t\t}\n \t\tcount++;\n-\t\tlast = (READ_ONCE32(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>\n+\t\tlast = (status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>\n \t\t\tENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;\n \t} while (!last);\n \n \tif (last) {\n \t\t*first_cdesc_idx = io_cq->cur_rx_pkt_cdesc_start_idx;\n-\t\tcount += io_cq->cur_rx_pkt_cdesc_count;\n \n \t\thead_masked = io_cq->head & (io_cq->q_depth - 1);\n \n+\t\t*num_descs = count;\n \t\tio_cq->cur_rx_pkt_cdesc_count = 0;\n \t\tio_cq->cur_rx_pkt_cdesc_start_idx = head_masked;\n \n@@ -263,11 +276,11 @@ static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n \t\t\t \"ENA q_id: %d packets were completed. first desc idx %u descs# %d\\n\",\n \t\t\t io_cq->qid, *first_cdesc_idx, count);\n \t} else {\n-\t\tio_cq->cur_rx_pkt_cdesc_count += count;\n-\t\tcount = 0;\n+\t\tio_cq->cur_rx_pkt_cdesc_count = count;\n+\t\t*num_descs = 0;\n \t}\n \n-\treturn count;\n+\treturn ENA_COM_OK;\n }\n \n static int ena_com_create_meta(struct ena_com_io_sq *io_sq,\n@@ -326,9 +339,6 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,\n \t * compare it to the stored version, just create the meta\n \t */\n \tif (io_sq->disable_meta_caching) {\n-\t\tif (unlikely(!ena_tx_ctx->meta_valid))\n-\t\t\treturn ENA_COM_INVAL;\n-\n \t\t*have_meta = true;\n \t\treturn ena_com_create_meta(io_sq, ena_meta);\n \t}\n@@ -417,7 +427,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,\n \tif (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV\n \t\t && !buffer_to_push)) {\n \t\tena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),\n-\t\t\t \"Push header wasn't provided on LLQ mode\\n\");\n+\t\t\t \"Push header wasn't provided in LLQ mode\\n\");\n \t\treturn ENA_COM_INVAL;\n \t}\n \n@@ -537,9 +547,6 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,\n \t}\n \n \trc = ena_com_close_bounce_buffer(io_sq);\n-\tif (rc)\n-\t\tena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),\n-\t\t\t \"Failed when closing bounce buffer\\n\");\n \n \t*nb_hw_desc = io_sq->tail - start_tail;\n \treturn rc;\n@@ -555,11 +562,15 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,\n \tu16 cdesc_idx = 0;\n \tu16 nb_hw_desc;\n \tu16 i = 0;\n+\tint rc;\n \n \tENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,\n \t\t ena_com_io_cq_to_ena_dev(io_cq), \"wrong Q type\");\n \n-\tnb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);\n+\trc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx, &nb_hw_desc);\n+\tif (unlikely(rc != ENA_COM_OK))\n+\t\treturn ENA_COM_FAULT;\n+\n \tif (nb_hw_desc == 0) {\n \t\tena_rx_ctx->descs = nb_hw_desc;\n \t\treturn 0;\ndiff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h\nindex 0cfd18882e..cee4f35124 100644\n--- a/drivers/net/ena/base/ena_eth_com.h\n+++ b/drivers/net/ena/base/ena_eth_com.h\n@@ -11,8 +11,10 @@ extern \"C\" {\n #endif\n #include \"ena_com.h\"\n \n-/* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */\n-#define ENA_COMP_HEAD_THRESH 4\n+/* we allow 2 DMA descriptors per LLQ entry */\n+#define ENA_LLQ_ENTRY_DESC_CHUNK_SIZE\t(2 * sizeof(struct ena_eth_io_tx_desc))\n+#define ENA_LLQ_HEADER\t\t(128UL - ENA_LLQ_ENTRY_DESC_CHUNK_SIZE)\n+#define ENA_LLQ_LARGE_HEADER\t(256UL - ENA_LLQ_ENTRY_DESC_CHUNK_SIZE)\n \n struct ena_com_tx_ctx {\n \tstruct ena_com_tx_meta ena_meta;\n@@ -48,7 +50,7 @@ struct ena_com_rx_ctx {\n \tbool frag;\n \tu32 hash;\n \tu16 descs;\n-\tint max_bufs;\n+\tu16 max_bufs;\n \tu8 pkt_offset;\n };\n \n@@ -171,28 +173,6 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)\n \treturn 0;\n }\n \n-static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)\n-{\n-\tu16 unreported_comp, head;\n-\tbool need_update;\n-\n-\tif (unlikely(io_cq->cq_head_db_reg)) {\n-\t\thead = io_cq->head;\n-\t\tunreported_comp = head - io_cq->last_head_update;\n-\t\tneed_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);\n-\n-\t\tif (unlikely(need_update)) {\n-\t\t\tena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),\n-\t\t\t\t \"Write completion queue doorbell for queue %d: head: %d\\n\",\n-\t\t\t\t io_cq->qid, head);\n-\t\t\tENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);\n-\t\t\tio_cq->last_head_update = head;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,\n \t\t\t\t\t u8 numa_node)\n {\ndiff --git a/drivers/net/ena/base/ena_plat.h b/drivers/net/ena/base/ena_plat.h\nindex 2583823080..a3649e0cb6 100644\n--- a/drivers/net/ena/base/ena_plat.h\n+++ b/drivers/net/ena/base/ena_plat.h\n@@ -14,14 +14,16 @@\n #else\n #include <ena_plat_dpdk.h>\n #endif\n+#elif defined(_WIN32)\n+#include <ena_plat_windows.h>\n #elif defined(__FreeBSD__)\n-#if defined(_KERNEL)\n+#if defined(__KERNEL__)\n #include <ena_plat_fbsd.h>\n #else\n #include <ena_plat_dpdk.h>\n #endif\n-#elif defined(_WIN32)\n-#include <ena_plat_windows.h>\n+#elif defined(__APPLE__)\n+#include <ena_plat_macos.h>\n #else\n #error \"Invalid platform\"\n #endif\ndiff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h\nindex 8f2b3a87c2..37dc40b5b0 100644\n--- a/drivers/net/ena/base/ena_plat_dpdk.h\n+++ b/drivers/net/ena/base/ena_plat_dpdk.h\n@@ -40,7 +40,7 @@ typedef uint64_t dma_addr_t;\n #define ETIME ETIMEDOUT\n #endif\n \n-#define ENA_PRIu64 PRIu64\n+#define ENA_PRIU64 PRIu64\n #define ena_atomic32_t rte_atomic32_t\n #define ena_mem_handle_t const struct rte_memzone *\n \n@@ -57,9 +57,12 @@ typedef uint64_t dma_addr_t;\n #define ENA_COM_TRY_AGAIN\t-EAGAIN\n #define ENA_COM_UNSUPPORTED -EOPNOTSUPP\n #define ENA_COM_EIO -EIO\n+#define ENA_COM_DEVICE_BUSY\t-EBUSY\n \n #define ____cacheline_aligned __rte_cache_aligned\n \n+#define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */\n+\n #define ENA_ABORT() abort()\n \n #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000)\n@@ -107,6 +110,7 @@ extern int ena_logtype_com;\n #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)\n #define U64_C(x) x ## ULL\n #define BIT(nr) (1UL << (nr))\n+#define BIT64(nr)\tBIT(nr)\n #define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n #define GENMASK(h, l)\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) &\t\t \\\n@@ -121,8 +125,7 @@ extern int ena_logtype_com;\n \n #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg)\n #define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg)\n-#define ena_trc_warn(dev, format, arg...)\t\t\t\t \\\n-\tena_trc_log(dev, WARNING, format, ##arg)\n+#define ena_trc_warn(dev, format, arg...) ena_trc_log(dev, WARNING, format, ##arg)\n #define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg)\n \n #define ENA_WARN(cond, dev, format, arg...)\t\t\t\t \\\n@@ -138,9 +141,9 @@ extern int ena_logtype_com;\n #define ena_spinlock_t rte_spinlock_t\n #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&(spinlock))\n #define ENA_SPINLOCK_LOCK(spinlock, flags)\t\t\t\t \\\n-\t({(void)flags; rte_spinlock_lock(&(spinlock)); })\n+\t({(void)(flags); rte_spinlock_lock(&(spinlock)); })\n #define ENA_SPINLOCK_UNLOCK(spinlock, flags)\t\t\t\t \\\n-\t({(void)flags; rte_spinlock_unlock(&(spinlock)); })\n+\t({(void)(flags); rte_spinlock_unlock(&(spinlock)); })\n #define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock))\n \n typedef struct {\n@@ -199,9 +202,21 @@ typedef struct {\n #define ENA_MIGHT_SLEEP()\n \n #define ena_time_t uint64_t\n-#define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())\n-#define ENA_GET_SYSTEM_TIMEOUT(timeout_us)\t\t\t\t \\\n+#define ena_time_high_res_t uint64_t\n+\n+/* Note that high resolution timers are not used by the ENA PMD for now.\n+ * Although these macro definitions compile, it shall fail the\n+ * compilation in case the unimplemented API is called prematurely.\n+ */\n+#define ENA_TIME_EXPIRE(timeout) ((timeout) < rte_get_timer_cycles())\n+#define ENA_TIME_EXPIRE_HIGH_RES(timeout) (RTE_SET_USED(timeout), 0)\n+#define ENA_TIME_INIT_HIGH_RES() 0\n+#define ENA_TIME_COMPARE_HIGH_RES(time1, time2) (RTE_SET_USED(time1), RTE_SET_USED(time2), 0)\n+#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \\\n \t((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n+#define ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(current_time, timeout_us) \\\n+\t(RTE_SET_USED(current_time), RTE_SET_USED(timeout_us), 0)\n+#define ENA_GET_SYSTEM_TIME_HIGH_RES() 0\n \n const struct rte_memzone *\n ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,\n@@ -281,7 +296,6 @@ ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,\n #define lower_32_bits(x) ((uint32_t)(x))\n #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))\n \n-#define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())\n #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)\t\t\t\t \\\n \t((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue))\n@@ -306,6 +320,25 @@ void ena_rss_key_fill(void *key, size_t size);\n #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)\n \n #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0\n+#define ENA_INTR_INITIAL_RX_INTERVAL_USECS_PLAT 0\n \n #include \"ena_includes.h\"\n+\n+#define ENA_BITS_PER_U64(bitmap) (ena_bits_per_u64(bitmap))\n+\n+#define ENA_FIELD_GET(value, mask, offset) (((value) & (mask)) >> (offset))\n+\n+static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap)\n+{\n+\tint count = 0;\n+\n+\twhile (bitmap) {\n+\t\tbitmap &= (bitmap - 1);\n+\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n+\n #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */\ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex 7345e480f8..b764442dbb 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -1171,7 +1171,6 @@ static int ena_start(struct rte_eth_dev *dev)\n \tstruct ena_adapter *adapter = dev->data->dev_private;\n \tuint64_t ticks;\n \tint rc = 0;\n-\tuint16_t i;\n \n \t/* Cannot allocate memory in secondary process */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n@@ -1209,11 +1208,6 @@ static int ena_start(struct rte_eth_dev *dev)\n \t++adapter->dev_stats.dev_start;\n \tadapter->state = ENA_ADAPTER_STATE_RUNNING;\n \n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n-\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n-\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n-\n \treturn 0;\n \n err_rss_init:\n@@ -1229,7 +1223,6 @@ static int ena_stop(struct rte_eth_dev *dev)\n \tstruct ena_com_dev *ena_dev = &adapter->ena_dev;\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tuint16_t i;\n \tint rc;\n \n \t/* Cannot free memory in secondary process */\n@@ -1261,11 +1254,6 @@ static int ena_stop(struct rte_eth_dev *dev)\n \tadapter->state = ENA_ADAPTER_STATE_STOPPED;\n \tdev->data->dev_started = 0;\n \n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n-\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n-\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n \treturn 0;\n }\n \n@@ -2687,7 +2675,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \t/* Burst refill to save doorbells, memory barriers, const interval */\n \tif (free_queue_entries >= rx_ring->rx_free_thresh) {\n-\t\tena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);\n \t\tena_populate_rx_queue(rx_ring, free_queue_entries);\n \t}\n \n@@ -3096,7 +3083,6 @@ static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt)\n \t\t/* acknowledge completion of sent packets */\n \t\ttx_ring->next_to_clean = next_to_clean;\n \t\tena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);\n-\t\tena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);\n \t}\n \n \tif (mbuf_cnt != 0)\n@@ -3629,7 +3615,7 @@ static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,\n \tstruct ena_ring *rxq = &adapter->rx_ring[queue_id];\n \tstruct ena_eth_io_intr_reg intr_reg;\n \n-\tena_com_update_intr_reg(&intr_reg, 0, 0, unmask);\n+\tena_com_update_intr_reg(&intr_reg, 0, 0, unmask, 1);\n \tena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);\n }\n \n", "prefixes": [ "1/5" ] }