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GET /api/patches/133155/?format=api
{ "id": 133155, "url": "http://patches.dpdk.org/api/patches/133155/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231023044141.22112-35-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231023044141.22112-35-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231023044141.22112-35-syalavarthi@marvell.com", "date": "2023-10-23T04:41:37", "name": "[v8,34/34] ml/cnxk: enable creation of mvtvm virtual device", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aaccf31a382b90bbf9ae09a66970f8eece6b3806", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231023044141.22112-35-syalavarthi@marvell.com/mbox/", "series": [ { "id": 29941, "url": "http://patches.dpdk.org/api/series/29941/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29941", "date": "2023-10-23T04:41:04", "name": "Implementation of revised ml/cnxk driver", "version": 8, "mbox": "http://patches.dpdk.org/series/29941/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133155/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133155/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C86B9431DC;\n\tMon, 23 Oct 2023 06:47:58 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BE7E142DD8;\n\tMon, 23 Oct 2023 06:42:38 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 19591402E6\n for <dev@dpdk.org>; Mon, 23 Oct 2023 06:42:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39MLq9rx014581 for <dev@dpdk.org>; Sun, 22 Oct 2023 21:41:59 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3tve5mvbem-17\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 22 Oct 2023 21:41:59 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Sun, 22 Oct 2023 21:41:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Sun, 22 Oct 2023 21:41:56 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 344553F7044;\n Sun, 22 Oct 2023 21:41:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Jgxp6SVdAWDsrbIIHRwj7qKEsuphvW0S2YMl3164CFo=;\n b=KrHY4n5pkNbGGjfAe4/whfigU6ddwvkvGV2IoouRjUpo/xTsLvlUhFKhWTjBITJQAMJ0\n pfIShJkHQpKnwMWs/Ifl2GXukEflcYjXlI+QcwJGSngmO4K/VO6+JExDALGN2OwCwVP2\n iV5x41hO5c6K6HHW0zj27faNzUpbDalHAyp9aktO4q01oAu1UX9JyobL81ypBB7XSb01\n /LYE+oXVToU29pwE2nlbDuxoLilTpiCJ4w/Z4SimweItW+VGKkKslVQ7cEuCW9OvopG9\n poyN+iFIpuOiDgfrZMxtBhuJEJaFK+teKhNI7mCl/N4v+NS3iRZ07KLYg2h4Q9HlMNFD 0g==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <aprabhu@marvell.com>,\n <ptakkar@marvell.com>", "Subject": "[PATCH v8 34/34] ml/cnxk: enable creation of mvtvm virtual device", "Date": "Sun, 22 Oct 2023 21:41:37 -0700", "Message-ID": "<20231023044141.22112-35-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20231023044141.22112-1-syalavarthi@marvell.com>", "References": "<20230830155927.3566-1-syalavarthi@marvell.com>\n <20231023044141.22112-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "fTNuRQBMTOdzaSmh4JejSRiKqOFCRrhs", "X-Proofpoint-GUID": "fTNuRQBMTOdzaSmh4JejSRiKqOFCRrhs", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-23_01,2023-10-19_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enable support to create a mvtvm virtual device on\nsystem's without a PCI based ML HW accelerator.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n doc/guides/mldevs/cnxk.rst | 50 +++++++-\n drivers/ml/cnxk/cn10k_ml_dev.c | 8 ++\n drivers/ml/cnxk/cn10k_ml_dev.h | 3 +\n drivers/ml/cnxk/cnxk_ml_dev.c | 3 +\n drivers/ml/cnxk/cnxk_ml_dev.h | 21 ++++\n drivers/ml/cnxk/cnxk_ml_ops.c | 82 +++++++++----\n drivers/ml/cnxk/meson.build | 1 +\n drivers/ml/cnxk/mvtvm_ml_dev.c | 196 +++++++++++++++++++++++++++++++\n drivers/ml/cnxk/mvtvm_ml_dev.h | 40 +++++++\n drivers/ml/cnxk/mvtvm_ml_ops.c | 31 +++++\n drivers/ml/cnxk/mvtvm_ml_ops.h | 2 +\n drivers/ml/cnxk/mvtvm_ml_stubs.c | 18 +++\n drivers/ml/cnxk/mvtvm_ml_stubs.h | 2 +\n 13 files changed, 433 insertions(+), 24 deletions(-)\n create mode 100644 drivers/ml/cnxk/mvtvm_ml_dev.c\n create mode 100644 drivers/ml/cnxk/mvtvm_ml_dev.h", "diff": "diff --git a/doc/guides/mldevs/cnxk.rst b/doc/guides/mldevs/cnxk.rst\nindex a4d8903896..28e5b5b87f 100644\n--- a/doc/guides/mldevs/cnxk.rst\n+++ b/doc/guides/mldevs/cnxk.rst\n@@ -239,6 +239,23 @@ Bind the ML PF device to the vfio_pci driver:\n usertools/dpdk-devbind.py -u 0000:00:10.0\n usertools/dpdk-devbind.py -b vfio-pci 0000:00:10.0\n \n+VDEV support\n+------------\n+\n+On platforms which don't support ML hardware acceleration through PCI device, the\n+Marvell ML CNXK PMD can execute inference operations on a vdev with the ML models\n+compiled using Apache TVM framework.\n+\n+VDEV can be enabled by passing the EAL arguments\n+\n+.. code-block:: console\n+\n+ --vdev ml_mvtvm\n+\n+VDEV can also be used on platforms with ML HW accelerator. However to use VDEV in\n+this case, the PCI device has to be un-binded. When PCI device is binded, creation\n+of vdev is skipped.\n+\n \n Runtime Config Options\n ----------------------\n@@ -249,6 +266,8 @@ Runtime Config Options\n The parameter ``fw_path`` can be used by the user\n to load ML firmware from a custom path.\n \n+ This option is supported only on PCI HW accelerator.\n+\n For example::\n \n -a 0000:00:10.0,fw_path=\"/home/user/ml_fw.bin\"\n@@ -264,6 +283,8 @@ Runtime Config Options\n When enabled, firmware would mask the DPE non-fatal hardware errors as warnings.\n The parameter ``enable_dpe_warnings`` is used fo this configuration.\n \n+ This option is supported only on PCI HW accelerator.\n+\n For example::\n \n -a 0000:00:10.0,enable_dpe_warnings=0\n@@ -280,11 +301,19 @@ Runtime Config Options\n Caching of model data improves the inferencing throughput / latency for the model.\n The parameter ``cache_model_data`` is used to enable data caching.\n \n+ This option is supported on PCI HW accelerator and vdev.\n+\n For example::\n \n -a 0000:00:10.0,cache_model_data=0\n \n- With the above configuration, model data caching is disabled.\n+ With the above configuration, model data caching is disabled on HW accelerator.\n+\n+ For example::\n+\n+ --vdev ml_mvtvm,cache_model_data=0\n+\n+ With the above configuration, model data caching is disabled on vdev.\n \n \n **OCM allocation mode** (default ``lowest``)\n@@ -300,6 +329,8 @@ Runtime Config Options\n ``largest``\n Allocate OCM for the model from the slot with largest amount of free space.\n \n+ This option is supported only on PCI HW accelerator.\n+\n For example::\n \n -a 0000:00:10.0,ocm_alloc_mode=lowest\n@@ -317,6 +348,8 @@ Runtime Config Options\n Supported page sizes by the driver are 1 KB, 2 KB, 4 KB, 8 KB and 16 KB.\n Default page size is 16 KB.\n \n+ This option is supported only on PCI HW accelerator.\n+\n For example::\n \n -a 0000:00:10.0,ocm_page_size=8192\n@@ -341,6 +374,8 @@ Runtime Config Options\n Enabling spinlock version would disable restrictions on the number of queue-pairs\n that can be supported by the driver.\n \n+ This option is supported only on PCI HW accelerator.\n+\n For example::\n \n -a 0000:00:10.0,hw_queue_lock=1\n@@ -349,6 +384,19 @@ Runtime Config Options\n in the fast path enqueue burst operation.\n \n \n+**Maximum queue pairs** (default ``1``)\n+\n+ VDEV supports additional EAL arguments to configure the maximum number of\n+ queue-pairs on the ML device through the option ``max_qps``.\n+\n+ This option is supported only on vdev.\n+\n+ For example::\n+\n+ --vdev ml_mvtvm,max_qps=4\n+\n+ With the above configuration, 4 queue-pairs are created on the vdev.\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex 91813e9d0a..41f3b7a95d 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -309,6 +309,12 @@ cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_de\n \n \tPLT_SET_USED(pci_drv);\n \n+\tif (cnxk_ml_dev_initialized == 1) {\n+\t\tplt_err(\"ML CNXK device already initialized!\");\n+\t\tplt_err(\"Cannot initialize CN10K PCI dev\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \tinit_params = (struct rte_ml_dev_pmd_init_params){\n \t\t.socket_id = rte_socket_id(), .private_data_size = sizeof(struct cnxk_ml_dev)};\n \n@@ -355,6 +361,8 @@ cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_de\n \tdev->dequeue_burst = NULL;\n \tdev->op_error_get = NULL;\n \n+\tcnxk_ml_dev_initialized = 1;\n+\tcnxk_mldev->type = CNXK_ML_DEV_TYPE_PCI;\n \tcnxk_mldev->state = ML_CNXK_DEV_STATE_PROBED;\n \n \treturn 0;\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 2e7eb6c9ef..cee405f3f5 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -11,6 +11,9 @@\n \n #include \"cnxk_ml_io.h\"\n \n+/* Device status */\n+extern int cnxk_ml_dev_initialized;\n+\n /* Dummy Device ops */\n extern struct rte_ml_dev_ops ml_dev_dummy_ops;\n \ndiff --git a/drivers/ml/cnxk/cnxk_ml_dev.c b/drivers/ml/cnxk/cnxk_ml_dev.c\nindex 63d1c9e417..dc4512223c 100644\n--- a/drivers/ml/cnxk/cnxk_ml_dev.c\n+++ b/drivers/ml/cnxk/cnxk_ml_dev.c\n@@ -7,6 +7,9 @@\n \n #include \"cnxk_ml_dev.h\"\n \n+/* Device status */\n+int cnxk_ml_dev_initialized;\n+\n /* Dummy operations for ML device */\n struct rte_ml_dev_ops ml_dev_dummy_ops = {0};\n \ndiff --git a/drivers/ml/cnxk/cnxk_ml_dev.h b/drivers/ml/cnxk/cnxk_ml_dev.h\nindex 382fca64be..491c4c4aea 100644\n--- a/drivers/ml/cnxk/cnxk_ml_dev.h\n+++ b/drivers/ml/cnxk/cnxk_ml_dev.h\n@@ -9,6 +9,10 @@\n \n #include \"cn10k_ml_dev.h\"\n \n+#ifdef RTE_MLDEV_CNXK_ENABLE_MVTVM\n+#include \"mvtvm_ml_dev.h\"\n+#endif\n+\n #include \"cnxk_ml_xstats.h\"\n \n /* ML command timeout in seconds */\n@@ -34,6 +38,15 @@ struct cnxk_ml_error_db {\n \tchar str[RTE_ML_STR_MAX];\n };\n \n+/* Device type */\n+enum cnxk_ml_dev_type {\n+\t/* PCI based Marvell's ML HW accelerator device */\n+\tCNXK_ML_DEV_TYPE_PCI,\n+\n+\t/* Generic Virtual device */\n+\tCNXK_ML_DEV_TYPE_VDEV,\n+};\n+\n /* Device configuration state enum */\n enum cnxk_ml_dev_state {\n \t/* Probed and not configured */\n@@ -66,6 +79,9 @@ struct cnxk_ml_dev {\n \t/* RTE device */\n \tstruct rte_ml_dev *mldev;\n \n+\t/* Device type */\n+\tenum cnxk_ml_dev_type type;\n+\n \t/* Configuration state */\n \tenum cnxk_ml_dev_state state;\n \n@@ -87,6 +103,11 @@ struct cnxk_ml_dev {\n \t/* CN10K device structure */\n \tstruct cn10k_ml_dev cn10k_mldev;\n \n+#ifdef RTE_MLDEV_CNXK_ENABLE_MVTVM\n+\t/* MVTVM device structure */\n+\tstruct mvtvm_ml_dev mvtvm_mldev;\n+#endif\n+\n \t/* Maximum number of layers */\n \tuint64_t max_nb_layers;\n \ndiff --git a/drivers/ml/cnxk/cnxk_ml_ops.c b/drivers/ml/cnxk/cnxk_ml_ops.c\nindex bf266d4d6e..36a5dcf9b0 100644\n--- a/drivers/ml/cnxk/cnxk_ml_ops.c\n+++ b/drivers/ml/cnxk/cnxk_ml_ops.c\n@@ -117,7 +117,8 @@ cnxk_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_desc\n \tqp->stats.enqueue_err_count = 0;\n \tqp->stats.dequeue_err_count = 0;\n \n-\tcn10k_ml_qp_initialize(cnxk_mldev, qp);\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI)\n+\t\tcn10k_ml_qp_initialize(cnxk_mldev, qp);\n \n \treturn qp;\n \n@@ -480,7 +481,12 @@ cnxk_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n \tdev_info->driver_name = dev->device->driver->name;\n \tdev_info->max_models = ML_CNXK_MAX_MODELS;\n \n-\treturn cn10k_ml_dev_info_get(cnxk_mldev, dev_info);\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI)\n+\t\treturn cn10k_ml_dev_info_get(cnxk_mldev, dev_info);\n+\telse\n+\t\treturn mvtvm_ml_dev_info_get(cnxk_mldev, dev_info);\n+\n+\treturn 0;\n }\n \n static int\n@@ -518,9 +524,11 @@ cnxk_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *co\n \t\t\t conf->nb_queue_pairs, conf->nb_models);\n \n \t\t/* Load firmware */\n-\t\tret = cn10k_ml_fw_load(cnxk_mldev);\n-\t\tif (ret != 0)\n-\t\t\treturn ret;\n+\t\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI) {\n+\t\t\tret = cn10k_ml_fw_load(cnxk_mldev);\n+\t\t\tif (ret != 0)\n+\t\t\t\treturn ret;\n+\t\t}\n \t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_CONFIGURED) {\n \t\tplt_ml_dbg(\"Re-configuring ML device, nb_queue_pairs = %u, nb_models = %u\",\n \t\t\t conf->nb_queue_pairs, conf->nb_models);\n@@ -618,10 +626,12 @@ cnxk_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *co\n \t}\n \tdev->data->nb_models = conf->nb_models;\n \n-\tret = cn10k_ml_dev_configure(cnxk_mldev, conf);\n-\tif (ret != 0) {\n-\t\tplt_err(\"Failed to configure CN10K ML Device\");\n-\t\tgoto error;\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI) {\n+\t\tret = cn10k_ml_dev_configure(cnxk_mldev, conf);\n+\t\tif (ret != 0) {\n+\t\t\tplt_err(\"Failed to configure CN10K ML Device\");\n+\t\t\tgoto error;\n+\t\t}\n \t}\n \n \tret = mvtvm_ml_dev_configure(cnxk_mldev, conf);\n@@ -629,12 +639,17 @@ cnxk_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *co\n \t\tgoto error;\n \n \t/* Set device capabilities */\n-\tcnxk_mldev->max_nb_layers =\n-\t\tcnxk_mldev->cn10k_mldev.fw.req->cn10k_req.jd.fw_load.cap.s.max_models;\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI)\n+\t\tcnxk_mldev->max_nb_layers =\n+\t\t\tcnxk_mldev->cn10k_mldev.fw.req->cn10k_req.jd.fw_load.cap.s.max_models;\n+\telse\n+\t\tcnxk_mldev->max_nb_layers = ML_CNXK_MAX_MODELS;\n \n \tcnxk_mldev->mldev->enqueue_burst = cnxk_ml_enqueue_burst;\n \tcnxk_mldev->mldev->dequeue_burst = cnxk_ml_dequeue_burst;\n-\tcnxk_mldev->mldev->op_error_get = cn10k_ml_op_error_get;\n+\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI)\n+\t\tcnxk_mldev->mldev->op_error_get = cn10k_ml_op_error_get;\n \n \t/* Allocate and initialize index_map */\n \tif (cnxk_mldev->index_map == NULL) {\n@@ -695,8 +710,10 @@ cnxk_ml_dev_close(struct rte_ml_dev *dev)\n \tif (mvtvm_ml_dev_close(cnxk_mldev) != 0)\n \t\tplt_err(\"Failed to close MVTVM ML Device\");\n \n-\tif (cn10k_ml_dev_close(cnxk_mldev) != 0)\n-\t\tplt_err(\"Failed to close CN10K ML Device\");\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI) {\n+\t\tif (cn10k_ml_dev_close(cnxk_mldev) != 0)\n+\t\t\tplt_err(\"Failed to close CN10K ML Device\");\n+\t}\n \n \tif (cnxk_mldev->index_map)\n \t\trte_free(cnxk_mldev->index_map);\n@@ -748,10 +765,12 @@ cnxk_ml_dev_start(struct rte_ml_dev *dev)\n \n \tcnxk_mldev = dev->data->dev_private;\n \n-\tret = cn10k_ml_dev_start(cnxk_mldev);\n-\tif (ret != 0) {\n-\t\tplt_err(\"Failed to start CN10K ML Device\");\n-\t\treturn ret;\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI) {\n+\t\tret = cn10k_ml_dev_start(cnxk_mldev);\n+\t\tif (ret != 0) {\n+\t\t\tplt_err(\"Failed to start CN10K ML Device\");\n+\t\t\treturn ret;\n+\t\t}\n \t}\n \n \tcnxk_mldev->state = ML_CNXK_DEV_STATE_STARTED;\n@@ -770,10 +789,12 @@ cnxk_ml_dev_stop(struct rte_ml_dev *dev)\n \n \tcnxk_mldev = dev->data->dev_private;\n \n-\tret = cn10k_ml_dev_stop(cnxk_mldev);\n-\tif (ret != 0) {\n-\t\tplt_err(\"Failed to stop CN10K ML Device\");\n-\t\treturn ret;\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI) {\n+\t\tret = cn10k_ml_dev_stop(cnxk_mldev);\n+\t\tif (ret != 0) {\n+\t\t\tplt_err(\"Failed to stop CN10K ML Device\");\n+\t\t\treturn ret;\n+\t\t}\n \t}\n \n \tcnxk_mldev->state = ML_CNXK_DEV_STATE_CONFIGURED;\n@@ -800,7 +821,12 @@ cnxk_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp)\n \t\t\tcnxk_ml_model_dump(cnxk_mldev, model, fp);\n \t}\n \n-\treturn cn10k_ml_dev_dump(cnxk_mldev, fp);\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_PCI)\n+\t\treturn cn10k_ml_dev_dump(cnxk_mldev, fp);\n+\telse\n+\t\treturn mvtvm_ml_dev_dump(cnxk_mldev, fp);\n+\n+\treturn 0;\n }\n \n static int\n@@ -813,6 +839,9 @@ cnxk_ml_dev_selftest(struct rte_ml_dev *dev)\n \n \tcnxk_mldev = dev->data->dev_private;\n \n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_VDEV)\n+\t\treturn -ENOTSUP;\n+\n \treturn cn10k_ml_dev_selftest(cnxk_mldev);\n }\n \n@@ -1145,6 +1174,11 @@ cnxk_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, u\n \t\treturn -EINVAL;\n \t}\n \n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_VDEV && type != ML_CNXK_MODEL_TYPE_TVM) {\n+\t\tplt_err(\"Unsupported model type\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Find model ID */\n \tfound = false;\n \tfor (lcl_model_id = 0; lcl_model_id < dev->data->nb_models; lcl_model_id++) {\n@@ -1384,6 +1418,8 @@ cnxk_ml_model_params_update(struct rte_ml_dev *dev, uint16_t model_id, void *buf\n \t\treturn -EINVAL;\n \n \tcnxk_mldev = dev->data->dev_private;\n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_VDEV)\n+\t\treturn -ENOTSUP;\n \n \tmodel = dev->data->models[model_id];\n \tif (model == NULL) {\ndiff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build\nindex 20534d0b00..0680a0faa5 100644\n--- a/drivers/ml/cnxk/meson.build\n+++ b/drivers/ml/cnxk/meson.build\n@@ -62,6 +62,7 @@ if enable_mvtvm\n dpdk_conf.set('RTE_MLDEV_CNXK_ENABLE_MVTVM', 1)\n \n sources += files(\n+ 'mvtvm_ml_dev.c',\n 'mvtvm_ml_ops.c',\n 'mvtvm_ml_model.c',\n )\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_dev.c b/drivers/ml/cnxk/mvtvm_ml_dev.c\nnew file mode 100644\nindex 0000000000..dcac7b7273\n--- /dev/null\n+++ b/drivers/ml/cnxk/mvtvm_ml_dev.c\n@@ -0,0 +1,196 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Marvell.\n+ */\n+\n+#include <rte_kvargs.h>\n+#include <rte_mldev.h>\n+#include <rte_mldev_pmd.h>\n+\n+#include <bus_vdev_driver.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cnxk_ml_dev.h\"\n+\n+#define MVTVM_ML_DEV_MAX_QPS\t \"max_qps\"\n+#define MVTVM_ML_DEV_CACHE_MODEL_DATA \"cache_model_data\"\n+\n+#define MVTVM_ML_DEV_MAX_QPS_DEFAULT\t 32\n+#define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT 1\n+\n+static const char *const valid_args[] = {MVTVM_ML_DEV_MAX_QPS, MVTVM_ML_DEV_CACHE_MODEL_DATA, NULL};\n+\n+static int\n+parse_integer_arg(const char *key __rte_unused, const char *value, void *extra_args)\n+{\n+\tint *i = (int *)extra_args;\n+\n+\t*i = atoi(value);\n+\tif (*i < 0) {\n+\t\tplt_err(\"Argument has to be positive.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_uint_arg(const char *key __rte_unused, const char *value, void *extra_args)\n+{\n+\tint i;\n+\tchar *end;\n+\terrno = 0;\n+\n+\ti = strtol(value, &end, 10);\n+\tif (*end != 0 || errno != 0 || i < 0)\n+\t\treturn -EINVAL;\n+\n+\t*((uint32_t *)extra_args) = i;\n+\n+\treturn 0;\n+}\n+\n+static int\n+mvtvm_mldev_parse_devargs(const char *args, struct mvtvm_ml_dev *mvtvm_mldev)\n+{\n+\tbool cache_model_data_set = false;\n+\tstruct rte_kvargs *kvlist = NULL;\n+\tbool max_qps_set = false;\n+\tint ret = 0;\n+\n+\tif (args == NULL)\n+\t\tgoto check_args;\n+\n+\tkvlist = rte_kvargs_parse(args, valid_args);\n+\tif (kvlist == NULL) {\n+\t\tplt_err(\"Error parsing %s devargs\\n\", \"MLDEV_NAME_MVTVM_PMD\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, MVTVM_ML_DEV_MAX_QPS) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_MAX_QPS, &parse_uint_arg,\n+\t\t\t\t\t &mvtvm_mldev->max_nb_qpairs);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\", MVTVM_ML_DEV_MAX_QPS);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tmax_qps_set = true;\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, MVTVM_ML_DEV_CACHE_MODEL_DATA) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, MVTVM_ML_DEV_CACHE_MODEL_DATA, &parse_integer_arg,\n+\t\t\t\t\t &mvtvm_mldev->cache_model_data);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\",\n+\t\t\t\tMVTVM_ML_DEV_CACHE_MODEL_DATA);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tcache_model_data_set = true;\n+\t}\n+\n+check_args:\n+\tif (!max_qps_set)\n+\t\tmvtvm_mldev->max_nb_qpairs = MVTVM_ML_DEV_MAX_QPS_DEFAULT;\n+\tplt_ml_dbg(\"ML: %s = %u\", MVTVM_ML_DEV_MAX_QPS, mvtvm_mldev->max_nb_qpairs);\n+\n+\tif (!cache_model_data_set) {\n+\t\tmvtvm_mldev->cache_model_data = CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT;\n+\t} else {\n+\t\tif ((mvtvm_mldev->cache_model_data < 0) || (mvtvm_mldev->cache_model_data > 1)) {\n+\t\t\tplt_err(\"Invalid argument, %s = %d\\n\", MVTVM_ML_DEV_CACHE_MODEL_DATA,\n+\t\t\t\tmvtvm_mldev->cache_model_data);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\tplt_ml_dbg(\"ML: %s = %d\", MVTVM_ML_DEV_CACHE_MODEL_DATA, mvtvm_mldev->cache_model_data);\n+\n+exit:\n+\tif (kvlist)\n+\t\trte_kvargs_free(kvlist);\n+\n+\treturn ret;\n+}\n+\n+static int\n+mvtvm_ml_vdev_probe(struct rte_vdev_device *vdev)\n+{\n+\tstruct rte_ml_dev_pmd_init_params init_params;\n+\tstruct mvtvm_ml_dev *mvtvm_mldev;\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\tstruct rte_ml_dev *dev;\n+\tconst char *input_args;\n+\tconst char *name;\n+\tint ret = 0;\n+\n+\tif (cnxk_ml_dev_initialized == 1) {\n+\t\tplt_err(\"ML CNXK device already initialized!\");\n+\t\tplt_err(\"Not creating ml_mvtvm vdev!\");\n+\t\treturn 0;\n+\t}\n+\n+\tinit_params = (struct rte_ml_dev_pmd_init_params){\n+\t\t.socket_id = rte_socket_id(), .private_data_size = sizeof(struct cnxk_ml_dev)};\n+\n+\tname = rte_vdev_device_name(vdev);\n+\tif (name == NULL)\n+\t\treturn -EINVAL;\n+\tinput_args = rte_vdev_device_args(vdev);\n+\n+\tdev = rte_ml_dev_pmd_create(name, &vdev->device, &init_params);\n+\tif (dev == NULL) {\n+\t\tret = -EFAULT;\n+\t\tgoto error_exit;\n+\t}\n+\n+\tcnxk_mldev = dev->data->dev_private;\n+\tcnxk_mldev->mldev = dev;\n+\tmvtvm_mldev = &cnxk_mldev->mvtvm_mldev;\n+\tmvtvm_mldev->vdev = vdev;\n+\n+\tret = mvtvm_mldev_parse_devargs(input_args, mvtvm_mldev);\n+\tif (ret < 0)\n+\t\tgoto error_exit;\n+\n+\tdev->dev_ops = &cnxk_ml_ops;\n+\tdev->enqueue_burst = NULL;\n+\tdev->dequeue_burst = NULL;\n+\tdev->op_error_get = NULL;\n+\n+\tcnxk_ml_dev_initialized = 1;\n+\tcnxk_mldev->type = CNXK_ML_DEV_TYPE_VDEV;\n+\n+\treturn 0;\n+\n+error_exit:\n+\tplt_err(\"Could not create device: ml_mvtvm\");\n+\n+\treturn ret;\n+}\n+\n+static int\n+mvtvm_ml_vdev_remove(struct rte_vdev_device *vdev)\n+{\n+\tstruct rte_ml_dev *dev;\n+\tconst char *name;\n+\n+\tname = rte_vdev_device_name(vdev);\n+\tif (name == NULL)\n+\t\treturn -EINVAL;\n+\n+\tdev = rte_ml_dev_pmd_get_named_dev(name);\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\treturn rte_ml_dev_pmd_destroy(dev);\n+}\n+\n+static struct rte_vdev_driver mvtvm_mldev_pmd = {.probe = mvtvm_ml_vdev_probe,\n+\t\t\t\t\t\t .remove = mvtvm_ml_vdev_remove};\n+\n+RTE_PMD_REGISTER_VDEV(MLDEV_NAME_MVTVM_PMD, mvtvm_mldev_pmd);\n+\n+RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_MVTVM_PMD,\n+\t\t\t MVTVM_ML_DEV_MAX_QPS \"=<int>\" MVTVM_ML_DEV_CACHE_MODEL_DATA \"=<0|1>\");\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_dev.h b/drivers/ml/cnxk/mvtvm_ml_dev.h\nnew file mode 100644\nindex 0000000000..6922c19337\n--- /dev/null\n+++ b/drivers/ml/cnxk/mvtvm_ml_dev.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Marvell.\n+ */\n+\n+#ifndef _MVTVM_ML_DEV_H_\n+#define _MVTVM_ML_DEV_H_\n+\n+#include <rte_mldev_core.h>\n+\n+/* Device status */\n+extern int cnxk_ml_dev_initialized;\n+\n+/* CNXK Device ops */\n+extern struct rte_ml_dev_ops cnxk_ml_ops;\n+\n+/* Marvell MVTVM ML PMD device name */\n+#define MLDEV_NAME_MVTVM_PMD ml_mvtvm\n+\n+/* Maximum number of descriptors per queue-pair */\n+#define ML_MVTVM_MAX_DESC_PER_QP 1024\n+\n+/* Maximum number of inputs / outputs per model */\n+#define ML_MVTVM_MAX_INPUT_OUTPUT 32\n+\n+/* Maximum number of segments for IO data */\n+#define ML_MVTVM_MAX_SEGMENTS 1\n+\n+/* Device private data */\n+struct mvtvm_ml_dev {\n+\t/* Virtual device */\n+\tstruct rte_vdev_device *vdev;\n+\n+\t/* Maximum number of queue pairs */\n+\tuint16_t max_nb_qpairs;\n+\n+\t/* Enable / disable model data caching */\n+\tint cache_model_data;\n+};\n+\n+#endif /* _MVTVM_ML_DEV_H_ */\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_ops.c b/drivers/ml/cnxk/mvtvm_ml_ops.c\nindex 6b88491371..e825c3fb23 100644\n--- a/drivers/ml/cnxk/mvtvm_ml_ops.c\n+++ b/drivers/ml/cnxk/mvtvm_ml_ops.c\n@@ -97,6 +97,22 @@ mvtvm_ml_model_xstat_get(struct cnxk_ml_dev *cnxk_mldev, struct cnxk_ml_model *m\n \treturn value;\n }\n \n+int\n+mvtvm_ml_dev_info_get(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_dev_info *dev_info)\n+{\n+\tstruct mvtvm_ml_dev *mvtvm_mldev;\n+\n+\tmvtvm_mldev = &cnxk_mldev->mvtvm_mldev;\n+\n+\tdev_info->max_queue_pairs = mvtvm_mldev->max_nb_qpairs;\n+\tdev_info->max_desc = ML_MVTVM_MAX_DESC_PER_QP;\n+\tdev_info->max_io = ML_MVTVM_MAX_INPUT_OUTPUT;\n+\tdev_info->max_segments = ML_MVTVM_MAX_SEGMENTS;\n+\tdev_info->align_size = RTE_CACHE_LINE_SIZE;\n+\n+\treturn 0;\n+}\n+\n int\n mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf)\n {\n@@ -127,6 +143,15 @@ mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev)\n \treturn ret;\n }\n \n+int\n+mvtvm_ml_dev_dump(struct cnxk_ml_dev *cnxk_mldev, FILE *fp)\n+{\n+\tRTE_SET_USED(cnxk_mldev);\n+\tRTE_SET_USED(fp);\n+\n+\treturn 0;\n+}\n+\n int\n mvtvm_ml_model_load(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_model_params *params,\n \t\t struct cnxk_ml_model *model)\n@@ -237,6 +262,12 @@ mvtvm_ml_model_load(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_model_params *\n \telse\n \t\tmodel->subtype = ML_CNXK_MODEL_SUBTYPE_TVM_HYBRID;\n \n+\tif (cnxk_mldev->type == CNXK_ML_DEV_TYPE_VDEV &&\n+\t model->subtype != ML_CNXK_MODEL_SUBTYPE_TVM_LLVM) {\n+\t\tplt_err(\"Unsupported model sub-type\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Set callback function array */\n \tif (model->subtype != ML_CNXK_MODEL_SUBTYPE_TVM_LLVM) {\n \t\tcallback = &model->mvtvm.cb;\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_ops.h b/drivers/ml/cnxk/mvtvm_ml_ops.h\nindex cb4b219743..0232c5ead5 100644\n--- a/drivers/ml/cnxk/mvtvm_ml_ops.h\n+++ b/drivers/ml/cnxk/mvtvm_ml_ops.h\n@@ -55,8 +55,10 @@ struct mvtvm_ml_req {\n \tstruct mvtvm_ml_result result;\n };\n \n+int mvtvm_ml_dev_info_get(struct cnxk_ml_dev *mldev, struct rte_ml_dev_info *dev_info);\n int mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf);\n int mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev);\n+int mvtvm_ml_dev_dump(struct cnxk_ml_dev *cnxk_mldev, FILE *fp);\n int mvtvm_ml_model_load(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_model_params *params,\n \t\t\tstruct cnxk_ml_model *model);\n int mvtvm_ml_model_unload(struct cnxk_ml_dev *cnxk_mldev, struct cnxk_ml_model *model);\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_stubs.c b/drivers/ml/cnxk/mvtvm_ml_stubs.c\nindex 19af1d2703..126a954c91 100644\n--- a/drivers/ml/cnxk/mvtvm_ml_stubs.c\n+++ b/drivers/ml/cnxk/mvtvm_ml_stubs.c\n@@ -67,6 +67,15 @@ mvtvm_ml_model_xstat_get(struct cnxk_ml_dev *cnxk_mldev, struct cnxk_ml_model *m\n \treturn 0;\n }\n \n+int\n+mvtvm_ml_dev_info_get(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_dev_info *dev_info)\n+{\n+\tRTE_SET_USED(cnxk_mldev);\n+\tRTE_SET_USED(dev_info);\n+\n+\treturn -ENOTSUP;\n+}\n+\n int\n mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf)\n {\n@@ -84,6 +93,15 @@ mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev)\n \treturn 0;\n }\n \n+int\n+mvtvm_ml_dev_dump(struct cnxk_ml_dev *cnxk_mldev, FILE *fp)\n+{\n+\tRTE_SET_USED(cnxk_mldev);\n+\tRTE_SET_USED(fp);\n+\n+\treturn -EINVAL;\n+}\n+\n int\n mvtvm_ml_model_load(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_model_params *params,\n \t\t struct cnxk_ml_model *model)\ndiff --git a/drivers/ml/cnxk/mvtvm_ml_stubs.h b/drivers/ml/cnxk/mvtvm_ml_stubs.h\nindex 3fd1f04c35..4220a963f2 100644\n--- a/drivers/ml/cnxk/mvtvm_ml_stubs.h\n+++ b/drivers/ml/cnxk/mvtvm_ml_stubs.h\n@@ -14,8 +14,10 @@ struct cnxk_ml_model;\n struct cnxk_ml_layer;\n \n enum cnxk_ml_model_type mvtvm_ml_model_type_get(struct rte_ml_model_params *params);\n+int mvtvm_ml_dev_info_get(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_dev_info *dev_info);\n int mvtvm_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf);\n int mvtvm_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev);\n+int mvtvm_ml_dev_dump(struct cnxk_ml_dev *cnxk_mldev, FILE *fp);\n int mvtvm_ml_model_load(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_model_params *params,\n \t\t\tstruct cnxk_ml_model *model);\n int mvtvm_ml_model_unload(struct cnxk_ml_dev *cnxk_mldev, struct cnxk_ml_model *model);\n", "prefixes": [ "v8", "34/34" ] }