Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132885/?format=api
{ "id": 132885, "url": "http://patches.dpdk.org/api/patches/132885/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231018080725.613579-4-vattunuru@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231018080725.613579-4-vattunuru@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231018080725.613579-4-vattunuru@marvell.com", "date": "2023-10-18T08:07:25", "name": "[v5,3/3] net/octeon_ep: add new fastpath routines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "83adf5179032feea74a4c7c829e3f259ba0a0f7f", "submitter": { "id": 1277, "url": "http://patches.dpdk.org/api/people/1277/?format=api", "name": "Vamsi Krishna Attunuru", "email": "vattunuru@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231018080725.613579-4-vattunuru@marvell.com/mbox/", "series": [ { "id": 29901, "url": "http://patches.dpdk.org/api/series/29901/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29901", "date": "2023-10-18T08:07:22", "name": "rewrite fastpath routines", "version": 5, "mbox": "http://patches.dpdk.org/series/29901/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132885/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/132885/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 86DF743198;\n\tWed, 18 Oct 2023 10:07:50 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2D80D42D6B;\n\tWed, 18 Oct 2023 10:07:39 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9248542D26\n for <dev@dpdk.org>; Wed, 18 Oct 2023 10:07:37 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39I7okhJ009779 for <dev@dpdk.org>; Wed, 18 Oct 2023 01:07:36 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tt14820m3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 18 Oct 2023 01:07:36 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 18 Oct 2023 01:07:34 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 18 Oct 2023 01:07:34 -0700", "from localhost.localdomain (unknown [10.28.36.156])\n by maili.marvell.com (Postfix) with ESMTP id 7D3B43F7075;\n Wed, 18 Oct 2023 01:07:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=/JB/PUzxyOIsZgey6mEUFrNyG5EWNYegkBSGkn+YDco=;\n b=ao56Jp0nWb+OHOm3xZ/elSQTr4ZtX+aeIxFkJcVc59Ci7nXs2EggJhypw55GUW8TVYEg\n z3wyEiVgqjLF5dkTTN9/02ofs18FCUQoS8Wb5BtTrH2kK1u2b7QkBHPfC5s/egl+vLpM\n Jn/ECjUeXC79kPwyQed0NV7NZkJtBfCZnVXQOw0MnEA/Tn/sq325SkailPsuF8JfRSPP\n nq3L9Ph+DjQ3E4dEJXdd0ZKGaDI/qsCRktP1an5/H6zoApUcDMCp0G6C+Zbhk2UCZY1M\n /WLOBdHpCU1sLYQnjCAbFInyF1jT14l1zUTh9nLhJWf/2kQO0NMFc3yzHsUtrVtMV3iZ WA==", "From": "Vamsi Attunuru <vattunuru@marvell.com>", "To": "<dev@dpdk.org>, <jerinj@marvell.com>", "CC": "<sthotton@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Subject": "[PATCH v5 3/3] net/octeon_ep: add new fastpath routines", "Date": "Wed, 18 Oct 2023 01:07:25 -0700", "Message-ID": "<20231018080725.613579-4-vattunuru@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231018080725.613579-1-vattunuru@marvell.com>", "References": "<20231012062354.535392-1-vattunuru@marvell.com>\n <20231018080725.613579-1-vattunuru@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "nvtXco1hTGifOiPlT1ePCHVGKbzPKAr5", "X-Proofpoint-ORIG-GUID": "nvtXco1hTGifOiPlT1ePCHVGKbzPKAr5", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-18_06,2023-10-17_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds new fastpath routines for cn10k & cn9k endpoint\ndevices and assigns the fastpath routines based on\nthe offload flags.\n\nPatch also adds misc changes to improve performance\nand code-readability.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/net/octeon_ep/cnxk_ep_rx.c | 310 ++++++++++++++++++++++++++\n drivers/net/octeon_ep/cnxk_ep_tx.c | 210 +++++++++++++++++\n drivers/net/octeon_ep/cnxk_ep_vf.c | 2 +\n drivers/net/octeon_ep/cnxk_ep_vf.h | 13 ++\n drivers/net/octeon_ep/meson.build | 2 +\n drivers/net/octeon_ep/otx2_ep_vf.c | 1 +\n drivers/net/octeon_ep/otx_ep_common.h | 125 ++++++-----\n drivers/net/octeon_ep/otx_ep_ethdev.c | 69 +++++-\n drivers/net/octeon_ep/otx_ep_rxtx.c | 93 +-------\n drivers/net/octeon_ep/otx_ep_rxtx.h | 38 +++-\n 10 files changed, 706 insertions(+), 157 deletions(-)", "diff": "diff --git a/drivers/net/octeon_ep/cnxk_ep_rx.c b/drivers/net/octeon_ep/cnxk_ep_rx.c\nnew file mode 100644\nindex 0000000000..22bf3ce7a7\n--- /dev/null\n+++ b/drivers/net/octeon_ep/cnxk_ep_rx.c\n@@ -0,0 +1,310 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#include \"otx_ep_common.h\"\n+#include \"otx2_ep_vf.h\"\n+#include \"otx_ep_rxtx.h\"\n+\n+static inline int\n+cnxk_ep_rx_refill_mbuf(struct otx_ep_droq *droq, uint32_t count)\n+{\n+\tstruct otx_ep_droq_desc *desc_ring = droq->desc_ring;\n+\tstruct rte_mbuf **recv_buf_list = droq->recv_buf_list;\n+\tuint32_t refill_idx = droq->refill_idx;\n+\tstruct rte_mbuf *buf;\n+\tuint32_t i;\n+\tint rc;\n+\n+\trc = rte_pktmbuf_alloc_bulk(droq->mpool, &recv_buf_list[refill_idx], count);\n+\tif (unlikely(rc)) {\n+\t\tdroq->stats.rx_alloc_failure++;\n+\t\treturn rc;\n+\t}\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tbuf = recv_buf_list[refill_idx];\n+\t\tdesc_ring[refill_idx].buffer_ptr = rte_mbuf_data_iova_default(buf);\n+\t\trefill_idx++;\n+\t}\n+\n+\tdroq->refill_idx = otx_ep_incr_index(droq->refill_idx, count, droq->nb_desc);\n+\tdroq->refill_count -= count;\n+\n+\treturn 0;\n+}\n+\n+static inline void\n+cnxk_ep_rx_refill(struct otx_ep_droq *droq)\n+{\n+\tuint32_t desc_refilled = 0, count;\n+\tuint32_t nb_desc = droq->nb_desc;\n+\tuint32_t refill_idx = droq->refill_idx;\n+\tint rc;\n+\n+\tif (unlikely(droq->read_idx == refill_idx))\n+\t\treturn;\n+\n+\tif (refill_idx < droq->read_idx) {\n+\t\tcount = droq->read_idx - refill_idx;\n+\t\trc = cnxk_ep_rx_refill_mbuf(droq, count);\n+\t\tif (unlikely(rc)) {\n+\t\t\tdroq->stats.rx_alloc_failure++;\n+\t\t\treturn;\n+\t\t}\n+\t\tdesc_refilled = count;\n+\t} else {\n+\t\tcount = nb_desc - refill_idx;\n+\t\trc = cnxk_ep_rx_refill_mbuf(droq, count);\n+\t\tif (unlikely(rc)) {\n+\t\t\tdroq->stats.rx_alloc_failure++;\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdesc_refilled = count;\n+\t\tcount = droq->read_idx;\n+\t\trc = cnxk_ep_rx_refill_mbuf(droq, count);\n+\t\tif (unlikely(rc)) {\n+\t\t\tdroq->stats.rx_alloc_failure++;\n+\t\t\treturn;\n+\t\t}\n+\t\tdesc_refilled += count;\n+\t}\n+\n+\t/* Flush the droq descriptor data to memory to be sure\n+\t * that when we update the credits the data in memory is\n+\t * accurate.\n+\t */\n+\trte_io_wmb();\n+\trte_write32(desc_refilled, droq->pkts_credit_reg);\n+}\n+\n+static inline uint32_t\n+cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)\n+{\n+\tuint32_t new_pkts;\n+\tuint32_t val;\n+\n+\t/* Batch subtractions from the HW counter to reduce PCIe traffic\n+\t * This adds an extra local variable, but almost halves the\n+\t * number of PCIe writes.\n+\t */\n+\tval = rte_atomic_load_explicit(droq->pkts_sent_ism, rte_memory_order_relaxed);\n+\tnew_pkts = val - droq->pkts_sent_ism_prev;\n+\tdroq->pkts_sent_ism_prev = val;\n+\n+\tif (val > (uint32_t)(1 << 31)) {\n+\t\t/* Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write64((uint64_t)val, droq->pkts_sent_reg);\n+\t\trte_mb();\n+\n+\t\trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n+\t\twhile (rte_atomic_load_explicit(droq->pkts_sent_ism, rte_memory_order_relaxed) >=\n+\t\t val) {\n+\t\t\trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n+\t\t\trte_mb();\n+\t\t}\n+\n+\t\tdroq->pkts_sent_ism_prev = 0;\n+\t}\n+\trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n+\tdroq->pkts_pending += new_pkts;\n+\n+\treturn new_pkts;\n+}\n+\n+static inline int16_t __rte_hot\n+cnxk_ep_rx_pkts_to_process(struct otx_ep_droq *droq, uint16_t nb_pkts)\n+{\n+\tif (droq->pkts_pending < nb_pkts)\n+\t\tcnxk_ep_check_rx_pkts(droq);\n+\n+\treturn RTE_MIN(nb_pkts, droq->pkts_pending);\n+}\n+\n+static __rte_always_inline void\n+cnxk_ep_process_pkts_scalar(struct rte_mbuf **rx_pkts, struct otx_ep_droq *droq, uint16_t new_pkts)\n+{\n+\tstruct rte_mbuf **recv_buf_list = droq->recv_buf_list;\n+\tuint32_t bytes_rsvd = 0, read_idx = droq->read_idx;\n+\tuint16_t port_id = droq->otx_ep_dev->port_id;\n+\tuint16_t nb_desc = droq->nb_desc;\n+\tuint16_t pkts;\n+\n+\tfor (pkts = 0; pkts < new_pkts; pkts++) {\n+\t\tstruct otx_ep_droq_info *info;\n+\t\tstruct rte_mbuf *mbuf;\n+\t\tuint16_t pkt_len;\n+\n+\t\tmbuf = recv_buf_list[read_idx];\n+\t\tinfo = rte_pktmbuf_mtod(mbuf, struct otx_ep_droq_info *);\n+\t\tread_idx = otx_ep_incr_index(read_idx, 1, nb_desc);\n+\t\tpkt_len = rte_bswap16(info->length >> 48);\n+\t\tmbuf->data_off += OTX_EP_INFO_SIZE;\n+\t\tmbuf->pkt_len = pkt_len;\n+\t\tmbuf->data_len = pkt_len;\n+\t\tmbuf->port = port_id;\n+\t\trx_pkts[pkts] = mbuf;\n+\t\tbytes_rsvd += pkt_len;\n+\t}\n+\tdroq->read_idx = read_idx;\n+\n+\tdroq->refill_count += new_pkts;\n+\tdroq->pkts_pending -= new_pkts;\n+\t/* Stats */\n+\tdroq->stats.pkts_received += new_pkts;\n+\tdroq->stats.bytes_received += bytes_rsvd;\n+}\n+\n+static __rte_always_inline void\n+cnxk_ep_process_pkts_scalar_mseg(struct rte_mbuf **rx_pkts, struct otx_ep_droq *droq,\n+\t\t\t\t uint16_t new_pkts)\n+{\n+\tstruct rte_mbuf **recv_buf_list = droq->recv_buf_list;\n+\tuint32_t total_pkt_len, bytes_rsvd = 0;\n+\tuint16_t port_id = droq->otx_ep_dev->port_id;\n+\tuint16_t nb_desc = droq->nb_desc;\n+\tuint16_t pkts;\n+\n+\tfor (pkts = 0; pkts < new_pkts; pkts++) {\n+\t\tstruct otx_ep_droq_info *info;\n+\t\tstruct rte_mbuf *first_buf = NULL;\n+\t\tstruct rte_mbuf *last_buf = NULL;\n+\t\tstruct rte_mbuf *mbuf;\n+\t\tuint32_t pkt_len = 0;\n+\n+\t\tmbuf = recv_buf_list[droq->read_idx];\n+\t\tinfo = rte_pktmbuf_mtod(mbuf, struct otx_ep_droq_info *);\n+\n+\t\ttotal_pkt_len = rte_bswap16(info->length >> 48) + OTX_EP_INFO_SIZE;\n+\n+\t\twhile (pkt_len < total_pkt_len) {\n+\t\t\tint cpy_len;\n+\n+\t\t\tcpy_len = ((pkt_len + droq->buffer_size) > total_pkt_len)\n+\t\t\t\t\t? ((uint32_t)total_pkt_len - pkt_len) : droq->buffer_size;\n+\n+\t\t\tmbuf = droq->recv_buf_list[droq->read_idx];\n+\n+\t\t\tif (!pkt_len) {\n+\t\t\t\t/* Note the first seg */\n+\t\t\t\tfirst_buf = mbuf;\n+\t\t\t\tmbuf->data_off += OTX_EP_INFO_SIZE;\n+\t\t\t\tmbuf->pkt_len = cpy_len - OTX_EP_INFO_SIZE;\n+\t\t\t\tmbuf->data_len = cpy_len - OTX_EP_INFO_SIZE;\n+\t\t\t} else {\n+\t\t\t\tmbuf->pkt_len = cpy_len;\n+\t\t\t\tmbuf->data_len = cpy_len;\n+\t\t\t\tfirst_buf->nb_segs++;\n+\t\t\t\tfirst_buf->pkt_len += mbuf->pkt_len;\n+\t\t\t}\n+\n+\t\t\tif (last_buf)\n+\t\t\t\tlast_buf->next = mbuf;\n+\n+\t\t\tlast_buf = mbuf;\n+\n+\t\t\tpkt_len += cpy_len;\n+\t\t\tdroq->read_idx = otx_ep_incr_index(droq->read_idx, 1, nb_desc);\n+\t\t\tdroq->refill_count++;\n+\t\t}\n+\t\tmbuf = first_buf;\n+\t\tmbuf->port = port_id;\n+\t\trx_pkts[pkts] = mbuf;\n+\t\tbytes_rsvd += pkt_len;\n+\t}\n+\n+\tdroq->refill_count += new_pkts;\n+\tdroq->pkts_pending -= pkts;\n+\t/* Stats */\n+\tdroq->stats.pkts_received += pkts;\n+\tdroq->stats.bytes_received += bytes_rsvd;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cnxk_ep_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n+\tuint16_t new_pkts;\n+\n+\tnew_pkts = cnxk_ep_rx_pkts_to_process(droq, nb_pkts);\n+\tcnxk_ep_process_pkts_scalar(rx_pkts, droq, new_pkts);\n+\n+\t/* Refill RX buffers */\n+\tif (droq->refill_count >= DROQ_REFILL_THRESHOLD)\n+\t\tcnxk_ep_rx_refill(droq);\n+\n+\treturn new_pkts;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cn9k_ep_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n+\tuint16_t new_pkts;\n+\n+\tnew_pkts = cnxk_ep_rx_pkts_to_process(droq, nb_pkts);\n+\tcnxk_ep_process_pkts_scalar(rx_pkts, droq, new_pkts);\n+\n+\t/* Refill RX buffers */\n+\tif (droq->refill_count >= DROQ_REFILL_THRESHOLD) {\n+\t\tcnxk_ep_rx_refill(droq);\n+\t} else {\n+\t\t/* SDP output goes into DROP state when output doorbell count\n+\t\t * goes below drop count. When door bell count is written with\n+\t\t * a value greater than drop count SDP output should come out\n+\t\t * of DROP state. Due to a race condition this is not happening.\n+\t\t * Writing doorbell register with 0 again may make SDP output\n+\t\t * come out of this state.\n+\t\t */\n+\n+\t\trte_write32(0, droq->pkts_credit_reg);\n+\t}\n+\n+\treturn new_pkts;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cnxk_ep_recv_pkts_mseg(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n+\tuint16_t new_pkts;\n+\n+\tnew_pkts = cnxk_ep_rx_pkts_to_process(droq, nb_pkts);\n+\tcnxk_ep_process_pkts_scalar_mseg(rx_pkts, droq, new_pkts);\n+\n+\t/* Refill RX buffers */\n+\tif (droq->refill_count >= DROQ_REFILL_THRESHOLD)\n+\t\tcnxk_ep_rx_refill(droq);\n+\n+\treturn new_pkts;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cn9k_ep_recv_pkts_mseg(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n+\tuint16_t new_pkts;\n+\n+\tnew_pkts = cnxk_ep_rx_pkts_to_process(droq, nb_pkts);\n+\tcnxk_ep_process_pkts_scalar_mseg(rx_pkts, droq, new_pkts);\n+\n+\t/* Refill RX buffers */\n+\tif (droq->refill_count >= DROQ_REFILL_THRESHOLD) {\n+\t\tcnxk_ep_rx_refill(droq);\n+\t} else {\n+\t\t/* SDP output goes into DROP state when output doorbell count\n+\t\t * goes below drop count. When door bell count is written with\n+\t\t * a value greater than drop count SDP output should come out\n+\t\t * of DROP state. Due to a race condition this is not happening.\n+\t\t * Writing doorbell register with 0 again may make SDP output\n+\t\t * come out of this state.\n+\t\t */\n+\n+\t\trte_write32(0, droq->pkts_credit_reg);\n+\t}\n+\n+\treturn new_pkts;\n+}\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_tx.c b/drivers/net/octeon_ep/cnxk_ep_tx.c\nnew file mode 100644\nindex 0000000000..86f771ca7e\n--- /dev/null\n+++ b/drivers/net/octeon_ep/cnxk_ep_tx.c\n@@ -0,0 +1,210 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#include \"cnxk_ep_vf.h\"\n+#include \"otx_ep_rxtx.h\"\n+\n+static uint32_t\n+cnxk_vf_update_read_index(struct otx_ep_instr_queue *iq)\n+{\n+\tuint32_t val;\n+\n+\t/* Batch subtractions from the HW counter to reduce PCIe traffic\n+\t * This adds an extra local variable, but almost halves the\n+\t * number of PCIe writes.\n+\t */\n+\tval = rte_atomic_load_explicit(iq->inst_cnt_ism, rte_memory_order_relaxed);\n+\tiq->inst_cnt += val - iq->inst_cnt_ism_prev;\n+\tiq->inst_cnt_ism_prev = val;\n+\n+\tif (val > (uint32_t)(1 << 31)) {\n+\t\t/* Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write64((uint64_t)val, iq->inst_cnt_reg);\n+\t\trte_mb();\n+\n+\t\trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n+\t\twhile (rte_atomic_load_explicit(iq->inst_cnt_ism, rte_memory_order_relaxed) >=\n+\t\t val) {\n+\t\t\trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n+\t\t\trte_mb();\n+\t\t}\n+\n+\t\tiq->inst_cnt_ism_prev = 0;\n+\t}\n+\trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n+\n+\t/* Modulo of the new index with the IQ size will give us\n+\t * the new index.\n+\t */\n+\treturn iq->inst_cnt & (iq->nb_desc - 1);\n+}\n+\n+static inline void\n+cnxk_ep_flush_iq(struct otx_ep_instr_queue *iq)\n+{\n+\tuint32_t instr_processed = 0;\n+\tuint32_t cnt = 0;\n+\n+\tiq->otx_read_index = cnxk_vf_update_read_index(iq);\n+\n+\tif (unlikely(iq->flush_index == iq->otx_read_index))\n+\t\treturn;\n+\n+\tif (iq->flush_index < iq->otx_read_index) {\n+\t\tinstr_processed = iq->otx_read_index - iq->flush_index;\n+\t\trte_pktmbuf_free_bulk(&iq->mbuf_list[iq->flush_index], instr_processed);\n+\t\tiq->flush_index = otx_ep_incr_index(iq->flush_index, instr_processed, iq->nb_desc);\n+\t} else {\n+\t\tcnt = iq->nb_desc - iq->flush_index;\n+\t\trte_pktmbuf_free_bulk(&iq->mbuf_list[iq->flush_index], cnt);\n+\t\tiq->flush_index = otx_ep_incr_index(iq->flush_index, cnt, iq->nb_desc);\n+\n+\t\tinstr_processed = iq->otx_read_index;\n+\t\trte_pktmbuf_free_bulk(&iq->mbuf_list[iq->flush_index], instr_processed);\n+\t\tiq->flush_index = otx_ep_incr_index(iq->flush_index, instr_processed, iq->nb_desc);\n+\n+\t\tinstr_processed += cnt;\n+\t}\n+\n+\tiq->stats.instr_processed = instr_processed;\n+\tiq->instr_pending -= instr_processed;\n+}\n+\n+static inline void\n+set_sg_size(struct otx_ep_sg_entry *sg_entry, uint16_t size, uint32_t pos)\n+{\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\tsg_entry->u.size[pos] = size;\n+#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\tsg_entry->u.size[(OTX_EP_NUM_SG_PTRS - 1) - pos] = size;\n+#endif\n+}\n+\n+static __rte_always_inline void\n+cnxk_ep_xmit_pkts_scalar(struct rte_mbuf **tx_pkts, struct otx_ep_instr_queue *iq, uint16_t nb_pkts)\n+{\n+\tstruct cnxk_ep_instr_32B *iqcmd;\n+\tstruct rte_mbuf *m;\n+\tuint32_t pkt_len;\n+\tuint32_t tx_bytes = 0;\n+\tuint32_t write_idx = iq->host_write_index;\n+\tuint16_t pkts, nb_desc = iq->nb_desc;\n+\tuint8_t desc_size = iq->desc_size;\n+\n+\tfor (pkts = 0; pkts < nb_pkts; pkts++) {\n+\t\tm = tx_pkts[pkts];\n+\t\tiq->mbuf_list[write_idx] = m;\n+\t\tpkt_len = rte_pktmbuf_data_len(m);\n+\n+\t\tiqcmd = (struct cnxk_ep_instr_32B *)(iq->base_addr + (write_idx * desc_size));\n+\t\tiqcmd->ih.u64 = iq->partial_ih | pkt_len;\n+\t\tiqcmd->dptr = rte_mbuf_data_iova(m); /*dptr*/\n+\t\ttx_bytes += pkt_len;\n+\n+\t\t/* Increment the host write index */\n+\t\twrite_idx = otx_ep_incr_index(write_idx, 1, nb_desc);\n+\t}\n+\tiq->host_write_index = write_idx;\n+\n+\t/* ring dbell */\n+\trte_io_wmb();\n+\trte_write64(pkts, iq->doorbell_reg);\n+\tiq->instr_pending += pkts;\n+\tiq->stats.tx_pkts += pkts;\n+\tiq->stats.tx_bytes += tx_bytes;\n+}\n+\n+static __rte_always_inline uint16_t\n+cnxk_ep_xmit_pkts_scalar_mseg(struct rte_mbuf **tx_pkts, struct otx_ep_instr_queue *iq,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t frags, num_sg, mask = OTX_EP_NUM_SG_PTRS - 1;\n+\tstruct otx_ep_buf_free_info *finfo;\n+\tstruct cnxk_ep_instr_32B *iqcmd;\n+\tstruct rte_mbuf *m;\n+\tuint32_t pkt_len, tx_bytes = 0;\n+\tuint32_t write_idx = iq->host_write_index;\n+\tuint16_t pkts, nb_desc = iq->nb_desc;\n+\tuint8_t desc_size = iq->desc_size;\n+\n+\tfor (pkts = 0; pkts < nb_pkts; pkts++) {\n+\t\tuint16_t j = 0;\n+\n+\t\tm = tx_pkts[pkts];\n+\t\tfrags = m->nb_segs;\n+\n+\t\tpkt_len = rte_pktmbuf_pkt_len(m);\n+\t\tnum_sg = (frags + mask) / OTX_EP_NUM_SG_PTRS;\n+\n+\t\tif (unlikely(pkt_len > OTX_EP_MAX_PKT_SZ && num_sg > OTX_EP_MAX_SG_LISTS)) {\n+\t\t\totx_ep_err(\"Failed to xmit the pkt, pkt_len is higher or pkt has more segments\\n\");\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tfinfo = &iq->req_list[write_idx].finfo;\n+\n+\t\tiq->mbuf_list[write_idx] = m;\n+\t\tiqcmd = (struct cnxk_ep_instr_32B *)(iq->base_addr + (write_idx * desc_size));\n+\t\tiqcmd->dptr = rte_mem_virt2iova(finfo->g.sg);\n+\t\tiqcmd->ih.u64 = iq->partial_ih | (1ULL << 62) | ((uint64_t)frags << 48) | pkt_len;\n+\n+\t\twhile (frags--) {\n+\t\t\tfinfo->g.sg[(j >> 2)].ptr[(j & mask)] = rte_mbuf_data_iova(m);\n+\t\t\tset_sg_size(&finfo->g.sg[(j >> 2)], m->data_len, (j & mask));\n+\t\t\tj++;\n+\t\t\tm = m->next;\n+\t\t}\n+\n+\t\t/* Increment the host write index */\n+\t\twrite_idx = otx_ep_incr_index(write_idx, 1, nb_desc);\n+\t\ttx_bytes += pkt_len;\n+\t}\n+exit:\n+\tiq->host_write_index = write_idx;\n+\n+\t/* ring dbell */\n+\trte_io_wmb();\n+\trte_write64(pkts, iq->doorbell_reg);\n+\tiq->instr_pending += pkts;\n+\tiq->stats.tx_pkts += pkts;\n+\tiq->stats.tx_bytes += tx_bytes;\n+\n+\treturn pkts;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cnxk_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_instr_queue *iq = (struct otx_ep_instr_queue *)tx_queue;\n+\tuint16_t pkts;\n+\n+\tpkts = RTE_MIN(nb_pkts, iq->nb_desc - iq->instr_pending);\n+\n+\tcnxk_ep_xmit_pkts_scalar(tx_pkts, iq, pkts);\n+\n+\tif (iq->instr_pending >= OTX_EP_MAX_INSTR)\n+\t\tcnxk_ep_flush_iq(iq);\n+\n+\t/* Return no# of instructions posted successfully. */\n+\treturn pkts;\n+}\n+\n+uint16_t __rte_noinline __rte_hot\n+cnxk_ep_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct otx_ep_instr_queue *iq = (struct otx_ep_instr_queue *)tx_queue;\n+\tuint16_t pkts;\n+\n+\tpkts = RTE_MIN(nb_pkts, iq->nb_desc - iq->instr_pending);\n+\n+\tpkts = cnxk_ep_xmit_pkts_scalar_mseg(tx_pkts, iq, pkts);\n+\n+\tif (iq->instr_pending >= OTX_EP_MAX_INSTR)\n+\t\tcnxk_ep_flush_iq(iq);\n+\n+\t/* Return no# of instructions posted successfully. */\n+\treturn pkts;\n+}\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex 7b3669fe0c..ef275703c3 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -156,6 +156,8 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t (void *)iq->inst_cnt_ism, ism_addr);\n \t*iq->inst_cnt_ism = 0;\n \tiq->inst_cnt_ism_prev = 0;\n+\tiq->partial_ih = ((uint64_t)otx_ep->pkind) << 36;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h b/drivers/net/octeon_ep/cnxk_ep_vf.h\nindex 86277449ea..41d8fbbb3a 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.h\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.h\n@@ -6,6 +6,8 @@\n \n #include <rte_io.h>\n \n+#include \"otx_ep_common.h\"\n+\n #define CNXK_CONFIG_XPANSION_BAR 0x38\n #define CNXK_CONFIG_PCIE_CAP 0x70\n #define CNXK_CONFIG_PCIE_DEVCAP 0x74\n@@ -178,6 +180,17 @@ struct cnxk_ep_instr_64B {\n \tuint64_t exhdr[4];\n };\n \n+struct cnxk_ep_instr_32B {\n+\t/* Pointer where the input data is available. */\n+\tuint64_t dptr;\n+\n+\t/* OTX_EP Instruction Header. */\n+\tunion otx_ep_instr_ih ih;\n+\n+\t/* Misc data bytes that can be passed as front data */\n+\tuint64_t rsvd[2];\n+};\n+\n #define CNXK_EP_IQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue) + 4)\n #define CNXK_EP_OQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue))\n #define CNXK_EP_ISM_EN (0x1)\ndiff --git a/drivers/net/octeon_ep/meson.build b/drivers/net/octeon_ep/meson.build\nindex e698bf9792..749776d70c 100644\n--- a/drivers/net/octeon_ep/meson.build\n+++ b/drivers/net/octeon_ep/meson.build\n@@ -9,4 +9,6 @@ sources = files(\n 'otx2_ep_vf.c',\n 'cnxk_ep_vf.c',\n 'otx_ep_mbox.c',\n+ 'cnxk_ep_rx.c',\n+ 'cnxk_ep_tx.c',\n )\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex f72b8d25d7..7f4edf8dcf 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -307,6 +307,7 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t (unsigned int)ism_addr);\n \t*iq->inst_cnt_ism = 0;\n \tiq->inst_cnt_ism_prev = 0;\n+\tiq->partial_ih = ((uint64_t)otx_ep->pkind) << 36;\n \n \treturn 0;\n }\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex 90e059cad0..82e57520d3 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -4,7 +4,20 @@\n #ifndef _OTX_EP_COMMON_H_\n #define _OTX_EP_COMMON_H_\n \n+#include <rte_bitops.h>\n #include <rte_spinlock.h>\n+#include <unistd.h>\n+#include <assert.h>\n+#include <rte_eal.h>\n+#include <rte_mempool.h>\n+#include <rte_mbuf.h>\n+#include <rte_io.h>\n+#include <rte_net.h>\n+#include <ethdev_pci.h>\n+\n+#define OTX_EP_CN8XX RTE_BIT32(0)\n+#define OTX_EP_CN9XX RTE_BIT32(1)\n+#define OTX_EP_CN10XX RTE_BIT32(2)\n \n #define OTX_EP_NW_PKT_OP 0x1220\n #define OTX_EP_NW_CMD_OP 0x1221\n@@ -38,7 +51,7 @@\n #define OTX_EP_NORESP_OHSM_SEND (4)\n #define OTX_EP_NORESP_LAST (4)\n #define OTX_EP_PCI_RING_ALIGN 65536\n-#define OTX_EP_MAX_SG_LISTS 4\n+#define OTX_EP_MAX_SG_LISTS 6\n #define OTX_EP_NUM_SG_PTRS 4\n #define SDP_PKIND 40\n #define SDP_OTX2_PKIND 57\n@@ -203,6 +216,38 @@ struct otx_ep_iq_config {\n * such structure to represent it.\n */\n struct otx_ep_instr_queue {\n+\t/* Location in memory updated by SDP ISM */\n+\tuint32_t *inst_cnt_ism;\n+\tstruct rte_mbuf **mbuf_list;\n+\t/* Pointer to the Virtual Base addr of the input ring. */\n+\tuint8_t *base_addr;\n+\n+\t/* track inst count locally to consolidate HW counter updates */\n+\tuint32_t inst_cnt_ism_prev;\n+\n+\t/* Input ring index, where the driver should write the next packet */\n+\tuint32_t host_write_index;\n+\n+\t/* Input ring index, where the OCTEON 9 should read the next packet */\n+\tuint32_t otx_read_index;\n+\t/** This index aids in finding the window in the queue where OCTEON 9\n+\t * has read the commands.\n+\t */\n+\tuint32_t flush_index;\n+\t/* This keeps track of the instructions pending in this queue. */\n+\tuint64_t instr_pending;\n+\n+\t/* Memory zone */\n+\tconst struct rte_memzone *iq_mz;\n+\t/* OTX_EP doorbell register for the ring. */\n+\tvoid *doorbell_reg;\n+\n+\t/* OTX_EP instruction count register for this ring. */\n+\tvoid *inst_cnt_reg;\n+\n+\t/* Number of instructions pending to be posted to OCTEON 9. */\n+\tuint32_t fill_cnt;\n+\n \tstruct otx_ep_device *otx_ep_dev;\n \n \tuint32_t q_no;\n@@ -219,54 +264,21 @@ struct otx_ep_instr_queue {\n \t/* Size of the descriptor. */\n \tuint8_t desc_size;\n \n-\t/* Input ring index, where the driver should write the next packet */\n-\tuint32_t host_write_index;\n-\n-\t/* Input ring index, where the OCTEON 9 should read the next packet */\n-\tuint32_t otx_read_index;\n-\n \tuint32_t reset_instr_cnt;\n \n-\t/** This index aids in finding the window in the queue where OCTEON 9\n-\t * has read the commands.\n-\t */\n-\tuint32_t flush_index;\n-\n \t/* Free-running/wrapping instruction counter for IQ. */\n \tuint32_t inst_cnt;\n \n-\t/* This keeps track of the instructions pending in this queue. */\n-\tuint64_t instr_pending;\n-\n-\t/* Pointer to the Virtual Base addr of the input ring. */\n-\tuint8_t *base_addr;\n+\tuint64_t partial_ih;\n \n \t/* This IQ request list */\n \tstruct otx_ep_instr_list *req_list;\n \n-\t/* OTX_EP doorbell register for the ring. */\n-\tvoid *doorbell_reg;\n-\n-\t/* OTX_EP instruction count register for this ring. */\n-\tvoid *inst_cnt_reg;\n-\n-\t/* Number of instructions pending to be posted to OCTEON 9. */\n-\tuint32_t fill_cnt;\n-\n \t/* Statistics for this input queue. */\n \tstruct otx_ep_iq_stats stats;\n \n \t/* DMA mapped base address of the input descriptor ring. */\n \tuint64_t base_addr_dma;\n-\n-\t/* Memory zone */\n-\tconst struct rte_memzone *iq_mz;\n-\n-\t/* Location in memory updated by SDP ISM */\n-\tuint32_t *inst_cnt_ism;\n-\n-\t/* track inst count locally to consolidate HW counter updates */\n-\tuint32_t inst_cnt_ism_prev;\n };\n \n /** Descriptor format.\n@@ -344,14 +356,17 @@ struct otx_ep_oq_config {\n \n /* The Descriptor Ring Output Queue(DROQ) structure. */\n struct otx_ep_droq {\n-\tstruct otx_ep_device *otx_ep_dev;\n \t/* The 8B aligned descriptor ring starts at this address. */\n \tstruct otx_ep_droq_desc *desc_ring;\n \n-\tuint32_t q_no;\n-\tuint64_t last_pkt_count;\n+\t/* The 8B aligned info ptrs begin from this address. */\n+\tstruct otx_ep_droq_info *info_list;\n \n-\tstruct rte_mempool *mpool;\n+\t/* receive buffer list contains mbuf ptr list */\n+\tstruct rte_mbuf **recv_buf_list;\n+\n+\t/* Packets pending to be processed */\n+\tuint64_t pkts_pending;\n \n \t/* Driver should read the next packet at this index */\n \tuint32_t read_idx;\n@@ -362,22 +377,17 @@ struct otx_ep_droq {\n \t/* At this index, the driver will refill the descriptor's buffer */\n \tuint32_t refill_idx;\n \n-\t/* Packets pending to be processed */\n-\tuint64_t pkts_pending;\n+\t/* The number of descriptors pending to refill. */\n+\tuint32_t refill_count;\n \n \t/* Number of descriptors in this ring. */\n \tuint32_t nb_desc;\n \n-\t/* The number of descriptors pending to refill. */\n-\tuint32_t refill_count;\n-\n \tuint32_t refill_threshold;\n \n-\t/* The 8B aligned info ptrs begin from this address. */\n-\tstruct otx_ep_droq_info *info_list;\n+\tuint64_t last_pkt_count;\n \n-\t/* receive buffer list contains mbuf ptr list */\n-\tstruct rte_mbuf **recv_buf_list;\n+\tstruct rte_mempool *mpool;\n \n \t/* The size of each buffer pointed by the buffer pointer. */\n \tuint32_t buffer_size;\n@@ -392,6 +402,13 @@ struct otx_ep_droq {\n \t */\n \tvoid *pkts_sent_reg;\n \n+\t/* Pointer to host memory copy of output packet count, set by ISM */\n+\tuint32_t *pkts_sent_ism;\n+\tuint32_t pkts_sent_ism_prev;\n+\n+\t/* Statistics for this DROQ. */\n+\tstruct otx_ep_droq_stats stats;\n+\n \t/** Handle DMA incompletion during pkt reads.\n \t * This variable is used to initiate a sent_reg_read\n \t * that completes pending dma\n@@ -400,8 +417,9 @@ struct otx_ep_droq {\n \t */\n \tuint32_t sent_reg_val;\n \n-\t/* Statistics for this DROQ. */\n-\tstruct otx_ep_droq_stats stats;\n+\tuint32_t q_no;\n+\n+\tstruct otx_ep_device *otx_ep_dev;\n \n \t/* DMA mapped address of the DROQ descriptor ring. */\n \tsize_t desc_ring_dma;\n@@ -419,10 +437,6 @@ struct otx_ep_droq {\n \tconst struct rte_memzone *desc_ring_mz;\n \n \tconst struct rte_memzone *info_mz;\n-\n-\t/* Pointer to host memory copy of output packet count, set by ISM */\n-\tuint32_t *pkts_sent_ism;\n-\tuint32_t pkts_sent_ism_prev;\n };\n #define OTX_EP_DROQ_SIZE\t\t(sizeof(struct otx_ep_droq))\n \n@@ -545,6 +559,9 @@ struct otx_ep_device {\n \n \t/* Negotiated Mbox version */\n \tuint32_t mbox_neg_ver;\n+\n+\t/* Generation */\n+\tuint32_t chip_gen;\n };\n \n int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,\ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex 970372bbd7..615cbbb648 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -27,6 +27,46 @@ static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {\n \t.nb_align\t= OTX_EP_TXD_ALIGN,\n };\n \n+static void\n+otx_ep_set_tx_func(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\n+\tif (otx_epvf->chip_gen == OTX_EP_CN10XX || otx_epvf->chip_gen == OTX_EP_CN9XX) {\n+\t\teth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts;\n+\t\tif (otx_epvf->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n+\t\t\teth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts_mseg;\n+\t} else {\n+\t\teth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;\n+\t}\n+\n+\tif (eth_dev->data->dev_started)\n+\t\trte_eth_fp_ops[eth_dev->data->port_id].tx_pkt_burst =\n+\t\t\teth_dev->tx_pkt_burst;\n+}\n+\n+static void\n+otx_ep_set_rx_func(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\n+\tif (otx_epvf->chip_gen == OTX_EP_CN10XX) {\n+\t\teth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts;\n+\t\tif (otx_epvf->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)\n+\t\t\teth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts_mseg;\n+\t} else if (otx_epvf->chip_gen == OTX_EP_CN9XX) {\n+\t\teth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts;\n+\t\tif (otx_epvf->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)\n+\t\t\teth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts_mseg;\n+\t} else {\n+\t\teth_dev->rx_pkt_burst = &otx_ep_recv_pkts;\n+\t}\n+\n+\tif (eth_dev->data->dev_started)\n+\t\trte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst =\n+\t\t\teth_dev->rx_pkt_burst;\n+}\n+\n static int\n otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_dev_info *devinfo)\n@@ -154,6 +194,10 @@ otx_ep_dev_start(struct rte_eth_dev *eth_dev)\n \t}\n \n \totx_ep_dev_link_update(eth_dev, 0);\n+\n+\totx_ep_set_tx_func(eth_dev);\n+\totx_ep_set_rx_func(eth_dev);\n+\n \totx_ep_info(\"dev started\\n\");\n \n \tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++)\n@@ -266,18 +310,23 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \n \totx_epvf->fn_list.setup_device_regs(otx_epvf);\n \n+\totx_epvf->eth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts;\n \totx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts;\n-\tif (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)\n+\tif (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) {\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;\n-\telse if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n+\t\totx_epvf->chip_gen = OTX_EP_CN8XX;\n+\t} else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {\n-\t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) {\n+\t\totx_epvf->eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts;\n+\t\totx_epvf->chip_gen = OTX_EP_CN9XX;\n+\t} else if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {\n+\t\totx_epvf->eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts;\n+\t\totx_epvf->chip_gen = OTX_EP_CN10XX;\n \t} else {\n \t\totx_ep_err(\"Invalid chip_id\\n\");\n \t\tret = -EINVAL;\n@@ -667,8 +716,8 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t/* Single process support */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n \t\teth_dev->dev_ops = &otx_ep_eth_dev_ops;\n-\t\teth_dev->rx_pkt_burst = &otx_ep_recv_pkts;\n-\t\teth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n+\t\totx_ep_set_tx_func(eth_dev);\n+\t\totx_ep_set_rx_func(eth_dev);\n \t\treturn 0;\n \t}\n \ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c\nindex 2654e13e18..f53f0578ef 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c\n@@ -13,15 +13,8 @@\n \n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n-#include \"otx2_ep_vf.h\"\n #include \"otx_ep_rxtx.h\"\n \n-/* SDP_LENGTH_S specifies packet length and is of 8-byte size */\n-#define OTX_EP_INFO_SIZE 8\n-#define OTX_EP_FSZ_FS0 0\n-#define DROQ_REFILL_THRESHOLD 16\n-#define OTX2_SDP_REQUEST_ISM (0x1ULL << 63)\n-\n static void\n otx_ep_dmazone_free(const struct rte_memzone *mz)\n {\n@@ -144,6 +137,13 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \t\t iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,\n \t\t iq->nb_desc);\n \n+\tiq->mbuf_list = rte_zmalloc_socket(\"mbuf_list\",\t(iq->nb_desc * sizeof(struct rte_mbuf *)),\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n+\tif (!iq->mbuf_list) {\n+\t\totx_ep_err(\"IQ[%d] mbuf_list alloc failed\\n\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n \tiq->otx_ep_dev = otx_ep;\n \tiq->q_no = iq_no;\n \tiq->fill_cnt = 0;\n@@ -676,85 +676,6 @@ otx_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts)\n \treturn count;\n }\n \n-/* Enqueue requests/packets to OTX_EP IQ queue.\n- * returns number of requests enqueued successfully\n- */\n-uint16_t\n-otx2_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts)\n-{\n-\tstruct otx_ep_instr_queue *iq = (struct otx_ep_instr_queue *)tx_queue;\n-\tstruct otx_ep_device *otx_ep = iq->otx_ep_dev;\n-\tstruct otx2_ep_instr_64B iqcmd2;\n-\tuint32_t iqreq_type;\n-\tstruct rte_mbuf *m;\n-\tuint32_t pkt_len;\n-\tint count = 0;\n-\tuint16_t i;\n-\tint dbell;\n-\tint index;\n-\n-\tiqcmd2.ih.u64 = 0;\n-\tiqcmd2.irh.u64 = 0;\n-\n-\t/* ih invars */\n-\tiqcmd2.ih.s.fsz = OTX_EP_FSZ_FS0;\n-\tiqcmd2.ih.s.pkind = otx_ep->pkind; /* The SDK decided PKIND value */\n-\t/* irh invars */\n-\tiqcmd2.irh.s.opcode = OTX_EP_NW_PKT_OP;\n-\n-\tfor (i = 0; i < nb_pkts; i++) {\n-\t\tm = pkts[i];\n-\t\tif (m->nb_segs == 1) {\n-\t\t\tpkt_len = rte_pktmbuf_data_len(m);\n-\t\t\tiqcmd2.ih.s.tlen = pkt_len + iqcmd2.ih.s.fsz;\n-\t\t\tiqcmd2.dptr = rte_mbuf_data_iova(m); /*dptr*/\n-\t\t\tiqcmd2.ih.s.gather = 0;\n-\t\t\tiqcmd2.ih.s.gsz = 0;\n-\t\t\tiqreq_type = OTX_EP_REQTYPE_NORESP_NET;\n-\t\t} else {\n-\t\t\tif (!(otx_ep->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS))\n-\t\t\t\tgoto xmit_fail;\n-\n-\t\t\tif (unlikely(prepare_xmit_gather_list(iq, m, &iqcmd2.dptr, &iqcmd2.ih) < 0))\n-\t\t\t\tgoto xmit_fail;\n-\n-\t\t\tpkt_len = rte_pktmbuf_pkt_len(m);\n-\t\t\tiqreq_type = OTX_EP_REQTYPE_NORESP_GATHER;\n-\t\t}\n-\n-\t\tiqcmd2.irh.u64 = rte_bswap64(iqcmd2.irh.u64);\n-\n-#ifdef OTX_EP_IO_DEBUG\n-\t\totx_ep_dbg(\"After swapping\\n\");\n-\t\totx_ep_dbg(\"Word0 [dptr]: 0x%016lx\\n\",\n-\t\t\t (unsigned long)iqcmd.dptr);\n-\t\totx_ep_dbg(\"Word1 [ihtx]: 0x%016lx\\n\", (unsigned long)iqcmd.ih);\n-\t\totx_ep_dbg(\"Word2 [pki_ih3]: 0x%016lx\\n\",\n-\t\t\t (unsigned long)iqcmd.pki_ih3);\n-\t\totx_ep_dbg(\"Word3 [rptr]: 0x%016lx\\n\",\n-\t\t\t (unsigned long)iqcmd.rptr);\n-\t\totx_ep_dbg(\"Word4 [irh]: 0x%016lx\\n\", (unsigned long)iqcmd.irh);\n-\t\totx_ep_dbg(\"Word5 [exhdr[0]]: 0x%016lx\\n\",\n-\t\t\t (unsigned long)iqcmd.exhdr[0]);\n-#endif\n-\t\tindex = iq->host_write_index;\n-\t\tdbell = (i == (unsigned int)(nb_pkts - 1)) ? 1 : 0;\n-\t\tif (otx_ep_send_data(otx_ep, iq, &iqcmd2, dbell))\n-\t\t\tgoto xmit_fail;\n-\t\totx_ep_iqreq_add(iq, m, iqreq_type, index);\n-\t\tiq->stats.tx_pkts++;\n-\t\tiq->stats.tx_bytes += pkt_len;\n-\t\tcount++;\n-\t}\n-\n-xmit_fail:\n-\tif (iq->instr_pending >= OTX_EP_MAX_INSTR)\n-\t\totx_ep_flush_iq(iq);\n-\n-\t/* Return no# of instructions posted successfully. */\n-\treturn count;\n-}\n-\n static uint32_t\n otx_ep_droq_refill(struct otx_ep_droq *droq)\n {\ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.h b/drivers/net/octeon_ep/otx_ep_rxtx.h\nindex 3f12527004..cb68ef3b41 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.h\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.h\n@@ -7,29 +7,53 @@\n \n #include <rte_byteorder.h>\n \n-#define OTX_EP_RXD_ALIGN 2\n-#define OTX_EP_TXD_ALIGN 2\n+#define OTX_EP_RXD_ALIGN 8\n+#define OTX_EP_TXD_ALIGN 8\n \n #define OTX_EP_IQ_SEND_FAILED (-1)\n #define OTX_EP_IQ_SEND_SUCCESS (0)\n \n-#define OTX_EP_MAX_DELAYED_PKT_RETRIES 10000\n+#define OTX_EP_MAX_DELAYED_PKT_RETRIES 10\n \n #define OTX_EP_FSZ 28\n #define OTX2_EP_FSZ 24\n-#define OTX_EP_MAX_INSTR 16\n+#define OTX_EP_MAX_INSTR 128\n+\n+/* SDP_LENGTH_S specifies packet length and is of 8-byte size */\n+#define OTX_EP_INFO_SIZE 8\n+#define DROQ_REFILL_THRESHOLD 16\n+#define OTX2_SDP_REQUEST_ISM (0x1ULL << 63)\n \n static inline uint32_t\n otx_ep_incr_index(uint32_t index, uint32_t count, uint32_t max)\n {\n \treturn ((index + count) & (max - 1));\n }\n+\n uint16_t\n otx_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts);\n+\n uint16_t\n otx2_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts);\n+\n+uint16_t\n+otx_ep_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t budget);\n+\n+uint16_t\n+cnxk_ep_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts);\n+\n+uint16_t\n+cnxk_ep_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts);\n+\n+uint16_t\n+cnxk_ep_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t budget);\n+\n+uint16_t\n+cnxk_ep_recv_pkts_mseg(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t budget);\n+\n+uint16_t\n+cn9k_ep_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t budget);\n+\n uint16_t\n-otx_ep_recv_pkts(void *rx_queue,\n-\t\t struct rte_mbuf **rx_pkts,\n-\t\t uint16_t budget);\n+cn9k_ep_recv_pkts_mseg(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t budget);\n #endif /* _OTX_EP_RXTX_H_ */\n", "prefixes": [ "v5", "3/3" ] }