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GET /api/patches/132775/?format=api
{ "id": 132775, "url": "http://patches.dpdk.org/api/patches/132775/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231017165951.27299-7-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231017165951.27299-7-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231017165951.27299-7-syalavarthi@marvell.com", "date": "2023-10-17T16:59:19", "name": "[v4,06/34] ml/cnxk: rename cnxk ops function pointers struct", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a201d80aca18e5f4639717a7b0ed34edcd9779ac", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231017165951.27299-7-syalavarthi@marvell.com/mbox/", "series": [ { "id": 29890, "url": "http://patches.dpdk.org/api/series/29890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29890", "date": "2023-10-17T16:59:13", "name": "Implementation of revised ml/cnxk driver", "version": 4, "mbox": "http://patches.dpdk.org/series/29890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132775/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/132775/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3C7B74318E;\n\tTue, 17 Oct 2023 19:01:24 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7F0B742E23;\n\tTue, 17 Oct 2023 19:00:19 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 49DD942DDE\n for <dev@dpdk.org>; Tue, 17 Oct 2023 19:00:11 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39HCUCbJ018496 for <dev@dpdk.org>; Tue, 17 Oct 2023 10:00:10 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3tstb3s9ky-6\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 17 Oct 2023 10:00:10 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 17 Oct 2023 10:00:05 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 17 Oct 2023 10:00:05 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 9A6025B695E;\n Tue, 17 Oct 2023 10:00:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=KSmmnHzzm0dBSt+g/CbA2Pfb7Rf1gsE2CHNhrUReXxk=;\n b=evid+Cy4DtITEdijtx648/KbvSMITOCRMiaQ+fQ1uSjyrVz3fm633ks1osqPZIAXYPIU\n z8WbZYmhBCS8BGYx3MEZ99GBb8IwveRGojUqWxD143DDKyc1UEkrEvqEzF9POTHEe8r6\n bJhTi4t/GxaTazbHX8+jQSRKHXugew46RkyZY1mcME3GzfDCBQz1/jsK9nHYg7aTiCLt\n JQsEP+dJsHHgzyp3FuT8dCRaLmKChyrtR/nwsTQ6xl5vqvf3U9DTU6rKPi+p2sr4FfBW\n SlG/bqbjvp0siYyrQw0wohcsAwzYJ7QASyjDaEqTdIypOwh16qQB6qnw+Xx4sQnNZ0iz Tg==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <aprabhu@marvell.com>,\n <ptakkar@marvell.com>", "Subject": "[PATCH v4 06/34] ml/cnxk: rename cnxk ops function pointers struct", "Date": "Tue, 17 Oct 2023 09:59:19 -0700", "Message-ID": "<20231017165951.27299-7-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20231017165951.27299-1-syalavarthi@marvell.com>", "References": "<20230830155927.3566-1-syalavarthi@marvell.com>\n <20231017165951.27299-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "AqAOrKSgVin3lYvaRo5Mi5vMvBTEyILG", "X-Proofpoint-GUID": "AqAOrKSgVin3lYvaRo5Mi5vMvBTEyILG", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-17_03,2023-10-17_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Renamed cn10k ML ops structure with cnxk prefix.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 2 +-\n drivers/ml/cnxk/cn10k_ml_ops.c | 73 +++++++++-------------------------\n drivers/ml/cnxk/cn10k_ml_ops.h | 34 +++++++++++++++-\n drivers/ml/cnxk/cnxk_ml_ops.c | 36 +++++++++++++++++\n drivers/ml/cnxk/cnxk_ml_ops.h | 2 +\n 5 files changed, 91 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex fc6f78d414..91813e9d0a 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -345,7 +345,7 @@ cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_de\n \t\t\tgoto pmd_destroy;\n \t\t}\n \n-\t\tdev->dev_ops = &cn10k_ml_ops;\n+\t\tdev->dev_ops = &cnxk_ml_ops;\n \t} else {\n \t\tplt_err(\"CN10K ML Ops are not supported on secondary process\");\n \t\tdev->dev_ops = &ml_dev_dummy_ops;\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 42a4389bbe..66b38fc1eb 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -119,7 +119,7 @@ cnxk_ml_qp_destroy(const struct rte_ml_dev *dev, struct cnxk_ml_qp *qp)\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_queue_pair_release(struct rte_ml_dev *dev, uint16_t queue_pair_id)\n {\n \tstruct cnxk_ml_qp *qp;\n@@ -860,7 +860,7 @@ cn10k_ml_cache_model_data(struct rte_ml_dev *dev, uint16_t model_id)\n \treturn ret;\n }\n \n-static int\n+int\n cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -888,7 +888,7 @@ cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf)\n {\n \tstruct rte_ml_dev_info dev_info;\n@@ -1087,7 +1087,7 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \treturn ret;\n }\n \n-static int\n+int\n cn10k_ml_dev_close(struct rte_ml_dev *dev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -1160,7 +1160,7 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev)\n \treturn rte_dev_remove(dev->device);\n }\n \n-static int\n+int\n cn10k_ml_dev_start(struct rte_ml_dev *dev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -1180,7 +1180,7 @@ cn10k_ml_dev_start(struct rte_ml_dev *dev)\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_stop(struct rte_ml_dev *dev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -1200,7 +1200,7 @@ cn10k_ml_dev_stop(struct rte_ml_dev *dev)\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n \t\t\t const struct rte_ml_dev_qp_conf *qp_conf, int socket_id)\n {\n@@ -1241,7 +1241,7 @@ cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_stats_get(struct rte_ml_dev *dev, struct rte_ml_dev_stats *stats)\n {\n \tstruct cnxk_ml_qp *qp;\n@@ -1258,7 +1258,7 @@ cn10k_ml_dev_stats_get(struct rte_ml_dev *dev, struct rte_ml_dev_stats *stats)\n \treturn 0;\n }\n \n-static void\n+void\n cn10k_ml_dev_stats_reset(struct rte_ml_dev *dev)\n {\n \tstruct cnxk_ml_qp *qp;\n@@ -1273,7 +1273,7 @@ cn10k_ml_dev_stats_reset(struct rte_ml_dev *dev)\n \t}\n }\n \n-static int\n+int\n cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode,\n \t\t\t int32_t model_id, struct rte_ml_dev_xstats_map *xstats_map,\n \t\t\t uint32_t size)\n@@ -1321,7 +1321,7 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mod\n \treturn idx;\n }\n \n-static int\n+int\n cn10k_ml_dev_xstats_by_name_get(struct rte_ml_dev *dev, const char *name, uint16_t *stat_id,\n \t\t\t\tuint64_t *value)\n {\n@@ -1363,7 +1363,7 @@ cn10k_ml_dev_xstats_by_name_get(struct rte_ml_dev *dev, const char *name, uint16\n \treturn -EINVAL;\n }\n \n-static int\n+int\n cn10k_ml_dev_xstats_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode, int32_t model_id,\n \t\t\tconst uint16_t stat_ids[], uint64_t values[], uint16_t nb_ids)\n {\n@@ -1427,7 +1427,7 @@ cn10k_ml_dev_xstats_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode\n \treturn idx;\n }\n \n-static int\n+int\n cn10k_ml_dev_xstats_reset(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode,\n \t\t\t int32_t model_id, const uint16_t stat_ids[], uint16_t nb_ids)\n {\n@@ -1441,7 +1441,7 @@ cn10k_ml_dev_xstats_reset(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mo\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -1528,7 +1528,7 @@ cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp)\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_dev_selftest(struct rte_ml_dev *dev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n@@ -2051,7 +2051,7 @@ cn10k_ml_model_stop(struct rte_ml_dev *dev, uint16_t model_id)\n \treturn ret;\n }\n \n-static int\n+int\n cn10k_ml_model_info_get(struct rte_ml_dev *dev, uint16_t model_id,\n \t\t\tstruct rte_ml_model_info *model_info)\n {\n@@ -2071,7 +2071,7 @@ cn10k_ml_model_info_get(struct rte_ml_dev *dev, uint16_t model_id,\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_model_params_update(struct rte_ml_dev *dev, uint16_t model_id, void *buffer)\n {\n \tstruct cnxk_ml_model *model;\n@@ -2105,7 +2105,7 @@ cn10k_ml_model_params_update(struct rte_ml_dev *dev, uint16_t model_id, void *bu\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_io_quantize(struct rte_ml_dev *dev, uint16_t model_id, struct rte_ml_buff_seg **dbuffer,\n \t\t struct rte_ml_buff_seg **qbuffer)\n {\n@@ -2186,7 +2186,7 @@ cn10k_ml_io_quantize(struct rte_ml_dev *dev, uint16_t model_id, struct rte_ml_bu\n \treturn 0;\n }\n \n-static int\n+int\n cn10k_ml_io_dequantize(struct rte_ml_dev *dev, uint16_t model_id, struct rte_ml_buff_seg **qbuffer,\n \t\t struct rte_ml_buff_seg **dbuffer)\n {\n@@ -2574,38 +2574,3 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n error_enqueue:\n \treturn ret;\n }\n-\n-struct rte_ml_dev_ops cn10k_ml_ops = {\n-\t/* Device control ops */\n-\t.dev_info_get = cn10k_ml_dev_info_get,\n-\t.dev_configure = cn10k_ml_dev_configure,\n-\t.dev_close = cn10k_ml_dev_close,\n-\t.dev_start = cn10k_ml_dev_start,\n-\t.dev_stop = cn10k_ml_dev_stop,\n-\t.dev_dump = cn10k_ml_dev_dump,\n-\t.dev_selftest = cn10k_ml_dev_selftest,\n-\n-\t/* Queue-pair handling ops */\n-\t.dev_queue_pair_setup = cn10k_ml_dev_queue_pair_setup,\n-\t.dev_queue_pair_release = cn10k_ml_dev_queue_pair_release,\n-\n-\t/* Stats ops */\n-\t.dev_stats_get = cn10k_ml_dev_stats_get,\n-\t.dev_stats_reset = cn10k_ml_dev_stats_reset,\n-\t.dev_xstats_names_get = cn10k_ml_dev_xstats_names_get,\n-\t.dev_xstats_by_name_get = cn10k_ml_dev_xstats_by_name_get,\n-\t.dev_xstats_get = cn10k_ml_dev_xstats_get,\n-\t.dev_xstats_reset = cn10k_ml_dev_xstats_reset,\n-\n-\t/* Model ops */\n-\t.model_load = cn10k_ml_model_load,\n-\t.model_unload = cn10k_ml_model_unload,\n-\t.model_start = cn10k_ml_model_start,\n-\t.model_stop = cn10k_ml_model_stop,\n-\t.model_info_get = cn10k_ml_model_info_get,\n-\t.model_params_update = cn10k_ml_model_params_update,\n-\n-\t/* I/O ops */\n-\t.io_quantize = cn10k_ml_io_quantize,\n-\t.io_dequantize = cn10k_ml_io_dequantize,\n-};\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex fd5992e192..16480b9ad8 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -286,7 +286,29 @@ struct cn10k_ml_req {\n };\n \n /* Device ops */\n-extern struct rte_ml_dev_ops cn10k_ml_ops;\n+int cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info);\n+int cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf);\n+int cn10k_ml_dev_close(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_start(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_stop(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp);\n+int cn10k_ml_dev_selftest(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n+\t\t\t\t const struct rte_ml_dev_qp_conf *qp_conf, int socket_id);\n+int cn10k_ml_dev_queue_pair_release(struct rte_ml_dev *dev, uint16_t queue_pair_id);\n+\n+int cn10k_ml_dev_stats_get(struct rte_ml_dev *dev, struct rte_ml_dev_stats *stats);\n+void cn10k_ml_dev_stats_reset(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode,\n+\t\t\t\t int32_t model_id, struct rte_ml_dev_xstats_map *xstats_map,\n+\t\t\t\t uint32_t size);\n+int cn10k_ml_dev_xstats_by_name_get(struct rte_ml_dev *dev, const char *name, uint16_t *stat_id,\n+\t\t\t\t uint64_t *value);\n+int cn10k_ml_dev_xstats_get(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode,\n+\t\t\t int32_t model_id, const uint16_t stat_ids[], uint64_t values[],\n+\t\t\t uint16_t nb_ids);\n+int cn10k_ml_dev_xstats_reset(struct rte_ml_dev *dev, enum rte_ml_dev_xstats_mode mode,\n+\t\t\t int32_t model_id, const uint16_t stat_ids[], uint16_t nb_ids);\n \n /* Slow-path ops */\n int cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n@@ -294,6 +316,16 @@ int cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *para\n int cn10k_ml_model_unload(struct rte_ml_dev *dev, uint16_t model_id);\n int cn10k_ml_model_start(struct rte_ml_dev *dev, uint16_t model_id);\n int cn10k_ml_model_stop(struct rte_ml_dev *dev, uint16_t model_id);\n+int cn10k_ml_model_info_get(struct rte_ml_dev *dev, uint16_t model_id,\n+\t\t\t struct rte_ml_model_info *model_info);\n+int cn10k_ml_model_params_update(struct rte_ml_dev *dev, uint16_t model_id, void *buffer);\n+\n+/* I/O ops */\n+int cn10k_ml_io_quantize(struct rte_ml_dev *dev, uint16_t model_id,\n+\t\t\t struct rte_ml_buff_seg **dbuffer, struct rte_ml_buff_seg **qbuffer);\n+\n+int cn10k_ml_io_dequantize(struct rte_ml_dev *dev, uint16_t model_id,\n+\t\t\t struct rte_ml_buff_seg **qbuffer, struct rte_ml_buff_seg **dbuffer);\n \n /* Fast-path ops */\n __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id,\ndiff --git a/drivers/ml/cnxk/cnxk_ml_ops.c b/drivers/ml/cnxk/cnxk_ml_ops.c\nindex f1872dcf7c..03402681c5 100644\n--- a/drivers/ml/cnxk/cnxk_ml_ops.c\n+++ b/drivers/ml/cnxk/cnxk_ml_ops.c\n@@ -3,5 +3,41 @@\n */\n \n #include <rte_mldev.h>\n+#include <rte_mldev_pmd.h>\n \n #include \"cnxk_ml_ops.h\"\n+\n+struct rte_ml_dev_ops cnxk_ml_ops = {\n+\t/* Device control ops */\n+\t.dev_info_get = cn10k_ml_dev_info_get,\n+\t.dev_configure = cn10k_ml_dev_configure,\n+\t.dev_close = cn10k_ml_dev_close,\n+\t.dev_start = cn10k_ml_dev_start,\n+\t.dev_stop = cn10k_ml_dev_stop,\n+\t.dev_dump = cn10k_ml_dev_dump,\n+\t.dev_selftest = cn10k_ml_dev_selftest,\n+\n+\t/* Queue-pair handling ops */\n+\t.dev_queue_pair_setup = cn10k_ml_dev_queue_pair_setup,\n+\t.dev_queue_pair_release = cn10k_ml_dev_queue_pair_release,\n+\n+\t/* Stats ops */\n+\t.dev_stats_get = cn10k_ml_dev_stats_get,\n+\t.dev_stats_reset = cn10k_ml_dev_stats_reset,\n+\t.dev_xstats_names_get = cn10k_ml_dev_xstats_names_get,\n+\t.dev_xstats_by_name_get = cn10k_ml_dev_xstats_by_name_get,\n+\t.dev_xstats_get = cn10k_ml_dev_xstats_get,\n+\t.dev_xstats_reset = cn10k_ml_dev_xstats_reset,\n+\n+\t/* Model ops */\n+\t.model_load = cn10k_ml_model_load,\n+\t.model_unload = cn10k_ml_model_unload,\n+\t.model_start = cn10k_ml_model_start,\n+\t.model_stop = cn10k_ml_model_stop,\n+\t.model_info_get = cn10k_ml_model_info_get,\n+\t.model_params_update = cn10k_ml_model_params_update,\n+\n+\t/* I/O ops */\n+\t.io_quantize = cn10k_ml_io_quantize,\n+\t.io_dequantize = cn10k_ml_io_dequantize,\n+};\ndiff --git a/drivers/ml/cnxk/cnxk_ml_ops.h b/drivers/ml/cnxk/cnxk_ml_ops.h\nindex b953fb0f5f..a925c07580 100644\n--- a/drivers/ml/cnxk/cnxk_ml_ops.h\n+++ b/drivers/ml/cnxk/cnxk_ml_ops.h\n@@ -60,4 +60,6 @@ struct cnxk_ml_qp {\n \tstruct rte_ml_dev_stats stats;\n };\n \n+extern struct rte_ml_dev_ops cnxk_ml_ops;\n+\n #endif /* _CNXK_ML_OPS_H_ */\n", "prefixes": [ "v4", "06/34" ] }