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GET /api/patches/132478/?format=api
{ "id": 132478, "url": "http://patches.dpdk.org/api/patches/132478/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231010202049.771959-9-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231010202049.771959-9-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231010202049.771959-9-nicolas.chautru@intel.com", "date": "2023-10-10T20:20:45", "name": "[v6,08/12] baseband/acc: add FEC capabilities for the VRB2 variant", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c235889d14271d63bcb5e129b11a2b0181481b42", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231010202049.771959-9-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29799, "url": "http://patches.dpdk.org/api/series/29799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29799", "date": "2023-10-10T20:20:37", "name": "VRB2 bbdev PMD introduction", "version": 6, "mbox": "http://patches.dpdk.org/series/29799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132478/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/132478/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3BC5D42354;\n\tTue, 10 Oct 2023 22:21:54 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B43F640A8A;\n\tTue, 10 Oct 2023 22:20:59 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 9FF6A4028A\n for <dev@dpdk.org>; Tue, 10 Oct 2023 22:20:51 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Oct 2023 13:20:50 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2023 13:20:50 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1696969251; x=1728505251;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=lOzDt44yw/dy1cHDeTmg3JM29cYil4iBMwvwTuR8Jag=;\n b=arYqvgpDA07Ee0Y28dA83CnPRKB2HhWPZZLZEaimp8zeAZQ1bxP1eQE6\n 7PYqS3EaNg8lstxdHFS5fmyCBmGpcj0SJUfRYwm4Pas62KkL2ZkcG4c+M\n GqUGscEYe/hwcN0HBVH95/DAiQOROx7Tcp0EAP8eVjPOMv4pXM9YMQbUq\n vseSdwquzeQsBky6ed01FSrD/+61/ZrkoPM+zWN4Wxe/QGV2DMM7cDA2k\n fvq6pgViH7P6PAAe2AFB3VaXP8d8oK0FmIfTbbnFlTWrGcGTsNLysoKX0\n 6zBAyS0NqQ4WmtGSqGh8VbNK2G/KVq8lL+lPpT+QAfbCvddVLf7mMUP84 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10859\"; a=\"364789104\"", "E=Sophos;i=\"6.03,213,1694761200\"; d=\"scan'208\";a=\"364789104\"", "E=McAfee;i=\"6600,9927,10859\"; a=\"823904097\"", "E=Sophos;i=\"6.03,213,1694761200\"; d=\"scan'208\";a=\"823904097\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v6 08/12] baseband/acc: add FEC capabilities for the VRB2\n variant", "Date": "Tue, 10 Oct 2023 20:20:45 +0000", "Message-Id": "<20231010202049.771959-9-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231010202049.771959-1-nicolas.chautru@intel.com>", "References": "<20231010202049.771959-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "New implementation for some of the FEC features\nspecific to the VRB2 variant.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/rte_vrb_pmd.c | 370 +++++++++++++++++++++++++----\n 1 file changed, 328 insertions(+), 42 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex b36dd6ccd8..dab61fd5df 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -1235,6 +1235,94 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n \t};\n \n \tstatic const struct rte_bbdev_op_cap vrb2_bbdev_capabilities[] = {\n+\t\t{\n+\t\t\t.type = RTE_BBDEV_OP_TURBO_DEC,\n+\t\t\t.cap.turbo_dec = {\n+\t\t\t\t.capability_flags =\n+\t\t\t\t\tRTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE |\n+\t\t\t\t\tRTE_BBDEV_TURBO_CRC_TYPE_24B |\n+\t\t\t\t\tRTE_BBDEV_TURBO_DEC_CRC_24B_DROP |\n+\t\t\t\t\tRTE_BBDEV_TURBO_EQUALIZER |\n+\t\t\t\t\tRTE_BBDEV_TURBO_SOFT_OUT_SATURATE |\n+\t\t\t\t\tRTE_BBDEV_TURBO_HALF_ITERATION_EVEN |\n+\t\t\t\t\tRTE_BBDEV_TURBO_CONTINUE_CRC_MATCH |\n+\t\t\t\t\tRTE_BBDEV_TURBO_SOFT_OUTPUT |\n+\t\t\t\t\tRTE_BBDEV_TURBO_EARLY_TERMINATION |\n+\t\t\t\t\tRTE_BBDEV_TURBO_DEC_INTERRUPTS |\n+\t\t\t\t\tRTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |\n+\t\t\t\t\tRTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT |\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAP_DEC |\n+\t\t\t\t\tRTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP |\n+\t\t\t\t\tRTE_BBDEV_TURBO_DEC_SCATTER_GATHER,\n+\t\t\t\t.max_llr_modulus = INT8_MAX,\n+\t\t\t\t.num_buffers_src =\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_hard_out =\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_soft_out =\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_BBDEV_OP_TURBO_ENC,\n+\t\t\t.cap.turbo_enc = {\n+\t\t\t\t.capability_flags =\n+\t\t\t\t\tRTE_BBDEV_TURBO_CRC_24B_ATTACH |\n+\t\t\t\t\tRTE_BBDEV_TURBO_RV_INDEX_BYPASS |\n+\t\t\t\t\tRTE_BBDEV_TURBO_RATE_MATCH |\n+\t\t\t\t\tRTE_BBDEV_TURBO_ENC_INTERRUPTS |\n+\t\t\t\t\tRTE_BBDEV_TURBO_ENC_SCATTER_GATHER,\n+\t\t\t\t.num_buffers_src =\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_dst =\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_BBDEV_OP_LDPC_ENC,\n+\t\t\t.cap.ldpc_enc = {\n+\t\t\t\t.capability_flags =\n+\t\t\t\t\tRTE_BBDEV_LDPC_RATE_MATCH |\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH |\n+\t\t\t\t\tRTE_BBDEV_LDPC_INTERLEAVER_BYPASS |\n+\t\t\t\t\tRTE_BBDEV_LDPC_ENC_INTERRUPTS |\n+\t\t\t\t\tRTE_BBDEV_LDPC_ENC_SCATTER_GATHER |\n+\t\t\t\t\tRTE_BBDEV_LDPC_ENC_CONCATENATION,\n+\t\t\t\t.num_buffers_src =\n+\t\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_dst =\n+\t\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_BBDEV_OP_LDPC_DEC,\n+\t\t\t.cap.ldpc_dec = {\n+\t\t\t.capability_flags =\n+\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |\n+\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |\n+\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK |\n+\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_16_CHECK |\n+\t\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |\n+\t\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |\n+\t\t\t\tRTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |\n+\t\t\t\tRTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS |\n+\t\t\t\tRTE_BBDEV_LDPC_DEC_SCATTER_GATHER |\n+\t\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION |\n+\t\t\t\tRTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION |\n+\t\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION |\n+\t\t\t\tRTE_BBDEV_LDPC_SOFT_OUT_ENABLE |\n+\t\t\t\tRTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS |\n+\t\t\t\tRTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS |\n+\t\t\t\tRTE_BBDEV_LDPC_DEC_INTERRUPTS,\n+\t\t\t.llr_size = 8,\n+\t\t\t.llr_decimals = 2,\n+\t\t\t.num_buffers_src =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t.num_buffers_hard_out =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t.num_buffers_soft_out = 0,\n+\t\t\t}\n+\t\t},\n \t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n \t};\n \n@@ -1419,8 +1507,8 @@ vrb_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw)\n \n /* Fill in a frame control word for LDPC decoding. */\n static inline void\n-vrb1_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n-\t\tunion acc_harq_layout_data *harq_layout)\n+vrb_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n+\t\tunion acc_harq_layout_data *harq_layout, uint16_t device_variant)\n {\n \tuint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;\n \tuint32_t harq_index;\n@@ -1466,18 +1554,26 @@ vrb1_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \t\tfcw->bypass_intlv = 1;\n \t\tfcw->qm = 2;\n \t}\n-\tfcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n-\tfcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n+\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) {\n+\t\tfcw->hcin_decomp_mode = 1;\n+\t\tfcw->hcout_comp_mode = 1;\n+\t} else if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION)) {\n+\t\tfcw->hcin_decomp_mode = 4;\n+\t\tfcw->hcout_comp_mode = 4;\n+\t} else {\n+\t\tfcw->hcin_decomp_mode = 0;\n+\t\tfcw->hcout_comp_mode = 0;\n+\t}\n+\n \tfcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION);\n \tharq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);\n-\n \tif (fcw->hcin_en > 0) {\n \t\tharq_in_length = op->ldpc_dec.harq_combined_input.length;\n-\t\tif (fcw->hcin_decomp_mode > 0)\n+\t\tif (fcw->hcin_decomp_mode == 1)\n \t\t\tharq_in_length = harq_in_length * 8 / 6;\n+\t\telse if (fcw->hcin_decomp_mode == 4)\n+\t\t\tharq_in_length = harq_in_length * 2;\n \t\tharq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb\n \t\t\t\t- op->ldpc_dec.n_filler);\n \t\tharq_in_length = RTE_ALIGN_CEIL(harq_in_length, 64);\n@@ -1491,20 +1587,27 @@ vrb1_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \t}\n \n \tfcw->itmax = op->ldpc_dec.iter_max;\n-\tfcw->itstop = check_bit(op->ldpc_dec.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);\n+\tfcw->itstop = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);\n \tfcw->cnu_algo = ACC_ALGO_MSA;\n \tfcw->synd_precoder = fcw->itstop;\n+\n+\tif (device_variant != VRB1_VARIANT) {\n+\t\tfcw->so_it = op->ldpc_dec.iter_max;\n+\t\tfcw->so_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_ENABLE);\n+\t\tfcw->so_bypass_intlv = check_bit(op->ldpc_dec.op_flags,\n+\t\t\t\tRTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS);\n+\t\tfcw->so_bypass_rm = check_bit(op->ldpc_dec.op_flags,\n+\t\t\t\tRTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS);\n+\t\tfcw->minsum_offset = 1;\n+\t\tfcw->dec_llrclip = 2;\n+\t}\n+\n \t/*\n-\t * These are all implicitly set:\n+\t * These are all implicitly set\n \t * fcw->synd_post = 0;\n-\t * fcw->so_en = 0;\n-\t * fcw->so_bypass_rm = 0;\n-\t * fcw->so_bypass_intlv = 0;\n \t * fcw->dec_convllr = 0;\n \t * fcw->hcout_convllr = 0;\n \t * fcw->hcout_size1 = 0;\n-\t * fcw->so_it = 0;\n \t * fcw->hcout_offset = 0;\n \t * fcw->negstop_th = 0;\n \t * fcw->negstop_it = 0;\n@@ -1515,7 +1618,8 @@ vrb1_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \tif (fcw->hcout_en > 0) {\n \t\tparity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)\n \t\t\t\t* op->ldpc_dec.z_c - op->ldpc_dec.n_filler;\n-\t\tk0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;\n+\t\tk0_p = (fcw->k0 > parity_offset) ?\n+\t\t\t\tfcw->k0 - op->ldpc_dec.n_filler : fcw->k0;\n \t\tncb_p = fcw->ncb - op->ldpc_dec.n_filler;\n \t\tl = k0_p + fcw->rm_e;\n \t\tharq_out_length = (uint16_t) fcw->hcin_size0;\n@@ -1658,19 +1762,28 @@ vrb_dma_desc_td_fill(struct rte_bbdev_dec_op *op,\n }\n \n static inline int\n-vrb1_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n+vrb_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\tstruct acc_dma_req_desc *desc,\n \t\tstruct rte_mbuf **input, struct rte_mbuf *h_output,\n \t\tuint32_t *in_offset, uint32_t *h_out_offset,\n \t\tuint32_t *h_out_length, uint32_t *mbuf_total_left,\n-\t\tuint32_t *seg_total_left, struct acc_fcw_ld *fcw)\n+\t\tuint32_t *seg_total_left, struct acc_fcw_ld *fcw, uint16_t device_variant)\n {\n \tstruct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;\n \tint next_triplet = 1; /* FCW already done. */\n \tuint32_t input_length;\n \tuint16_t output_length, crc24_overlap = 0;\n \tuint16_t sys_cols, K, h_p_size, h_np_size;\n-\tbool h_comp = check_bit(dec->op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n+\n+\tif (device_variant == VRB1_VARIANT) {\n+\t\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION) ||\n+\t\t\t\tcheck_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_ENABLE)) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"VRB1 does not support the requested capabilities %x\",\n+\t\t\t\t\top->ldpc_dec.op_flags);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n \n \tacc_header_init(desc);\n \n@@ -1711,8 +1824,10 @@ vrb1_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\t\treturn -1;\n \t\t}\n \t\th_p_size = fcw->hcin_size0 + fcw->hcin_size1;\n-\t\tif (h_comp)\n+\t\tif (fcw->hcin_decomp_mode == 1)\n \t\t\th_p_size = (h_p_size * 3 + 3) / 4;\n+\t\telse if (fcw->hcin_decomp_mode == 4)\n+\t\t\th_p_size = h_p_size / 2;\n \t\tif (op->ldpc_dec.harq_combined_input.data == 0) {\n \t\t\trte_bbdev_log(ERR, \"HARQ input is not defined\");\n \t\t\treturn -1;\n@@ -1735,21 +1850,36 @@ vrb1_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\t\t*h_out_offset, output_length >> 3, next_triplet,\n \t\t\tACC_DMA_BLKID_OUT_HARD);\n \n-\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {\n+\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_ENABLE)) {\n+\t\tif (op->ldpc_dec.soft_output.data == 0) {\n+\t\t\trte_bbdev_log(ERR, \"Soft output is not defined\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tdec->soft_output.length = fcw->rm_e;\n+\t\tacc_dma_fill_blk_type(desc, dec->soft_output.data, dec->soft_output.offset,\n+\t\t\t\tfcw->rm_e, next_triplet, ACC_DMA_BLKID_OUT_SOFT);\n+\t\tnext_triplet++;\n+\t}\n+\n+\tif (check_bit(op->ldpc_dec.op_flags,\n+\t\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {\n \t\tif (op->ldpc_dec.harq_combined_output.data == 0) {\n \t\t\trte_bbdev_log(ERR, \"HARQ output is not defined\");\n \t\t\treturn -1;\n \t\t}\n \n-\t\t/* Pruned size of the HARQ. */\n+\t\t/* Pruned size of the HARQ */\n \t\th_p_size = fcw->hcout_size0 + fcw->hcout_size1;\n-\t\t/* Non-Pruned size of the HARQ. */\n+\t\t/* Non-Pruned size of the HARQ */\n \t\th_np_size = fcw->hcout_offset > 0 ?\n \t\t\t\tfcw->hcout_offset + fcw->hcout_size1 :\n \t\t\t\th_p_size;\n-\t\tif (h_comp) {\n+\t\tif (fcw->hcin_decomp_mode == 1) {\n \t\t\th_np_size = (h_np_size * 3 + 3) / 4;\n \t\t\th_p_size = (h_p_size * 3 + 3) / 4;\n+\t\t} else if (fcw->hcin_decomp_mode == 4) {\n+\t\t\th_np_size = h_np_size / 2;\n+\t\t\th_p_size = h_p_size / 2;\n \t\t}\n \t\tdec->harq_combined_output.length = h_np_size;\n \t\tacc_dma_fill_blk_type(\n@@ -1877,6 +2007,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops,\n \t/** This could be done at polling. */\n \tacc_header_init(&desc->req);\n \tdesc->req.numCBs = num;\n+\tdesc->req.dltb = 0;\n \n \tin_length_in_bytes = ops[0]->ldpc_enc.input.data->data_len;\n \tout_length = (enc->cb_params.e + 7) >> 3;\n@@ -2102,6 +2233,104 @@ vrb1_enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op\n \treturn return_descs;\n }\n \n+/* Fill in a frame control word for LDPC encoding. */\n+static inline void\n+vrb2_fcw_letb_fill(const struct rte_bbdev_enc_op *op, struct acc_fcw_le *fcw)\n+{\n+\tfcw->qm = op->ldpc_enc.q_m;\n+\tfcw->nfiller = op->ldpc_enc.n_filler;\n+\tfcw->BG = (op->ldpc_enc.basegraph - 1);\n+\tfcw->Zc = op->ldpc_enc.z_c;\n+\tfcw->ncb = op->ldpc_enc.n_cb;\n+\tfcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_enc.basegraph,\n+\t\t\top->ldpc_enc.rv_index);\n+\tfcw->rm_e = op->ldpc_enc.tb_params.ea;\n+\tfcw->rm_e_b = op->ldpc_enc.tb_params.eb;\n+\tfcw->crc_select = check_bit(op->ldpc_enc.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH);\n+\tfcw->bypass_intlv = 0;\n+\tif (op->ldpc_enc.tb_params.c > 1) {\n+\t\tfcw->mcb_count = 0;\n+\t\tfcw->C = op->ldpc_enc.tb_params.c;\n+\t\tfcw->Cab = op->ldpc_enc.tb_params.cab;\n+\t} else {\n+\t\tfcw->mcb_count = 1;\n+\t\tfcw->C = 0;\n+\t}\n+}\n+\n+/* Enqueue one encode operations for device in TB mode.\n+ * returns the number of descs used.\n+ */\n+static inline int\n+vrb2_enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,\n+\t\tuint16_t enq_descs)\n+{\n+\tunion acc_dma_desc *desc = NULL;\n+\tuint32_t in_offset, out_offset, out_length, seg_total_left;\n+\tstruct rte_mbuf *input, *output_head, *output;\n+\tstruct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;\n+\tint next_triplet = 1; /* FCW already done. */\n+\tuint32_t in_length_in_bytes;\n+\tuint16_t K, in_length_in_bits;\n+\n+\tdesc = acc_desc(q, enq_descs);\n+\tvrb2_fcw_letb_fill(op, &desc->req.fcw_le);\n+\n+\tinput = enc->input.data;\n+\toutput_head = output = enc->output.data;\n+\tin_offset = enc->input.offset;\n+\tout_offset = enc->output.offset;\n+\tseg_total_left = rte_pktmbuf_data_len(enc->input.data) - in_offset;\n+\n+\tacc_header_init(&desc->req);\n+\tK = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;\n+\tin_length_in_bits = K - enc->n_filler;\n+\tif ((enc->op_flags & RTE_BBDEV_LDPC_CRC_24A_ATTACH) ||\n+\t\t\t(enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH))\n+\t\tin_length_in_bits -= 24;\n+\tin_length_in_bytes = (in_length_in_bits >> 3) * enc->tb_params.c;\n+\n+\tnext_triplet = acc_dma_fill_blk_type_in(&desc->req, &input, &in_offset,\n+\t\t\tin_length_in_bytes, &seg_total_left, next_triplet,\n+\t\t\tcheck_bit(enc->op_flags, RTE_BBDEV_LDPC_ENC_SCATTER_GATHER));\n+\tif (unlikely(next_triplet < 0)) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Mismatch between data to process and mbuf data length in bbdev_op: %p\",\n+\t\t\t\top);\n+\t\treturn -1;\n+\t}\n+\tdesc->req.data_ptrs[next_triplet - 1].last = 1;\n+\tdesc->req.m2dlen = next_triplet;\n+\n+\t/* Set output length */\n+\t/* Integer round up division by 8 */\n+\tout_length = (enc->tb_params.ea * enc->tb_params.cab +\n+\t\t\tenc->tb_params.eb * (enc->tb_params.c - enc->tb_params.cab) + 7) >> 3;\n+\n+\tnext_triplet = acc_dma_fill_blk_type(&desc->req, output, out_offset,\n+\t\t\tout_length, next_triplet, ACC_DMA_BLKID_OUT_ENC);\n+\tenc->output.length = out_length;\n+\tout_offset += out_length;\n+\tdesc->req.data_ptrs[next_triplet - 1].last = 1;\n+\tdesc->req.data_ptrs[next_triplet - 1].dma_ext = 0;\n+\tdesc->req.d2mlen = next_triplet - desc->req.m2dlen;\n+\tdesc->req.numCBs = enc->tb_params.c;\n+\tif (desc->req.numCBs > 1)\n+\t\tdesc->req.dltb = 1;\n+\tdesc->req.op_addr = op;\n+\n+\tif (out_length < ACC_MAX_E_MBUF)\n+\t\tmbuf_append(output_head, output, out_length);\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\trte_memdump(stderr, \"FCW\", &desc->req.fcw_le, sizeof(desc->req.fcw_le));\n+\trte_memdump(stderr, \"Req Desc.\", desc, sizeof(*desc));\n+#endif\n+\t/* One CB (one op) was successfully prepared to enqueue */\n+\treturn 1;\n+}\n+\n /** Enqueue one decode operations for device in CB mode. */\n static inline int\n enqueue_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n@@ -2206,7 +2435,7 @@ vrb_enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tstruct acc_fcw_ld *fcw;\n \t\tuint32_t seg_total_left;\n \t\tfcw = &desc->req.fcw_ld;\n-\t\tq->d->fcw_ld_fill(op, fcw, harq_layout);\n+\t\tvrb_fcw_ld_fill(op, fcw, harq_layout, q->d->device_variant);\n \n \t\t/* Special handling when using mbuf or not. */\n \t\tif (check_bit(op->ldpc_dec.op_flags,\n@@ -2215,10 +2444,10 @@ vrb_enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\telse\n \t\t\tseg_total_left = fcw->rm_e;\n \n-\t\tret = vrb1_dma_desc_ld_fill(op, &desc->req, &input, h_output,\n+\t\tret = vrb_dma_desc_ld_fill(op, &desc->req, &input, h_output,\n \t\t\t\t&in_offset, &h_out_offset,\n \t\t\t\t&h_out_length, &mbuf_total_left,\n-\t\t\t\t&seg_total_left, fcw);\n+\t\t\t\t&seg_total_left, fcw, q->d->device_variant);\n \t\tif (unlikely(ret < 0))\n \t\t\treturn ret;\n \t}\n@@ -2275,7 +2504,8 @@ vrb_enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \tdesc_first = desc;\n \tfcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET;\n \tharq_layout = q->d->harq_layout;\n-\tq->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);\n+\n+\tvrb_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q->d->device_variant);\n \n \tinput = op->ldpc_dec.input.data;\n \th_output_head = h_output = op->ldpc_dec.hard_output.data;\n@@ -2307,12 +2537,11 @@ vrb_enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tdesc->req.data_ptrs[0].blen = ACC_FCW_LD_BLEN;\n \t\trte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, ACC_FCW_LD_BLEN);\n \t\tdesc->req.fcw_ld.tb_trailer_size = (c - r - 1) * trail_len;\n-\n-\t\tret = vrb1_dma_desc_ld_fill(op, &desc->req, &input,\n+\t\tret = vrb_dma_desc_ld_fill(op, &desc->req, &input,\n \t\t\t\th_output, &in_offset, &h_out_offset,\n \t\t\t\t&h_out_length,\n \t\t\t\t&mbuf_total_left, &seg_total_left,\n-\t\t\t\t&desc->req.fcw_ld);\n+\t\t\t\t&desc->req.fcw_ld, q->d->device_variant);\n \n \t\tif (unlikely(ret < 0))\n \t\t\treturn ret;\n@@ -2576,14 +2805,22 @@ vrb_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,\n \tint descs_used;\n \n \tfor (i = 0; i < num; ++i) {\n-\t\tcbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc);\n-\t\t/* Check if there are available space for further processing. */\n-\t\tif (unlikely((avail - cbs_in_tb < 0) || (cbs_in_tb == 0))) {\n-\t\t\tacc_enqueue_ring_full(q_data);\n-\t\t\tbreak;\n+\t\tif (q->d->device_variant == VRB1_VARIANT) {\n+\t\t\tcbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc);\n+\t\t\t/* Check if there are available space for further processing. */\n+\t\t\tif (unlikely((avail - cbs_in_tb < 0) || (cbs_in_tb == 0))) {\n+\t\t\t\tacc_enqueue_ring_full(q_data);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tdescs_used = vrb1_enqueue_ldpc_enc_one_op_tb(q, ops[i],\n+\t\t\t\t\tenqueued_descs, cbs_in_tb);\n+\t\t} else {\n+\t\t\tif (unlikely(avail < 1)) {\n+\t\t\t\tacc_enqueue_ring_full(q_data);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tdescs_used = vrb2_enqueue_ldpc_enc_one_op_tb(q, ops[i], enqueued_descs);\n \t\t}\n-\n-\t\tdescs_used = vrb1_enqueue_ldpc_enc_one_op_tb(q, ops[i], enqueued_descs, cbs_in_tb);\n \t\tif (descs_used < 0) {\n \t\t\tacc_enqueue_invalid(q_data);\n \t\t\tbreak;\n@@ -2865,6 +3102,51 @@ vrb_dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n \treturn desc->req.numCBs;\n }\n \n+/* Dequeue one LDPC encode operations from VRB2 device in TB mode. */\n+static inline int\n+vrb2_dequeue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n+\t\tuint16_t *dequeued_ops, uint32_t *aq_dequeued,\n+\t\tuint16_t *dequeued_descs)\n+{\n+\tunion acc_dma_desc *desc, atom_desc;\n+\tunion acc_dma_rsp_desc rsp;\n+\tstruct rte_bbdev_enc_op *op;\n+\n+\tdesc = acc_desc_tail(q, *dequeued_descs);\n+\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);\n+\n+\t/* Check fdone bit. */\n+\tif (!(atom_desc.rsp.val & ACC_FDONE))\n+\t\treturn -1;\n+\n+\trsp.val = atom_desc.rsp.val;\n+\trte_bbdev_log_debug(\"Resp. desc %p: %x\", desc, rsp.val);\n+\n+\t/* Dequeue. */\n+\top = desc->req.op_addr;\n+\n+\t/* Clearing status, it will be set based on response. */\n+\top->status = 0;\n+\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n+\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n+\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n+\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\n+\tif (desc->req.last_desc_in_batch) {\n+\t\t(*aq_dequeued)++;\n+\t\tdesc->req.last_desc_in_batch = 0;\n+\t}\n+\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n+\tdesc->rsp.add_info_0 = 0; /* Reserved bits. */\n+\tdesc->rsp.add_info_1 = 0; /* Reserved bits. */\n+\n+\t/* One op was successfully dequeued */\n+\tref_op[0] = op;\n+\t(*dequeued_descs)++;\n+\t(*dequeued_ops)++;\n+\treturn 1;\n+}\n+\n /* Dequeue one LDPC encode operations from device in TB mode.\n * That operation may cover multiple descriptors.\n */\n@@ -3189,9 +3471,14 @@ vrb_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \n \tfor (i = 0; i < avail; i++) {\n \t\tif (cbm == RTE_BBDEV_TRANSPORT_BLOCK)\n-\t\t\tret = vrb_dequeue_enc_one_op_tb(q, &ops[dequeued_ops],\n-\t\t\t\t\t&dequeued_ops, &aq_dequeued,\n-\t\t\t\t\t&dequeued_descs, num);\n+\t\t\tif (q->d->device_variant == VRB1_VARIANT)\n+\t\t\t\tret = vrb_dequeue_enc_one_op_tb(q, &ops[dequeued_ops],\n+\t\t\t\t\t\t&dequeued_ops, &aq_dequeued,\n+\t\t\t\t\t\t&dequeued_descs, num);\n+\t\t\telse\n+\t\t\t\tret = vrb2_dequeue_ldpc_enc_one_op_tb(q, &ops[dequeued_ops],\n+\t\t\t\t\t\t&dequeued_ops, &aq_dequeued,\n+\t\t\t\t\t\t&dequeued_descs);\n \t\telse\n \t\t\tret = vrb_dequeue_enc_one_op_cb(q, &ops[dequeued_ops],\n \t\t\t\t\t&dequeued_ops, &aq_dequeued,\n@@ -3526,7 +3813,6 @@ vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \t\t\t(pci_dev->id.device_id == RTE_VRB1_VF_DEVICE_ID)) {\n \t\td->device_variant = VRB1_VARIANT;\n \t\td->queue_offset = vrb1_queue_offset;\n-\t\td->fcw_ld_fill = vrb1_fcw_ld_fill;\n \t\td->num_qgroups = VRB1_NUM_QGRPS;\n \t\td->num_aqs = VRB1_NUM_AQS;\n \t\tif (d->pf_device)\n", "prefixes": [ "v6", "08/12" ] }