Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132319/?format=api
{ "id": 132319, "url": "http://patches.dpdk.org/api/patches/132319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231005021854.109096-12-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231005021854.109096-12-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231005021854.109096-12-nicolas.chautru@intel.com", "date": "2023-10-05T02:18:53", "name": "[v4,11/12] baseband/acc: add support for VRB2 engine error detection", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "20837fffe10724e29de758856b5b5acc6a164c71", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231005021854.109096-12-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29739, "url": "http://patches.dpdk.org/api/series/29739/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29739", "date": "2023-10-05T02:18:42", "name": "VRB2 bbdev PMD introduction", "version": 4, "mbox": "http://patches.dpdk.org/series/29739/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132319/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/132319/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A3F1A426BB;\n\tThu, 5 Oct 2023 04:27:24 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 52A64406B8;\n\tThu, 5 Oct 2023 04:26:12 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id A243C402CE\n for <dev@dpdk.org>; Thu, 5 Oct 2023 04:26:00 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Oct 2023 19:26:00 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by orsmga008.jf.intel.com with ESMTP; 04 Oct 2023 19:25:59 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1696472760; x=1728008760;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=eK7N0vsUT0LtJsnIBIC1zv6hJyjxeb/OpC35ruXUV80=;\n b=fnucfXdWCWrB8/ZY75x3J1aNa2pv65Oqf//V07YwSkCUVoH9lQGmitl7\n M2/m0AcWGg2F5diiwVkpaxyO1h+7tLeYlEJQ7Gtqm4ldg2kG7gP0QDJh1\n jOcxtcCeU9So9RLBh68MiOtGyJMWN7p9P6SeVDfrZiPtfLyIIaO/AaifA\n jxNJwuri3cTrbELhpEcv4ek0pcdiIMoYLkxDIGiMnTYgVYGDPiurnIghw\n a0a/pxXJwy7CaCDEwG7TV4eFAK8pOiQLP6IBuxwqjcEExRo1ryEHAeQAb\n 5GLTz55YMzUG6FCswDVFQN6ir/g4WsW0oBqpbFTOmcCwRtoyRP41r8AvW w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10853\"; a=\"363657700\"", "E=Sophos;i=\"6.03,201,1694761200\"; d=\"scan'208\";a=\"363657700\"", "E=McAfee;i=\"6600,9927,10853\"; a=\"781063053\"", "E=Sophos;i=\"6.03,201,1694761200\"; d=\"scan'208\";a=\"781063053\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v4 11/12] baseband/acc: add support for VRB2 engine error\n detection", "Date": "Thu, 5 Oct 2023 02:18:53 +0000", "Message-Id": "<20231005021854.109096-12-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231005021854.109096-1-nicolas.chautru@intel.com>", "References": "<20231005021854.109096-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding missing incremental functionality for the VRB2\nvariant. Notably detection of engine error during the\ndequeue. Minor cosmetic edits.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/rte_vrb_pmd.c | 19 ++++++++++++-------\n drivers/baseband/acc/vrb1_pf_enum.h | 17 ++++++++++++-----\n 2 files changed, 24 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex d2e60d6ca8..eb9c4e4a5c 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -1499,6 +1499,7 @@ vrb_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw)\n \t\t\t\tfcw->ea = op->turbo_dec.cb_params.e;\n \t\t\t\tfcw->eb = op->turbo_dec.cb_params.e;\n \t\t\t}\n+\n \t\t\tif (op->turbo_dec.rv_index == 0)\n \t\t\t\tfcw->k0_start_col = ACC_FCW_TD_RVIDX_0;\n \t\t\telse if (op->turbo_dec.rv_index == 1)\n@@ -2073,7 +2074,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops,\n \treturn num;\n }\n \n-/* Enqueue one encode operations for device for a partial TB\n+/* Enqueue one encode operations for VRB1 device for a partial TB\n * all codes blocks have same configuration multiplexed on the same descriptor.\n */\n static inline void\n@@ -2417,7 +2418,7 @@ enqueue_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \treturn 1;\n }\n \n-/** Enqueue one decode operations for device in CB mode */\n+/** Enqueue one decode operations for device in CB mode. */\n static inline int\n vrb_enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tuint16_t total_enqueued_cbs, bool same_op)\n@@ -2981,7 +2982,6 @@ vrb_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,\n \t\t\tbreak;\n \t\t}\n \t\tavail -= 1;\n-\n \t\trte_bbdev_log(INFO, \"Op %d %d %d %d %d %d %d %d %d %d %d %d\\n\",\n \t\t\ti, ops[i]->ldpc_dec.op_flags, ops[i]->ldpc_dec.rv_index,\n \t\t\tops[i]->ldpc_dec.iter_max, ops[i]->ldpc_dec.iter_count,\n@@ -3109,6 +3109,7 @@ vrb_dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n \top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n \top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n \top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n \n \tif (desc->req.last_desc_in_batch) {\n \t\t(*aq_dequeued)++;\n@@ -3225,6 +3226,7 @@ vrb_dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n \t\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n \t\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n \t\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\t\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n \n \t\tif (desc->req.last_desc_in_batch) {\n \t\t\t(*aq_dequeued)++;\n@@ -3271,6 +3273,8 @@ vrb_dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n \top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n \top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\n \tif (op->status != 0) {\n \t\t/* These errors are not expected. */\n \t\tq_data->queue_stats.dequeue_err_count++;\n@@ -3324,6 +3328,7 @@ vrb_dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n \top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n \top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n+\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n \tif (op->status != 0)\n \t\tq_data->queue_stats.dequeue_err_count++;\n \n@@ -3405,6 +3410,7 @@ vrb_dequeue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,\n \t\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n \t\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n \t\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\t\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n \n \t\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK))\n \t\t\ttb_crc_check ^= desc->rsp.add_info_1;\n@@ -3456,7 +3462,6 @@ vrb_dequeue_enc(struct rte_bbdev_queue_data *q_data,\n \tif (avail == 0)\n \t\treturn 0;\n \top = acc_op_tail(q, 0);\n-\n \tcbm = op->turbo_enc.code_block_mode;\n \n \tfor (i = 0; i < avail; i++) {\n@@ -3796,9 +3801,8 @@ vrb_enqueue_fft_one_op(struct acc_queue *q, struct rte_bbdev_fft_op *op,\n \t\t\t\t&in_offset, &out_offset, &win_offset, &pwr_offset);\n \t}\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\trte_memdump(stderr, \"FCW\", &desc->req.fcw_fft,\n-\t\t\tsizeof(desc->req.fcw_fft));\n-\trte_memdump(stderr, \"Req Desc.\", desc, sizeof(*desc));\n+\trte_memdump(stderr, \"FCW\", fcw, 128);\n+\trte_memdump(stderr, \"Req Desc.\", desc, 128);\n #endif\n \treturn 1;\n }\n@@ -3871,6 +3875,7 @@ vrb_dequeue_fft_one_op(struct rte_bbdev_queue_data *q_data,\n \top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n \top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n \top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n+\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n \tif (op->status != 0)\n \t\tq_data->queue_stats.dequeue_err_count++;\n \ndiff --git a/drivers/baseband/acc/vrb1_pf_enum.h b/drivers/baseband/acc/vrb1_pf_enum.h\nindex 82a36685e9..6dc359800f 100644\n--- a/drivers/baseband/acc/vrb1_pf_enum.h\n+++ b/drivers/baseband/acc/vrb1_pf_enum.h\n@@ -98,11 +98,18 @@ enum {\n \tACC_PF_INT_DMA_UL5G_DESC_IRQ = 8,\n \tACC_PF_INT_DMA_DL5G_DESC_IRQ = 9,\n \tACC_PF_INT_DMA_MLD_DESC_IRQ = 10,\n-\tACC_PF_INT_ARAM_ECC_1BIT_ERR = 11,\n-\tACC_PF_INT_PARITY_ERR = 12,\n-\tACC_PF_INT_QMGR_ERR = 13,\n-\tACC_PF_INT_INT_REQ_OVERFLOW = 14,\n-\tACC_PF_INT_APB_TIMEOUT = 15,\n+\tACC_PF_INT_ARAM_ACCESS_ERR = 11,\n+\tACC_PF_INT_ARAM_ECC_1BIT_ERR = 12,\n+\tACC_PF_INT_PARITY_ERR = 13,\n+\tACC_PF_INT_QMGR_OVERFLOW = 14,\n+\tACC_PF_INT_QMGR_ERR = 15,\n+\tACC_PF_INT_ATS_ERR = 22,\n+\tACC_PF_INT_ARAM_FUUL = 23,\n+\tACC_PF_INT_EXTRA_READ = 24,\n+\tACC_PF_INT_COMPLETION_TIMEOUT = 25,\n+\tACC_PF_INT_CORE_HANG = 26,\n+\tACC_PF_INT_DMA_HANG = 28,\n+\tACC_PF_INT_DS_HANG = 27,\n };\n \n #endif /* VRB1_PF_ENUM_H */\n", "prefixes": [ "v4", "11/12" ] }