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GET /api/patches/132318/?format=api
{ "id": 132318, "url": "http://patches.dpdk.org/api/patches/132318/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231005021854.109096-11-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231005021854.109096-11-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231005021854.109096-11-nicolas.chautru@intel.com", "date": "2023-10-05T02:18:52", "name": "[v4,10/12] baseband/acc: add MLD support in VRB2 variant", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "663c48f572eecee81395da62ae1efec17962596b", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231005021854.109096-11-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29739, "url": "http://patches.dpdk.org/api/series/29739/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29739", "date": "2023-10-05T02:18:42", "name": "VRB2 bbdev PMD introduction", "version": 4, "mbox": "http://patches.dpdk.org/series/29739/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132318/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/132318/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3493A426BB;\n\tThu, 5 Oct 2023 04:27:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0402840A70;\n\tThu, 5 Oct 2023 04:26:11 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 2D5F4402D4\n for <dev@dpdk.org>; Thu, 5 Oct 2023 04:26:00 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Oct 2023 19:25:59 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by orsmga008.jf.intel.com with ESMTP; 04 Oct 2023 19:25:58 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1696472760; x=1728008760;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=os2UlA1IbPSzAxw5lWoIGLGb8a07tqEzWgrGiMiVWu8=;\n b=aPiodf3oauXLqs+Dxx5tjOM9l2qTENdQCSjWb0J4khGuML2aEMcLlByF\n kJFQ1T1xjcEu3gLNDd4oaU5QNCX1t7IDBRoH/L/Ok6b/FAyadkj1tEmNR\n wyX1hxfqfcHz6dquUjGhrysfvZ5+ssh/weBX2JB7MSgeWKRNJRZhplKfE\n vyhWEaaQraVI8HR5HZoHwoX5ge7Pmd7OMn0j/5s4XPOWSSARdlX21O/1D\n KvgFBjWVuWubev1hTgOKkYFUGnNaTLcSKH5E/n/l/g/xCiWDWr7UeKesZ\n YKZ00MgSe36cAVtJtlZcRWJM4O4UPl6OWRqWJlZR7NNTrCGRpW/AM7rPi A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10853\"; a=\"363657698\"", "E=Sophos;i=\"6.03,201,1694761200\"; d=\"scan'208\";a=\"363657698\"", "E=McAfee;i=\"6600,9927,10853\"; a=\"781063049\"", "E=Sophos;i=\"6.03,201,1694761200\"; d=\"scan'208\";a=\"781063049\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v4 10/12] baseband/acc: add MLD support in VRB2 variant", "Date": "Thu, 5 Oct 2023 02:18:52 +0000", "Message-Id": "<20231005021854.109096-11-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231005021854.109096-1-nicolas.chautru@intel.com>", "References": "<20231005021854.109096-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding the capability for the MLD-TS processing specific to\nthe VRB2 variant.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/rte_vrb_pmd.c | 374 +++++++++++++++++++++++++++++\n 1 file changed, 374 insertions(+)", "diff": "diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex c47416a443..d2e60d6ca8 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -1339,6 +1339,17 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n \t\t\t\t.fft_windows_num = ACC_MAX_FFT_WIN,\n \t\t\t}\n \t\t},\n+\t\t{\n+\t\t\t.type\t= RTE_BBDEV_OP_MLDTS,\n+\t\t\t.cap.mld = {\n+\t\t\t\t.capability_flags =\n+\t\t\t\t\t\tRTE_BBDEV_MLDTS_REP,\n+\t\t\t\t.num_buffers_src =\n+\t\t\t\t\t\t1,\n+\t\t\t\t.num_buffers_dst =\n+\t\t\t\t\t\t1,\n+\t\t\t}\n+\t\t},\n \t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n \t};\n \n@@ -3906,6 +3917,367 @@ vrb_dequeue_fft(struct rte_bbdev_queue_data *q_data,\n \treturn i;\n }\n \n+/* Fill in a frame control word for MLD-TS processing. */\n+static inline void\n+vrb2_fcw_mldts_fill(struct rte_bbdev_mldts_op *op, struct acc_fcw_mldts *fcw)\n+{\n+\tfcw->nrb = op->mldts.num_rbs;\n+\tfcw->NLayers = op->mldts.num_layers - 1;\n+\tfcw->Qmod0 = (op->mldts.q_m[0] >> 1) - 1;\n+\tfcw->Qmod1 = (op->mldts.q_m[1] >> 1) - 1;\n+\tfcw->Qmod2 = (op->mldts.q_m[2] >> 1) - 1;\n+\tfcw->Qmod3 = (op->mldts.q_m[3] >> 1) - 1;\n+\t/* Mark some layers as disabled */\n+\tif (op->mldts.num_layers == 2) {\n+\t\tfcw->Qmod2 = 3;\n+\t\tfcw->Qmod3 = 3;\n+\t}\n+\tif (op->mldts.num_layers == 3)\n+\t\tfcw->Qmod3 = 3;\n+\tfcw->Rrep = op->mldts.r_rep;\n+\tfcw->Crep = op->mldts.c_rep;\n+}\n+\n+/* Fill in descriptor for one MLD-TS processing operation. */\n+static inline int\n+vrb2_dma_desc_mldts_fill(struct rte_bbdev_mldts_op *op,\n+\t\tstruct acc_dma_req_desc *desc,\n+\t\tstruct rte_mbuf *input_q, struct rte_mbuf *input_r,\n+\t\tstruct rte_mbuf *output,\n+\t\tuint32_t *in_offset, uint32_t *out_offset)\n+{\n+\tuint16_t qsize_per_re[VRB2_MLD_LAY_SIZE] = {8, 12, 16}; /* Layer 2 to 4. */\n+\tuint16_t rsize_per_re[VRB2_MLD_LAY_SIZE] = {14, 26, 42};\n+\tuint16_t sc_factor_per_rrep[VRB2_MLD_RREP_SIZE] = {12, 6, 4, 3, 0, 2};\n+\tuint16_t i, outsize_per_re = 0;\n+\tuint32_t sc_num, r_num, q_size, r_size, out_size;\n+\n+\t/* Prevent out of range access. */\n+\tif (op->mldts.r_rep > 5)\n+\t\top->mldts.r_rep = 5;\n+\tif (op->mldts.num_layers < 2)\n+\t\top->mldts.num_layers = 2;\n+\tif (op->mldts.num_layers > 4)\n+\t\top->mldts.num_layers = 4;\n+\tfor (i = 0; i < op->mldts.num_layers; i++)\n+\t\toutsize_per_re += op->mldts.q_m[i];\n+\tsc_num = op->mldts.num_rbs * RTE_BBDEV_SCPERRB * (op->mldts.c_rep + 1);\n+\tr_num = op->mldts.num_rbs * sc_factor_per_rrep[op->mldts.r_rep];\n+\tq_size = qsize_per_re[op->mldts.num_layers - 2] * sc_num;\n+\tr_size = rsize_per_re[op->mldts.num_layers - 2] * r_num;\n+\tout_size = sc_num * outsize_per_re;\n+\n+\t/* FCW already done. */\n+\tacc_header_init(desc);\n+\tdesc->data_ptrs[1].address = rte_pktmbuf_iova_offset(input_q, *in_offset);\n+\tdesc->data_ptrs[1].blen = q_size;\n+\tdesc->data_ptrs[1].blkid = ACC_DMA_BLKID_IN;\n+\tdesc->data_ptrs[1].last = 0;\n+\tdesc->data_ptrs[1].dma_ext = 0;\n+\tdesc->data_ptrs[2].address = rte_pktmbuf_iova_offset(input_r, *in_offset);\n+\tdesc->data_ptrs[2].blen = r_size;\n+\tdesc->data_ptrs[2].blkid = ACC_DMA_BLKID_IN_MLD_R;\n+\tdesc->data_ptrs[2].last = 1;\n+\tdesc->data_ptrs[2].dma_ext = 0;\n+\tdesc->data_ptrs[3].address = rte_pktmbuf_iova_offset(output, *out_offset);\n+\tdesc->data_ptrs[3].blen = out_size;\n+\tdesc->data_ptrs[3].blkid = ACC_DMA_BLKID_OUT_HARD;\n+\tdesc->data_ptrs[3].last = 1;\n+\tdesc->data_ptrs[3].dma_ext = 0;\n+\tdesc->m2dlen = 3;\n+\tdesc->d2mlen = 1;\n+\tdesc->op_addr = op;\n+\tdesc->cbs_in_tb = 1;\n+\n+\treturn 0;\n+}\n+\n+/* Check whether the MLD operation can be processed as a single operation. */\n+static inline bool\n+vrb2_check_mld_r_constraint(struct rte_bbdev_mldts_op *op) {\n+\tuint8_t layer_idx, rrep_idx;\n+\tuint16_t max_rb[VRB2_MLD_LAY_SIZE][VRB2_MLD_RREP_SIZE] = {\n+\t\t\t{188, 275, 275, 275, 0, 275},\n+\t\t\t{101, 202, 275, 275, 0, 275},\n+\t\t\t{62, 124, 186, 248, 0, 275} };\n+\n+\tif (op->mldts.c_rep == 0)\n+\t\treturn true;\n+\n+\tlayer_idx = RTE_MIN(op->mldts.num_layers - VRB2_MLD_MIN_LAYER,\n+\t\t\tVRB2_MLD_MAX_LAYER - VRB2_MLD_MIN_LAYER);\n+\trrep_idx = RTE_MIN(op->mldts.r_rep, VRB2_MLD_MAX_RREP);\n+\trte_bbdev_log_debug(\"RB %d index %d %d max %d\\n\", op->mldts.num_rbs, layer_idx, rrep_idx,\n+\t\t\tmax_rb[layer_idx][rrep_idx]);\n+\n+\treturn (op->mldts.num_rbs <= max_rb[layer_idx][rrep_idx]);\n+}\n+\n+/** Enqueue MLDTS operation split across symbols. */\n+static inline int\n+enqueue_mldts_split_op(struct acc_queue *q, struct rte_bbdev_mldts_op *op,\n+\t\tuint16_t total_enqueued_descs)\n+{\n+\tuint16_t qsize_per_re[VRB2_MLD_LAY_SIZE] = {8, 12, 16}; /* Layer 2 to 4. */\n+\tuint16_t rsize_per_re[VRB2_MLD_LAY_SIZE] = {14, 26, 42};\n+\tuint16_t sc_factor_per_rrep[VRB2_MLD_RREP_SIZE] = {12, 6, 4, 3, 0, 2};\n+\tuint32_t i, outsize_per_re = 0, sc_num, r_num, q_size, r_size, out_size, num_syms;\n+\tunion acc_dma_desc *desc, *first_desc;\n+\tuint16_t desc_idx, symb;\n+\tstruct rte_mbuf *input_q, *input_r, *output;\n+\tuint32_t in_offset, out_offset;\n+\tstruct acc_fcw_mldts *fcw;\n+\n+\tdesc_idx = acc_desc_idx(q, total_enqueued_descs);\n+\tfirst_desc = q->ring_addr + desc_idx;\n+\tinput_q = op->mldts.qhy_input.data;\n+\tinput_r = op->mldts.r_input.data;\n+\toutput = op->mldts.output.data;\n+\tin_offset = op->mldts.qhy_input.offset;\n+\tout_offset = op->mldts.output.offset;\n+\tnum_syms = op->mldts.c_rep + 1;\n+\tfcw = &first_desc->req.fcw_mldts;\n+\tvrb2_fcw_mldts_fill(op, fcw);\n+\tfcw->Crep = 0; /* C rep forced to zero. */\n+\n+\t/* Prevent out of range access. */\n+\tif (op->mldts.r_rep > 5)\n+\t\top->mldts.r_rep = 5;\n+\tif (op->mldts.num_layers < 2)\n+\t\top->mldts.num_layers = 2;\n+\tif (op->mldts.num_layers > 4)\n+\t\top->mldts.num_layers = 4;\n+\n+\tfor (i = 0; i < op->mldts.num_layers; i++)\n+\t\toutsize_per_re += op->mldts.q_m[i];\n+\tsc_num = op->mldts.num_rbs * RTE_BBDEV_SCPERRB; /* C rep forced to zero. */\n+\tr_num = op->mldts.num_rbs * sc_factor_per_rrep[op->mldts.r_rep];\n+\tq_size = qsize_per_re[op->mldts.num_layers - 2] * sc_num;\n+\tr_size = rsize_per_re[op->mldts.num_layers - 2] * r_num;\n+\tout_size = sc_num * outsize_per_re;\n+\n+\tfor (symb = 0; symb < num_syms; symb++) {\n+\t\tdesc_idx = ((q->sw_ring_head + total_enqueued_descs + symb) & q->sw_ring_wrap_mask);\n+\t\tdesc = q->ring_addr + desc_idx;\n+\t\tacc_header_init(&desc->req);\n+\t\tif (symb == 0)\n+\t\t\tdesc->req.cbs_in_tb = num_syms;\n+\t\telse\n+\t\t\trte_memcpy(&desc->req.fcw_mldts, fcw, ACC_FCW_MLDTS_BLEN);\n+\t\tdesc->req.data_ptrs[1].address = rte_pktmbuf_iova_offset(input_q, in_offset);\n+\t\tdesc->req.data_ptrs[1].blen = q_size;\n+\t\tin_offset += q_size;\n+\t\tdesc->req.data_ptrs[1].blkid = ACC_DMA_BLKID_IN;\n+\t\tdesc->req.data_ptrs[1].last = 0;\n+\t\tdesc->req.data_ptrs[1].dma_ext = 0;\n+\t\tdesc->req.data_ptrs[2].address = rte_pktmbuf_iova_offset(input_r, 0);\n+\t\tdesc->req.data_ptrs[2].blen = r_size;\n+\t\tdesc->req.data_ptrs[2].blkid = ACC_DMA_BLKID_IN_MLD_R;\n+\t\tdesc->req.data_ptrs[2].last = 1;\n+\t\tdesc->req.data_ptrs[2].dma_ext = 0;\n+\t\tdesc->req.data_ptrs[3].address = rte_pktmbuf_iova_offset(output, out_offset);\n+\t\tdesc->req.data_ptrs[3].blen = out_size;\n+\t\tout_offset += out_size;\n+\t\tdesc->req.data_ptrs[3].blkid = ACC_DMA_BLKID_OUT_HARD;\n+\t\tdesc->req.data_ptrs[3].last = 1;\n+\t\tdesc->req.data_ptrs[3].dma_ext = 0;\n+\t\tdesc->req.m2dlen = VRB2_MLD_M2DLEN;\n+\t\tdesc->req.d2mlen = 1;\n+\t\tdesc->req.op_addr = op;\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t\trte_memdump(stderr, \"FCW\", &desc->req.fcw_mldts, sizeof(desc->req.fcw_mldts));\n+\t\trte_memdump(stderr, \"Req Desc.\", desc, sizeof(*desc));\n+#endif\n+\t}\n+\tdesc->req.sdone_enable = 0;\n+\n+\treturn num_syms;\n+}\n+\n+/** Enqueue one MLDTS operation. */\n+static inline int\n+enqueue_mldts_one_op(struct acc_queue *q, struct rte_bbdev_mldts_op *op,\n+\t\tuint16_t total_enqueued_descs)\n+{\n+\tunion acc_dma_desc *desc;\n+\tstruct rte_mbuf *input_q, *input_r, *output;\n+\tuint32_t in_offset, out_offset;\n+\tstruct acc_fcw_mldts *fcw;\n+\n+\tdesc = acc_desc(q, total_enqueued_descs);\n+\tinput_q = op->mldts.qhy_input.data;\n+\tinput_r = op->mldts.r_input.data;\n+\toutput = op->mldts.output.data;\n+\tin_offset = op->mldts.qhy_input.offset;\n+\tout_offset = op->mldts.output.offset;\n+\tfcw = &desc->req.fcw_mldts;\n+\tvrb2_fcw_mldts_fill(op, fcw);\n+\tvrb2_dma_desc_mldts_fill(op, &desc->req, input_q, input_r, output,\n+\t\t\t&in_offset, &out_offset);\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\trte_memdump(stderr, \"FCW\", &desc->req.fcw_mldts, sizeof(desc->req.fcw_mldts));\n+\trte_memdump(stderr, \"Req Desc.\", desc, sizeof(*desc));\n+#endif\n+\treturn 1;\n+}\n+\n+/* Enqueue MLDTS operations. */\n+static uint16_t\n+vrb2_enqueue_mldts(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_mldts_op **ops, uint16_t num)\n+{\n+\tint32_t aq_avail, avail;\n+\tstruct acc_queue *q = q_data->queue_private;\n+\tuint16_t i, enqueued_descs = 0, descs_in_op;\n+\tint ret;\n+\tbool as_one_op;\n+\n+\taq_avail = acc_aq_avail(q_data, num);\n+\tif (unlikely((aq_avail <= 0) || (num == 0)))\n+\t\treturn 0;\n+\tavail = acc_ring_avail_enq(q);\n+\n+\tfor (i = 0; i < num; ++i) {\n+\t\tas_one_op = vrb2_check_mld_r_constraint(ops[i]);\n+\t\tdescs_in_op = as_one_op ? 1 : ops[i]->mldts.c_rep + 1;\n+\n+\t\t/* Check if there are available space for further processing. */\n+\t\tif (unlikely(avail < descs_in_op)) {\n+\t\t\tacc_enqueue_ring_full(q_data);\n+\t\t\tbreak;\n+\t\t}\n+\t\tavail -= descs_in_op;\n+\n+\t\tif (as_one_op)\n+\t\t\tret = enqueue_mldts_one_op(q, ops[i], enqueued_descs);\n+\t\telse\n+\t\t\tret = enqueue_mldts_split_op(q, ops[i], enqueued_descs);\n+\n+\t\tif (ret < 0) {\n+\t\t\tacc_enqueue_invalid(q_data);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tenqueued_descs += ret;\n+\t}\n+\n+\tif (unlikely(i == 0))\n+\t\treturn 0; /* Nothing to enqueue. */\n+\n+\tacc_dma_enqueue(q, enqueued_descs, &q_data->queue_stats);\n+\n+\t/* Update stats. */\n+\tq_data->queue_stats.enqueued_count += i;\n+\tq_data->queue_stats.enqueue_err_count += num - i;\n+\treturn i;\n+}\n+\n+/*\n+ * Dequeue one MLDTS operation.\n+ * This may have been split over multiple descriptors.\n+ */\n+static inline int\n+dequeue_mldts_one_op(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct acc_queue *q, struct rte_bbdev_mldts_op **ref_op,\n+\t\tuint16_t dequeued_ops, uint32_t *aq_dequeued)\n+{\n+\tunion acc_dma_desc *desc, atom_desc, *last_desc;\n+\tunion acc_dma_rsp_desc rsp;\n+\tstruct rte_bbdev_mldts_op *op;\n+\tuint8_t descs_in_op, i;\n+\n+\tdesc = acc_desc_tail(q, dequeued_ops);\n+\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);\n+\n+\t/* Check fdone bit. */\n+\tif (!(atom_desc.rsp.val & ACC_FDONE))\n+\t\treturn -1;\n+\n+\tdescs_in_op = desc->req.cbs_in_tb;\n+\tif (descs_in_op > 1) {\n+\t\t/* Get last CB. */\n+\t\tlast_desc = acc_desc_tail(q, dequeued_ops + descs_in_op - 1);\n+\t\t/* Check if last op is ready to dequeue by checking fdone bit. If not exit. */\n+\t\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)last_desc, __ATOMIC_RELAXED);\n+\t\tif (!(atom_desc.rsp.val & ACC_FDONE))\n+\t\t\treturn -1;\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t\trte_memdump(stderr, \"Last Resp\", &last_desc->rsp.val, sizeof(desc->rsp.val));\n+#endif\n+\t\t/* Check each operation iteratively using fdone. */\n+\t\tfor (i = 1; i < descs_in_op - 1; i++) {\n+\t\t\tlast_desc = q->ring_addr + ((q->sw_ring_tail + dequeued_ops + i)\n+\t\t\t\t\t& q->sw_ring_wrap_mask);\n+\t\t\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)last_desc,\n+\t\t\t\t\t__ATOMIC_RELAXED);\n+\t\t\tif (!(atom_desc.rsp.val & ACC_FDONE))\n+\t\t\t\treturn -1;\n+\t\t}\n+\t}\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\trte_memdump(stderr, \"Resp\", &desc->rsp.val, sizeof(desc->rsp.val));\n+#endif\n+\t/* Dequeue. */\n+\top = desc->req.op_addr;\n+\n+\t/* Clearing status, it will be set based on response. */\n+\top->status = 0;\n+\n+\tfor (i = 0; i < descs_in_op; i++) {\n+\t\tdesc = q->ring_addr + ((q->sw_ring_tail + dequeued_ops + i) & q->sw_ring_wrap_mask);\n+\t\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);\n+\t\trsp.val = atom_desc.rsp.val;\n+\t\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n+\t\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n+\t\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n+\t\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\t}\n+\n+\tif (op->status != 0)\n+\t\tq_data->queue_stats.dequeue_err_count++;\n+\tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n+\t\tvrb_check_ir(q->d);\n+\n+\t/* Check if this is the last desc in batch (Atomic Queue). */\n+\tif (desc->req.last_desc_in_batch) {\n+\t\t(*aq_dequeued)++;\n+\t\tdesc->req.last_desc_in_batch = 0;\n+\t}\n+\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n+\tdesc->rsp.add_info_0 = 0;\n+\t*ref_op = op;\n+\n+\treturn descs_in_op;\n+}\n+\n+/* Dequeue MLDTS operations from VRB2 device. */\n+static uint16_t\n+vrb2_dequeue_mldts(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_mldts_op **ops, uint16_t num)\n+{\n+\tstruct acc_queue *q = q_data->queue_private;\n+\tuint16_t dequeue_num, i, dequeued_cbs = 0;\n+\tuint32_t avail = acc_ring_avail_deq(q);\n+\tuint32_t aq_dequeued = 0;\n+\tint ret;\n+\n+\tdequeue_num = RTE_MIN(avail, num);\n+\n+\tfor (i = 0; i < dequeue_num; ++i) {\n+\t\tret = dequeue_mldts_one_op(q_data, q, &ops[i], dequeued_cbs, &aq_dequeued);\n+\t\tif (ret <= 0)\n+\t\t\tbreak;\n+\t\tdequeued_cbs += ret;\n+\t}\n+\n+\tq->aq_dequeued += aq_dequeued;\n+\tq->sw_ring_tail += dequeued_cbs;\n+\t/* Update enqueue stats. */\n+\tq_data->queue_stats.dequeued_count += i;\n+\treturn i;\n+}\n+\n /* Initialization Function */\n static void\n vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n@@ -3924,6 +4296,8 @@ vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \tdev->dequeue_ldpc_dec_ops = vrb_dequeue_ldpc_dec;\n \tdev->enqueue_fft_ops = vrb_enqueue_fft;\n \tdev->dequeue_fft_ops = vrb_dequeue_fft;\n+\tdev->enqueue_mldts_ops = vrb2_enqueue_mldts;\n+\tdev->dequeue_mldts_ops = vrb2_dequeue_mldts;\n \n \td->pf_device = !strcmp(drv->driver.name, RTE_STR(VRB_PF_DRIVER_NAME));\n \td->mmio_base = pci_dev->mem_resource[0].addr;\n", "prefixes": [ "v4", "10/12" ] }