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GET /api/patches/13216/?format=api
{ "id": 13216, "url": "http://patches.dpdk.org/api/patches/13216/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1465250923-78695-13-git-send-email-stephen.hurd@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1465250923-78695-13-git-send-email-stephen.hurd@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1465250923-78695-13-git-send-email-stephen.hurd@broadcom.com", "date": "2016-06-06T22:08:17", "name": "[dpdk-dev,v4,13/39] bnxt: initial Tx code implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6eae9e5084c2561516d273cdd875d43cb09e7b81", "submitter": { "id": 438, "url": "http://patches.dpdk.org/api/people/438/?format=api", "name": "Stephen Hurd", "email": "stephen.hurd@broadcom.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1465250923-78695-13-git-send-email-stephen.hurd@broadcom.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/13216/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/13216/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0959B697A;\n\tTue, 7 Jun 2016 00:09:39 +0200 (CEST)", "from mail-gw1-out.broadcom.com (mail-gw1-out.broadcom.com\n\t[216.31.210.62]) by dpdk.org (Postfix) with ESMTP id D71E1377C\n\tfor <dev@dpdk.org>; Tue, 7 Jun 2016 00:09:28 +0200 (CEST)", "from mail-irv-18.broadcom.com ([10.15.198.37])\n\tby mail-gw1-out.broadcom.com with ESMTP; 06 Jun 2016 16:16:26 -0700", "from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com\n\t[10.11.16.101])\n\tby mail-irv-18.broadcom.com (Postfix) with ESMTP id C30B382026;\n\tMon, 6 Jun 2016 15:09:27 -0700 (PDT)", "from DPDK-C1.broadcom.com (dhcp-10-13-115-104.irv.broadcom.com\n\t[10.13.115.104])\n\tby mail-irva-12.broadcom.com (Postfix) with ESMTP id 571FA127636;\n\tMon, 6 Jun 2016 15:09:27 -0700 (PDT)" ], "X-IronPort-AV": "E=Sophos;i=\"5.26,429,1459839600\"; d=\"scan'208\";a=\"96627866\"", "From": "Stephen Hurd <stephen.hurd@broadcom.com>", "To": "dev@dpdk.org,\n\tajit.khaparde@broadcom.com,\n\tbruce.richardson@intel.com", "Date": "Mon, 6 Jun 2016 15:08:17 -0700", "Message-Id": "<1465250923-78695-13-git-send-email-stephen.hurd@broadcom.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com>", "References": "<1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com>", "Subject": "[dpdk-dev] [PATCH v4 13/39] bnxt: initial Tx code implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ajit Khaparde <ajit.khaparde@broadcom.com>\n\nInitial implementation of tx_pkt_burst for transmit.\nAdd code to allocate rings to bnxt_ring.c\nThis allows creation of rings in ASIC, which is used by the Tx function.\n\nv4:\nAddress review comments and fix issues pointed out by checkpatch.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: David Christensen <david.christensen@broadcom.com>\nSigned-off-by: Stephen Hurd <stephen.hurd@broadcom.com>\n---\n drivers/net/bnxt/Makefile | 1 +\n drivers/net/bnxt/bnxt_cpr.h | 4 +-\n drivers/net/bnxt/bnxt_ethdev.c | 3 +-\n drivers/net/bnxt/bnxt_ring.c | 145 ++++++++++\n drivers/net/bnxt/bnxt_ring.h | 8 +\n drivers/net/bnxt/bnxt_txq.c | 42 ++-\n drivers/net/bnxt/bnxt_txr.c | 314 ++++++++++++++++++++\n drivers/net/bnxt/bnxt_txr.h | 71 +++++\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 512 +++++++++++++++++++++++++++++++++\n 9 files changed, 1091 insertions(+), 9 deletions(-)\n create mode 100644 drivers/net/bnxt/bnxt_txr.c\n create mode 100644 drivers/net/bnxt/bnxt_txr.h", "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex f6a04f8..0785681 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -56,6 +56,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_ring.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxq.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_stats.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txr.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c\n \n #\ndiff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h\nindex e6333fc..f104281 100644\n--- a/drivers/net/bnxt/bnxt_cpr.h\n+++ b/drivers/net/bnxt/bnxt_cpr.h\n@@ -51,11 +51,11 @@\n \n #define B_CP_DB_REARM(cpr, raw_cons)\t\t\t\t\t\\\n \t\t(*(uint32_t *)((cpr)->cp_doorbell) = (DB_CP_REARM_FLAGS | \\\n-\t\t\t\tRING_CMP(&cpr->cp_ring_struct, raw_cons)))\n+\t\t\t\tRING_CMP(cpr->cp_ring_struct, raw_cons)))\n \n #define B_CP_DIS_DB(cpr, raw_cons)\t\t\t\t\t\\\n \t\t(*(uint32_t *)((cpr)->cp_doorbell) = (DB_CP_FLAGS |\t\\\n-\t\t\t\tRING_CMP(&cpr->cp_ring_struct, raw_cons)))\n+\t\t\t\tRING_CMP(cpr->cp_ring_struct, raw_cons)))\n \n struct bnxt_ring_struct;\n struct bnxt_cp_ring_info {\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 3453509..4ace543 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -44,6 +44,7 @@\n #include \"bnxt_rxq.h\"\n #include \"bnxt_stats.h\"\n #include \"bnxt_txq.h\"\n+#include \"bnxt_txr.h\"\n \n #define DRV_MODULE_NAME\t\t\"bnxt\"\n static const char bnxt_version[] =\n@@ -269,7 +270,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \teth_dev->dev_ops = &bnxt_dev_ops;\n \t/* eth_dev->rx_pkt_burst = &bnxt_recv_pkts; */\n-\t/* eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; */\n+\teth_dev->tx_pkt_burst = &bnxt_xmit_pkts;\n \n \trc = bnxt_alloc_hwrm_resources(bp);\n \tif (rc) {\ndiff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c\nindex d3b70cc..be77bbe 100644\n--- a/drivers/net/bnxt/bnxt_ring.c\n+++ b/drivers/net/bnxt/bnxt_ring.c\n@@ -31,8 +31,14 @@\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n \n+#include <rte_memzone.h>\n+\n #include \"bnxt.h\"\n+#include \"bnxt_cpr.h\"\n #include \"bnxt_ring.h\"\n+#include \"bnxt_txr.h\"\n+\n+#include \"hsi_struct_def_dpdk.h\"\n \n /*\n * Generic ring handling\n@@ -45,3 +51,142 @@ void bnxt_free_ring(struct bnxt_ring_struct *ring)\n \t\t*ring->vmem = NULL;\n \t}\n }\n+\n+/*\n+ * Allocates a completion ring with vmem and stats optionally also allocating\n+ * a TX and/or RX ring. Passing NULL as tx_ring_info and/or rx_ring_info\n+ * to not allocate them.\n+ *\n+ * Order in the allocation is:\n+ * stats - Always non-zero length\n+ * cp vmem - Always zero-length, supported for the bnxt_ring_struct abstraction\n+ * tx vmem - Only non-zero length if tx_ring_info is not NULL\n+ * rx vmem - Only non-zero length if rx_ring_info is not NULL\n+ * cp bd ring - Always non-zero length\n+ * tx bd ring - Only non-zero length if tx_ring_info is not NULL\n+ * rx bd ring - Only non-zero length if rx_ring_info is not NULL\n+ */\n+int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n+\t\t\t struct bnxt_tx_ring_info *tx_ring_info,\n+\t\t\t struct bnxt_rx_ring_info *rx_ring_info,\n+\t\t\t struct bnxt_cp_ring_info *cp_ring_info,\n+\t\t\t const char *suffix)\n+{\n+\tstruct bnxt_ring_struct *cp_ring = cp_ring_info->cp_ring_struct;\n+\tstruct bnxt_ring_struct *tx_ring;\n+\t/* TODO: RX ring */\n+\t/* struct bnxt_ring_struct *rx_ring; */\n+\tstruct rte_pci_device *pdev = bp->pdev;\n+\tconst struct rte_memzone *mz = NULL;\n+\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tint stats_len = (tx_ring_info || rx_ring_info) ?\n+\t RTE_CACHE_LINE_ROUNDUP(sizeof(struct ctx_hw_stats64)) : 0;\n+\n+\tint cp_vmem_start = stats_len;\n+\tint cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size);\n+\n+\tint tx_vmem_start = cp_vmem_start + cp_vmem_len;\n+\tint tx_vmem_len =\n+\t tx_ring_info ? RTE_CACHE_LINE_ROUNDUP(tx_ring_info->\n+\t\t\t\t\t\ttx_ring_struct->vmem_size) : 0;\n+\n+\tint rx_vmem_start = tx_vmem_start + tx_vmem_len;\n+\t/* TODO: RX ring */\n+\tint rx_vmem_len = 0;\n+\t/*\n+\t * rx_ring_info ? RTE_CACHE_LINE_ROUNDUP(rx_ring_info->\n+\t * rx_ring_struct->vmem_size) : 0;\n+\t */\n+\n+\tint cp_ring_start = rx_vmem_start + rx_vmem_len;\n+\tint cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size *\n+\t\t\t\t\t\t sizeof(struct cmpl_base));\n+\n+\tint tx_ring_start = cp_ring_start + cp_ring_len;\n+\tint tx_ring_len = tx_ring_info ?\n+\t RTE_CACHE_LINE_ROUNDUP(tx_ring_info->tx_ring_struct->ring_size *\n+\t\t\t\t sizeof(struct tx_bd_long)) : 0;\n+\n+\tint rx_ring_start = tx_ring_start + tx_ring_len;\n+\t/* TODO: RX ring */\n+\tint rx_ring_len = 0;\n+\t/*\n+\t * rx_ring_info ?\n+\t * RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size *\n+\t * sizeof(struct rx_prod_pkt_bd)) : 0;\n+\t */\n+\n+\tint total_alloc_len = rx_ring_start + rx_ring_len;\n+\n+\tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE,\n+\t\t \"bnxt_%04x:%02x:%02x:%02x-%04x_%s\", pdev->addr.domain,\n+\t\t pdev->addr.bus, pdev->addr.devid, pdev->addr.function, qidx,\n+\t\t suffix);\n+\tmz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;\n+\tmz = rte_memzone_lookup(mz_name);\n+\tif (!mz) {\n+\t\tmz = rte_memzone_reserve(mz_name, total_alloc_len,\n+\t\t\t\t\t SOCKET_ID_ANY,\n+\t\t\t\t\t RTE_MEMZONE_2MB |\n+\t\t\t\t\t RTE_MEMZONE_SIZE_HINT_ONLY);\n+\t\tif (mz == NULL)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\tmemset(mz->addr, 0, mz->len);\n+\n+\tif (tx_ring_info) {\n+\t\ttx_ring = tx_ring_info->tx_ring_struct;\n+\n+\t\ttx_ring->bd = ((char *)mz->addr + tx_ring_start);\n+\t\ttx_ring_info->tx_desc_ring = (struct tx_bd_long *)tx_ring->bd;\n+\t\ttx_ring->bd_dma = mz->phys_addr + tx_ring_start;\n+\t\ttx_ring_info->tx_desc_mapping = tx_ring->bd_dma;\n+\n+\t\tif (!tx_ring->bd)\n+\t\t\treturn -ENOMEM;\n+\t\tif (tx_ring->vmem_size) {\n+\t\t\ttx_ring->vmem =\n+\t\t\t (void **)((char *)mz->addr + tx_vmem_start);\n+\t\t\ttx_ring_info->tx_buf_ring =\n+\t\t\t (struct bnxt_sw_tx_bd *)tx_ring->vmem;\n+\t\t}\n+\t}\n+\n+/*\n+ *\tif (rx_ring_info) {\n+ *\t\trx_ring = &rx_ring_info->rx_ring_struct;\n+ *\n+ *\t\trx_ring->bd = ((char *)mz->addr + rx_ring_start);\n+ *\t\trx_ring_info->rx_desc_ring =\n+ *\t\t (struct rx_prod_pkt_bd *)rx_ring->bd;\n+ *\t\trx_ring->bd_dma = mz->phys_addr + rx_ring_start;\n+ *\t\trx_ring_info->rx_desc_mapping = rx_ring->bd_dma;\n+ *\n+ *\t\tif (!rx_ring->bd)\n+ *\t\t\treturn -ENOMEM;\n+ *\t\tif (rx_ring->vmem_size) {\n+ *\t\t\trx_ring->vmem =\n+ *\t\t\t (void **)((char *)mz->addr + rx_vmem_start);\n+ *\t\t\trx_ring_info->rx_buf_ring =\n+ *\t\t\t (struct bnxt_sw_rx_bd *)rx_ring->vmem;\n+ *\t\t}\n+ *\t}\n+ */\n+\n+\tcp_ring->bd = ((char *)mz->addr + cp_ring_start);\n+\tcp_ring->bd_dma = mz->phys_addr + cp_ring_start;\n+\tcp_ring_info->cp_desc_ring = cp_ring->bd;\n+\tcp_ring_info->cp_desc_mapping = cp_ring->bd_dma;\n+\n+\tif (!cp_ring->bd)\n+\t\treturn -ENOMEM;\n+\tif (cp_ring->vmem_size)\n+\t\t*cp_ring->vmem = ((char *)mz->addr + stats_len);\n+\tif (stats_len) {\n+\t\tcp_ring_info->hw_stats = mz->addr;\n+\t\tcp_ring_info->hw_stats_map = mz->phys_addr;\n+\t}\n+\tcp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;\n+\treturn 0;\n+}\ndiff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h\nindex ebbd759..281587c 100644\n--- a/drivers/net/bnxt/bnxt_ring.h\n+++ b/drivers/net/bnxt/bnxt_ring.h\n@@ -87,6 +87,14 @@ struct bnxt_ring_grp_info {\n };\n \n struct bnxt;\n+struct bnxt_tx_ring_info;\n+struct bnxt_rx_ring_info;\n+struct bnxt_cp_ring_info;\n void bnxt_free_ring(struct bnxt_ring_struct *ring);\n+int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n+\t\t\t struct bnxt_tx_ring_info *tx_ring_info,\n+\t\t\t struct bnxt_rx_ring_info *rx_ring_info,\n+\t\t\t struct bnxt_cp_ring_info *cp_ring_info,\n+\t\t\t const char *suffix);\n \n #endif\ndiff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c\nindex a3648c2..7aba199 100644\n--- a/drivers/net/bnxt/bnxt_txq.c\n+++ b/drivers/net/bnxt/bnxt_txq.c\n@@ -39,6 +39,7 @@\n #include \"bnxt_cpr.h\"\n #include \"bnxt_ring.h\"\n #include \"bnxt_txq.h\"\n+#include \"bnxt_txr.h\"\n \n /*\n * TX Queues\n@@ -55,9 +56,20 @@ void bnxt_free_txq_stats(struct bnxt_tx_queue *txq)\n \t\tcpr->hw_stats = NULL;\n }\n \n-static void bnxt_tx_queue_release_mbufs(struct bnxt_tx_queue *txq __rte_unused)\n+static void bnxt_tx_queue_release_mbufs(struct bnxt_tx_queue *txq)\n {\n-\t/* TODO: Requires interaction with TX ring */\n+\tstruct bnxt_sw_tx_bd *sw_ring;\n+\tuint16_t i;\n+\n+\tsw_ring = txq->tx_ring->tx_buf_ring;\n+\tif (sw_ring) {\n+\t\tfor (i = 0; i < txq->tx_ring->tx_ring_struct->ring_size; i++) {\n+\t\t\tif (sw_ring[i].mbuf) {\n+\t\t\t\trte_pktmbuf_free(sw_ring[i].mbuf);\n+\t\t\t\tsw_ring[i].mbuf = NULL;\n+\t\t\t}\n+\t\t}\n+\t}\n }\n \n void bnxt_free_tx_mbufs(struct bnxt *bp)\n@@ -76,7 +88,15 @@ void bnxt_tx_queue_release_op(void *tx_queue)\n \tstruct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;\n \n \tif (txq) {\n-\t\t/* TODO: Free ring and stats here */\n+\t\t/* Free TX ring hardware descriptors */\n+\t\tbnxt_tx_queue_release_mbufs(txq);\n+\t\tbnxt_free_ring(txq->tx_ring->tx_ring_struct);\n+\n+\t\t/* Free TX completion ring hardware descriptors */\n+\t\tbnxt_free_ring(txq->cp_ring->cp_ring_struct);\n+\n+\t\tbnxt_free_txq_stats(txq);\n+\n \t\trte_free(txq);\n \t}\n }\n@@ -112,14 +132,24 @@ int bnxt_tx_queue_setup_op(struct rte_eth_dev *eth_dev,\n \ttxq->nb_tx_desc = nb_desc;\n \ttxq->tx_free_thresh = tx_conf->tx_free_thresh;\n \n-\t/* TODO: Initialize ring structure */\n+\tbnxt_init_tx_ring_struct(txq);\n \n \ttxq->queue_id = queue_idx;\n \ttxq->port_id = eth_dev->data->port_id;\n \n-\t/* TODO: Allocate TX ring hardware descriptors */\n+\t/* Allocate TX ring hardware descriptors */\n+\tif (bnxt_alloc_rings(bp, queue_idx, txq->tx_ring, NULL, txq->cp_ring,\n+\t\t\t\"bnxt_tx_ring\")) {\n+\t\tRTE_LOG(ERR, PMD, \"ring_dma_zone_reserve for tx_ring failed!\");\n+\t\tbnxt_tx_queue_release_op(txq);\n+\t\treturn -ENOMEM;\n+\t}\n \n-\t/* TODO: Initialize the ring */\n+\tif (bnxt_init_one_tx_ring(txq)) {\n+\t\tRTE_LOG(ERR, PMD, \"bnxt_init_one_tx_ring failed!\");\n+\t\tbnxt_tx_queue_release_op(txq);\n+\t\treturn -ENOMEM;\n+\t}\n \n \teth_dev->data->tx_queues[queue_idx] = txq;\n \treturn 0;\ndiff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c\nnew file mode 100644\nindex 0000000..2314410\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_txr.c\n@@ -0,0 +1,314 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_byteorder.h>\n+#include <rte_malloc.h>\n+\n+#include \"bnxt.h\"\n+#include \"bnxt_cpr.h\"\n+#include \"bnxt_ring.h\"\n+#include \"bnxt_txq.h\"\n+#include \"bnxt_txr.h\"\n+#include \"hsi_struct_def_dpdk.h\"\n+#include <stdbool.h>\n+\n+/*\n+ * TX Ring handling\n+ */\n+\n+void bnxt_free_tx_rings(struct bnxt *bp)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < (int)bp->tx_nr_rings; i++) {\n+\t\tstruct bnxt_tx_queue *txq = bp->tx_queues[i];\n+\n+\t\tif (!txq)\n+\t\t\tcontinue;\n+\n+\t\tbnxt_free_ring(txq->tx_ring->tx_ring_struct);\n+\t\t/* TODO: free() txq->tx_ring and txq->tx_ring->tx_ring_struct */\n+\t\tbnxt_free_ring(txq->cp_ring->cp_ring_struct);\n+\t\t/* TODO: free() txq->cp_ring and txq->cp_ring->cp_ring_struct */\n+\n+\t\trte_free(txq);\n+\t\tbp->tx_queues[i] = NULL;\n+\t}\n+}\n+\n+int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq)\n+{\n+\tstruct bnxt_tx_ring_info *txr = txq->tx_ring;\n+\tstruct bnxt_ring_struct *ring = txr->tx_ring_struct;\n+\n+\ttxq->tx_wake_thresh = ring->ring_size / 2;\n+\tring->fw_ring_id = INVALID_HW_RING_ID;\n+\n+\treturn 0;\n+}\n+\n+void bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq)\n+{\n+\tstruct bnxt_cp_ring_info *cpr;\n+\tstruct bnxt_tx_ring_info *txr;\n+\tstruct bnxt_ring_struct *ring;\n+\n+\t/* TODO: These need to be allocated */\n+\ttxr = txq->tx_ring;\n+\tring = txr->tx_ring_struct;\n+\tring->ring_size = rte_align32pow2(txq->nb_tx_desc + 1);\n+\tring->ring_mask = ring->ring_size - 1;\n+\tring->bd = (void *)txr->tx_desc_ring;\n+\tring->bd_dma = txr->tx_desc_mapping;\n+\tring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_tx_bd);\n+\tring->vmem = (void **)&txr->tx_buf_ring;\n+\n+\t/* TODO: These need to be allocated */\n+\tcpr = txq->cp_ring;\n+\tring = cpr->cp_ring_struct;\n+\tring->ring_size = txr->tx_ring_struct->ring_size;\n+\tring->ring_mask = ring->ring_size - 1;\n+\tring->bd = (void *)cpr->cp_desc_ring;\n+\tring->bd_dma = cpr->cp_desc_mapping;\n+\tring->vmem_size = 0;\n+\tring->vmem = NULL;\n+}\n+\n+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_ring_info *txr)\n+{\n+\t/* Tell compiler to fetch tx indices from memory. */\n+\trte_compiler_barrier();\n+\n+\treturn txr->tx_ring_struct->ring_size -\n+\t\t((txr->tx_prod - txr->tx_cons) &\n+\t\t\ttxr->tx_ring_struct->ring_mask) - 1;\n+}\n+\n+static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n+\t\t\t\tstruct bnxt_tx_queue *txq)\n+{\n+\tstruct bnxt_tx_ring_info *txr = txq->tx_ring;\n+\tstruct tx_bd_long *txbd;\n+\tstruct tx_bd_long_hi *txbd1;\n+\tuint32_t vlan_tag_flags, cfa_action;\n+\tbool long_bd = false;\n+\tuint16_t last_prod = 0;\n+\tstruct rte_mbuf *m_seg;\n+\tstruct bnxt_sw_tx_bd *tx_buf;\n+\tstatic const uint32_t lhint_arr[4] = {\n+\t\tTX_BD_LONG_FLAGS_LHINT_LT512,\n+\t\tTX_BD_LONG_FLAGS_LHINT_LT1K,\n+\t\tTX_BD_LONG_FLAGS_LHINT_LT2K,\n+\t\tTX_BD_LONG_FLAGS_LHINT_LT2K\n+\t};\n+\n+\tif (tx_pkt->ol_flags & (PKT_TX_TCP_SEG | PKT_TX_TCP_CKSUM |\n+\t\t\t\tPKT_TX_UDP_CKSUM | PKT_TX_IP_CKSUM |\n+\t\t\t\tPKT_TX_VLAN_PKT))\n+\t\tlong_bd = true;\n+\n+\ttx_buf = &txr->tx_buf_ring[txr->tx_prod];\n+\ttx_buf->mbuf = tx_pkt;\n+\ttx_buf->nr_bds = long_bd + tx_pkt->nb_segs;\n+\tlast_prod = (txr->tx_prod + tx_buf->nr_bds - 1) &\n+\t\t\t\ttxr->tx_ring_struct->ring_mask;\n+\n+\tif (unlikely(bnxt_tx_avail(txr) < tx_buf->nr_bds))\n+\t\treturn -ENOMEM;\n+\n+\ttxbd = &txr->tx_desc_ring[txr->tx_prod];\n+\ttxbd->opaque = txr->tx_prod;\n+\ttxbd->flags_type = tx_buf->nr_bds << TX_BD_LONG_FLAGS_BD_CNT_SFT;\n+\ttxbd->len = tx_pkt->data_len;\n+\tif (txbd->len >= 2014)\n+\t\ttxbd->flags_type |= TX_BD_LONG_FLAGS_LHINT_GTE2K;\n+\telse\n+\t\ttxbd->flags_type |= lhint_arr[txbd->len >> 9];\n+\ttxbd->addr = rte_cpu_to_le_32(RTE_MBUF_DATA_DMA_ADDR(tx_buf->mbuf));\n+\n+\tif (long_bd) {\n+\t\ttxbd->flags_type |= TX_BD_LONG_TYPE_TX_BD_LONG;\n+\t\tvlan_tag_flags = 0;\n+\t\tcfa_action = 0;\n+\t\tif (tx_buf->mbuf->ol_flags & PKT_TX_VLAN_PKT) {\n+\t\t\t/* shurd: Should this mask at\n+\t\t\t * TX_BD_LONG_CFA_META_VLAN_VID_MASK?\n+\t\t\t */\n+\t\t\tvlan_tag_flags = TX_BD_LONG_CFA_META_KEY_VLAN_TAG |\n+\t\t\t\ttx_buf->mbuf->vlan_tci;\n+\t\t\t/* Currently supports 8021Q, 8021AD vlan offloads\n+\t\t\t * QINQ1, QINQ2, QINQ3 vlan headers are deprecated\n+\t\t\t */\n+\t\t\t/* DPDK only supports 802.11q VLAN packets */\n+\t\t\tvlan_tag_flags |=\n+\t\t\t\t\tTX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;\n+\t\t}\n+\n+\t\ttxr->tx_prod = RING_NEXT(txr->tx_ring_struct, txr->tx_prod);\n+\n+\t\ttxbd1 = (struct tx_bd_long_hi *)\n+\t\t\t\t\t&txr->tx_desc_ring[txr->tx_prod];\n+\t\ttxbd1->lflags = 0;\n+\t\ttxbd1->cfa_meta = vlan_tag_flags;\n+\t\ttxbd1->cfa_action = cfa_action;\n+\n+\t\tif (tx_pkt->ol_flags & PKT_TX_TCP_SEG) {\n+\t\t\t/* TSO */\n+\t\t\ttxbd1->lflags = TX_BD_LONG_LFLAGS_LSO;\n+\t\t\ttxbd1->hdr_size = tx_pkt->l2_len + tx_pkt->l3_len +\n+\t\t\t\t\ttx_pkt->l4_len;\n+\t\t\ttxbd1->mss = tx_pkt->tso_segsz;\n+\n+\t\t} else if (tx_pkt->ol_flags & (PKT_TX_TCP_CKSUM |\n+\t\t\t\t\tPKT_TX_UDP_CKSUM)) {\n+\t\t\t/* TCP/UDP CSO */\n+\t\t\ttxbd1->lflags = TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;\n+\t\t\ttxbd1->mss = 0;\n+\n+\t\t} else if (tx_pkt->ol_flags & PKT_TX_IP_CKSUM) {\n+\t\t\t/* IP CSO */\n+\t\t\ttxbd1->lflags = TX_BD_LONG_LFLAGS_IP_CHKSUM;\n+\t\t\ttxbd1->mss = 0;\n+\t\t}\n+\t} else {\n+\t\ttxbd->flags_type |= TX_BD_SHORT_TYPE_TX_BD_SHORT;\n+\t}\n+\n+\tm_seg = tx_pkt->next;\n+\t/* i is set at the end of the if(long_bd) block */\n+\twhile (txr->tx_prod != last_prod) {\n+\t\ttxr->tx_prod = RING_NEXT(txr->tx_ring_struct, txr->tx_prod);\n+\t\ttx_buf = &txr->tx_buf_ring[txr->tx_prod];\n+\n+\t\ttxbd = &txr->tx_desc_ring[txr->tx_prod];\n+\t\ttxbd->addr = rte_cpu_to_le_32(RTE_MBUF_DATA_DMA_ADDR(m_seg));\n+\t\ttxbd->flags_type = TX_BD_SHORT_TYPE_TX_BD_SHORT;\n+\t\ttxbd->len = m_seg->data_len;\n+\n+\t\tm_seg = m_seg->next;\n+\t}\n+\n+\ttxbd->flags_type |= TX_BD_LONG_FLAGS_PACKET_END;\n+\n+\ttxr->tx_prod = RING_NEXT(txr->tx_ring_struct, txr->tx_prod);\n+\n+\treturn 0;\n+}\n+\n+static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nr_pkts)\n+{\n+\tstruct bnxt_tx_ring_info *txr = txq->tx_ring;\n+\tuint16_t cons = txr->tx_cons;\n+\tint i, j;\n+\n+\tfor (i = 0; i < nr_pkts; i++) {\n+\t\tstruct bnxt_sw_tx_bd *tx_buf;\n+\t\tstruct rte_mbuf *mbuf;\n+\n+\t\ttx_buf = &txr->tx_buf_ring[cons];\n+\t\tcons = RING_NEXT(txr->tx_ring_struct, cons);\n+\t\tmbuf = tx_buf->mbuf;\n+\t\ttx_buf->mbuf = NULL;\n+\n+\t\t/* EW - no need to unmap DMA memory? */\n+\n+\t\tfor (j = 1; j < tx_buf->nr_bds; j++)\n+\t\t\tcons = RING_NEXT(txr->tx_ring_struct, cons);\n+\t\trte_pktmbuf_free(mbuf);\n+\t}\n+\n+\ttxr->tx_cons = cons;\n+}\n+\n+static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq)\n+{\n+\tstruct bnxt_cp_ring_info *cpr = txq->cp_ring;\n+\tuint32_t raw_cons = cpr->cp_raw_cons;\n+\tuint32_t cons;\n+\tint nb_tx_pkts = 0;\n+\tstruct tx_cmpl *txcmp;\n+\n+\tif ((txq->tx_ring->tx_ring_struct->ring_size -\n+\t\t\t(bnxt_tx_avail(txq->tx_ring))) >\n+\t\t\ttxq->tx_free_thresh) {\n+\t\twhile (1) {\n+\t\t\tcons = RING_CMP(cpr->cp_ring_struct, raw_cons);\n+\t\t\ttxcmp = (struct tx_cmpl *)&cpr->cp_desc_ring[cons];\n+\n+\t\t\tif (!CMP_VALID(txcmp, raw_cons, cpr->cp_ring_struct))\n+\t\t\t\tbreak;\n+\n+\t\t\tif (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)\n+\t\t\t\tnb_tx_pkts++;\n+\t\t\telse\n+\t\t\t\tRTE_LOG(DEBUG, PMD,\n+\t\t\t\t\t\t\"Unhandled CMP type %02x\\n\",\n+\t\t\t\t\t\tCMP_TYPE(txcmp));\n+\t\t\traw_cons = NEXT_RAW_CMP(raw_cons);\n+\t\t}\n+\t\tif (nb_tx_pkts)\n+\t\t\tbnxt_tx_cmp(txq, nb_tx_pkts);\n+\t\tcpr->cp_raw_cons = raw_cons;\n+\t\tB_CP_DIS_DB(cpr, cpr->cp_raw_cons);\n+\t}\n+\treturn nb_tx_pkts;\n+}\n+\n+uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct bnxt_tx_queue *txq = tx_queue;\n+\tuint16_t nb_tx_pkts = 0;\n+\tuint16_t db_mask = txq->tx_ring->tx_ring_struct->ring_size >> 2;\n+\tuint16_t last_db_mask = 0;\n+\n+\t/* Handle TX completions */\n+\tbnxt_handle_tx_cp(txq);\n+\n+\t/* Handle TX burst request */\n+\tfor (nb_tx_pkts = 0; nb_tx_pkts < nb_pkts; nb_tx_pkts++) {\n+\t\tif (bnxt_start_xmit(tx_pkts[nb_tx_pkts], txq)) {\n+\t\t\tbreak;\n+\t\t} else if ((nb_tx_pkts & db_mask) != last_db_mask) {\n+\t\t\tB_TX_DB(txq->tx_ring->tx_doorbell,\n+\t\t\t\t\ttxq->tx_ring->tx_prod);\n+\t\t\tlast_db_mask = nb_tx_pkts & db_mask;\n+\t\t}\n+\t}\n+\tif (nb_tx_pkts)\n+\t\tB_TX_DB(txq->tx_ring->tx_doorbell, txq->tx_ring->tx_prod);\n+\n+\treturn nb_tx_pkts;\n+}\ndiff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h\nnew file mode 100644\nindex 0000000..1797a3d\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_txr.h\n@@ -0,0 +1,71 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _BNXT_TXR_H_\n+#define _BNXT_TXR_H_\n+\n+#define MAX_TX_RINGS\t16\n+#define BNXT_TX_PUSH_THRESH 92\n+\n+#define B_TX_DB(db, prod)\t\t\t\t\t\t\\\n+\t\t(*(uint32_t *)db = (DB_KEY_TX | prod))\n+\n+struct bnxt_tx_ring_info {\n+\tuint16_t\t\ttx_prod;\n+\tuint16_t\t\ttx_cons;\n+\tvoid\t\t\t*tx_doorbell;\n+\n+\tstruct tx_bd_long\t*tx_desc_ring;\n+\tstruct bnxt_sw_tx_bd\t*tx_buf_ring;\n+\n+\tphys_addr_t\t\ttx_desc_mapping;\n+\n+#define BNXT_DEV_STATE_CLOSING\t0x1\n+\tuint32_t\t\tdev_state;\n+\n+\tstruct bnxt_ring_struct\t*tx_ring_struct;\n+};\n+\n+struct bnxt_sw_tx_bd {\n+\tstruct rte_mbuf\t\t*mbuf; /* mbuf associated with TX descriptor */\n+\tuint8_t\t\t\tis_gso;\n+\tunsigned short\t\tnr_bds;\n+};\n+\n+void bnxt_free_tx_rings(struct bnxt *bp);\n+int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);\n+void bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq);\n+uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+\n+#endif\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 91a83d1..1543f20 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -99,6 +99,518 @@ struct ctx_hw_stats64 {\n #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))\n #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))\n \n+/* Short TX BD (16 bytes) */\n+struct tx_bd_short {\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Only the packet_end bit must be valid for the remaining BDs of a\n+\t * packet.\n+\t */\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define TX_BD_SHORT_TYPE_MASK\t\t\tUINT32_C(0x3f)\n+\t#define TX_BD_SHORT_TYPE_SFT\t\t\t0\n+\t\t/*\n+\t\t * Indicates that this BD is 16B long and is used for normal L2\n+\t\t * packet transmission.\n+\t\t */\n+\t#define TX_BD_SHORT_TYPE_TX_BD_SHORT\t\t(UINT32_C(0x0) << 0)\n+\t/*\n+\t * If set to 1, the packet ends with the data in the buffer pointed to\n+\t * by this descriptor. This flag must be valid on every BD.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_PACKET_END\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, the device will not generate a completion for this\n+\t * transmit packet unless there is an error in it's processing. If this\n+\t * bit is set to 0, then the packet will be completed normally. This bit\n+\t * must be valid only on the first BD of a packet.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_NO_CMPL\t\tUINT32_C(0x80)\n+\t/*\n+\t * This value indicates how many 16B BD locations are consumed in the\n+\t * ring by this packet. A value of 1 indicates that this BD is the only\n+\t * BD (and that the it is a short BD). A value of 3 indicates either 3\n+\t * short BDs or 1 long BD and one short BD in the packet. A value of 0\n+\t * indicates that there are 32 BD locations in the packet (the maximum).\n+\t * This field is valid only on the first BD of a packet.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_BD_CNT_MASK\t\tUINT32_C(0x1f00)\n+\t#define TX_BD_SHORT_FLAGS_BD_CNT_SFT\t\t8\n+\t/*\n+\t * This value is a hint for the length of the entire packet. It is used\n+\t * by the chip to optimize internal processing. The packet will be\n+\t * dropped if the hint is too short. This field is valid only on the\n+\t * first BD of a packet.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_LHINT_MASK\t\tUINT32_C(0x6000)\n+\t#define TX_BD_SHORT_FLAGS_LHINT_SFT\t\t13\n+\t\t/* indicates packet length < 512B */\n+\t#define TX_BD_SHORT_FLAGS_LHINT_LT512\t\t(UINT32_C(0x0) << 13)\n+\t\t/* indicates 512 <= packet length < 1KB */\n+\t#define TX_BD_SHORT_FLAGS_LHINT_LT1K\t\t(UINT32_C(0x1) << 13)\n+\t\t/* indicates 1KB <= packet length < 2KB */\n+\t#define TX_BD_SHORT_FLAGS_LHINT_LT2K\t\t(UINT32_C(0x2) << 13)\n+\t\t/* indicates packet length >= 2KB */\n+\t#define TX_BD_SHORT_FLAGS_LHINT_GTE2K\t\t(UINT32_C(0x3) << 13)\n+\t#define TX_BD_SHORT_FLAGS_LHINT_LAST\tTX_BD_SHORT_FLAGS_LHINT_GTE2K\n+\t/*\n+\t * If set to 1, the device immediately updates the Send Consumer Index\n+\t * after the buffer associated with this descriptor has been transferred\n+\t * via DMA to NIC memory from host memory. An interrupt may or may not\n+\t * be generated according to the state of the interrupt avoidance\n+\t * mechanisms. If this bit is set to 0, then the Consumer Index is only\n+\t * updated as soon as one of the host interrupt coalescing conditions\n+\t * has been met. This bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_COAL_NOW\t\tUINT32_C(0x8000)\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Only the packet_end bit must be valid for the remaining BDs of a\n+\t * packet.\n+\t */\n+\t#define TX_BD_SHORT_FLAGS_MASK\t\t\tUINT32_C(0xffc0)\n+\t#define TX_BD_SHORT_FLAGS_SFT\t\t\t6\n+\tuint16_t flags_type;\n+\n+\t/*\n+\t * This is the length of the host physical buffer this BD describes in\n+\t * bytes. This field must be valid on all BDs of a packet.\n+\t */\n+\tuint16_t len;\n+\t/*\n+\t * The opaque data field is pass through to the completion and can be\n+\t * used for any data that the driver wants to associate with the\n+\t * transmit BD. This field must be valid on the first BD of a packet.\n+\t */\n+\tuint32_t opaque;\n+\n+\t/*\n+\t * This is the host physical address for the portion of the packet\n+\t * described by this TX BD. This value must be valid on all BDs of a\n+\t * packet.\n+\t */\n+\tuint64_t addr;\n+} __attribute__((packed));\n+\n+/* Long TX BD (32 bytes split to 2 16-byte struct) */\n+struct tx_bd_long {\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Only the packet_end bit must be valid for the remaining BDs of a\n+\t * packet.\n+\t */\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define TX_BD_LONG_TYPE_MASK\t\t\tUINT32_C(0x3f)\n+\t#define TX_BD_LONG_TYPE_SFT\t\t\t0\n+\t\t/*\n+\t\t * Indicates that this BD is 32B long and is used for normal L2\n+\t\t * packet transmission.\n+\t\t */\n+\t#define TX_BD_LONG_TYPE_TX_BD_LONG\t\t(UINT32_C(0x10) << 0)\n+\t/*\n+\t * If set to 1, the packet ends with the data in the buffer pointed to\n+\t * by this descriptor. This flag must be valid on every BD.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_PACKET_END\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, the device will not generate a completion for this\n+\t * transmit packet unless there is an error in it's processing. If this\n+\t * bit is set to 0, then the packet will be completed normally. This bit\n+\t * must be valid only on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_NO_CMPL\t\tUINT32_C(0x80)\n+\t/*\n+\t * This value indicates how many 16B BD locations are consumed in the\n+\t * ring by this packet. A value of 1 indicates that this BD is the only\n+\t * BD (and that the it is a short BD). A value of 3 indicates either 3\n+\t * short BDs or 1 long BD and one short BD in the packet. A value of 0\n+\t * indicates that there are 32 BD locations in the packet (the maximum).\n+\t * This field is valid only on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_BD_CNT_MASK\t\tUINT32_C(0x1f00)\n+\t#define TX_BD_LONG_FLAGS_BD_CNT_SFT\t\t8\n+\t/*\n+\t * This value is a hint for the length of the entire packet. It is used\n+\t * by the chip to optimize internal processing. The packet will be\n+\t * dropped if the hint is too short. This field is valid only on the\n+\t * first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_LHINT_MASK\t\tUINT32_C(0x6000)\n+\t#define TX_BD_LONG_FLAGS_LHINT_SFT\t\t13\n+\t\t/* indicates packet length < 512B */\n+\t#define TX_BD_LONG_FLAGS_LHINT_LT512\t\t(UINT32_C(0x0) << 13)\n+\t\t/* indicates 512 <= packet length < 1KB */\n+\t#define TX_BD_LONG_FLAGS_LHINT_LT1K\t\t(UINT32_C(0x1) << 13)\n+\t\t/* indicates 1KB <= packet length < 2KB */\n+\t#define TX_BD_LONG_FLAGS_LHINT_LT2K\t\t(UINT32_C(0x2) << 13)\n+\t\t/* indicates packet length >= 2KB */\n+\t#define TX_BD_LONG_FLAGS_LHINT_GTE2K\t\t(UINT32_C(0x3) << 13)\n+\t#define TX_BD_LONG_FLAGS_LHINT_LAST\tTX_BD_LONG_FLAGS_LHINT_GTE2K\n+\t/*\n+\t * If set to 1, the device immediately updates the Send Consumer Index\n+\t * after the buffer associated with this descriptor has been transferred\n+\t * via DMA to NIC memory from host memory. An interrupt may or may not\n+\t * be generated according to the state of the interrupt avoidance\n+\t * mechanisms. If this bit is set to 0, then the Consumer Index is only\n+\t * updated as soon as one of the host interrupt coalescing conditions\n+\t * has been met. This bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_COAL_NOW\t\tUINT32_C(0x8000)\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Only the packet_end bit must be valid for the remaining BDs of a\n+\t * packet.\n+\t */\n+\t#define TX_BD_LONG_FLAGS_MASK\t\t\tUINT32_C(0xffc0)\n+\t#define TX_BD_LONG_FLAGS_SFT\t\t\t6\n+\tuint16_t flags_type;\n+\n+\t/*\n+\t * This is the length of the host physical buffer this BD describes in\n+\t * bytes. This field must be valid on all BDs of a packet.\n+\t */\n+\tuint16_t len;\n+\n+\t/*\n+\t * The opaque data field is pass through to the completion and can be\n+\t * used for any data that the driver wants to associate with the\n+\t * transmit BD. This field must be valid on the first BD of a packet.\n+\t */\n+\tuint32_t opaque;\n+\n+\t/*\n+\t * This is the host physical address for the portion of the packet\n+\t * described by this TX BD. This value must be valid on all BDs of a\n+\t * packet.\n+\t */\n+\tuint64_t addr;\n+} __attribute__((packed));\n+\n+/* last 16 bytes of Long TX BD */\n+\n+struct tx_bd_long_hi {\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Their value on other BDs of the packet will be ignored.\n+\t */\n+\t/*\n+\t * If set to 1, the controller replaces the TCP/UPD checksum fields of\n+\t * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the\n+\t * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP\n+\t * checksum for the packet associated with this descriptor. This bit\n+\t * must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, the controller replaces the IP checksum of the normal\n+\t * packets, or the inner IP checksum of the encapsulated packets with\n+\t * the hardware calculated IP checksum for the packet associated with\n+\t * this descriptor. This bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_IP_CHKSUM\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, the controller will not append an Ethernet CRC to the\n+\t * end of the frame. This bit must be valid on the first BD of a packet.\n+\t * Packet must be 64B or longer when this flag is set. It is not useful\n+\t * to use this bit with any form of TX offload such as CSO or LSO. The\n+\t * intent is that the packet from the host already has a valid Ethernet\n+\t * CRC on the packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_NOCRC\t\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, the device will record the time at which the packet was\n+\t * actually transmitted at the TX MAC. This bit must be valid on the\n+\t * first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_STAMP\t\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, The controller replaces the tunnel IP checksum field\n+\t * with hardware calculated IP checksum for the IP header of the packet\n+\t * associated with this descriptor. In case of VXLAN, the controller\n+\t * also replaces the outer header UDP checksum with hardware calculated\n+\t * UDP checksum for the packet associated with this descriptor.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM\t\tUINT32_C(0x10)\n+\t/*\n+\t * If set to 1, the device will treat this packet with LSO(Large Send\n+\t * Offload) processing for both normal or encapsulated packets, which is\n+\t * a form of TCP segmentation. When this bit is 1, the hdr_size and mss\n+\t * fields must be valid. The driver doesn't need to set t_ip_chksum,\n+\t * ip_chksum, and tcp_udp_chksum flags since the controller will replace\n+\t * the appropriate checksum fields for segmented packets. When this bit\n+\t * is 1, the hdr_size and mss fields must be valid.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_LSO\t\t\tUINT32_C(0x20)\n+\t/*\n+\t * If set to zero when LSO is '1', then the IPID will be treated as a\n+\t * 16b number and will be wrapped if it exceeds a value of 0xffff. If\n+\t * set to one when LSO is '1', then the IPID will be treated as a 15b\n+\t * number and will be wrapped if it exceeds a value 0f 0x7fff.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_IPID_FMT\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to zero when LSO is '1', then the IPID of the tunnel IP header\n+\t * will not be modified during LSO operations. If set to one when LSO is\n+\t * '1', then the IPID of the tunnel IP header will be incremented for\n+\t * each subsequent segment of an LSO operation.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_T_IPID\t\tUINT32_C(0x80)\n+\t/*\n+\t * If set to '1', then the RoCE ICRC will be appended to the packet.\n+\t * Packet must be a valid RoCE format packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_ROCE_CRC\t\tUINT32_C(0x100)\n+\t/*\n+\t * If set to '1', then the FCoE CRC will be appended to the packet.\n+\t * Packet must be a valid FCoE format packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_FCOE_CRC\t\tUINT32_C(0x200)\n+\tuint16_t lflags;\n+\n+\t/*\n+\t * When LSO is '1', this field must contain the offset of the TCP\n+\t * payload from the beginning of the packet in as 16b words. In case of\n+\t * encapsulated/tunneling packet, this field contains the offset of the\n+\t * inner TCP payload from beginning of the packet as 16-bit words. This\n+\t * value must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_HDR_SIZE_MASK\t\tUINT32_C(0x1ff)\n+\t#define TX_BD_LONG_HDR_SIZE_SFT\t\t\t0\n+\tuint16_t hdr_size;\n+\n+\t/*\n+\t * This is the MSS value that will be used to do the LSO processing. The\n+\t * value is the length in bytes of the TCP payload for each segment\n+\t * generated by the LSO operation. This value must be valid on the first\n+\t * BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_MSS_MASK\t\t\tUINT32_C(0x7fff)\n+\t#define TX_BD_LONG_MSS_SFT\t\t\t0\n+\tuint32_t mss;\n+\n+\tuint16_t unused_2;\n+\n+\t/*\n+\t * This value selects a CFA action to perform on the packet. Set this\n+\t * value to zero if no CFA action is desired. This value must be valid\n+\t * on the first BD of a packet.\n+\t */\n+\tuint16_t cfa_action;\n+\n+\t/*\n+\t * This value is action meta-data that defines CFA edit operations that\n+\t * are done in addition to any action editing.\n+\t */\n+\t/* When key=1, This is the VLAN tag VID value. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_VID_MASK\tUINT32_C(0xfff)\n+\t#define TX_BD_LONG_CFA_META_VLAN_VID_SFT\t0\n+\t/* When key=1, This is the VLAN tag DE value. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_DE\t\tUINT32_C(0x1000)\n+\t/* When key=1, This is the VLAN tag PRI value. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK\tUINT32_C(0xe000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_PRI_SFT\t13\n+\t/* When key=1, This is the VLAN tag TPID select value. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK\tUINT32_C(0x70000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_SFT\t16\n+\t\t/* 0x88a8 */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8\t(UINT32_C(0x0) << 16)\n+\t\t/* 0x8100 */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100\t(UINT32_C(0x1) << 16)\n+\t\t/* 0x9100 */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100\t(UINT32_C(0x2) << 16)\n+\t\t/* 0x9200 */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200\t(UINT32_C(0x3) << 16)\n+\t\t/* 0x9300 */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300\t(UINT32_C(0x4) << 16)\n+\t\t/* Value programmed in CFA VLANTPID register. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG\t(UINT32_C(0x5) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \\\n+\t\t\t\t\tTX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG\n+\t/* When key=1, This is the VLAN tag TPID select value. */\n+\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK\tUINT32_C(0xff80000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT\t19\n+\t/*\n+\t * This field identifies the type of edit to be performed on the packet.\n+\t * This value must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_CFA_META_KEY_MASK\t\tUINT32_C(0xf0000000)\n+\t#define TX_BD_LONG_CFA_META_KEY_SFT\t\t28\n+\t\t/* No editing */\n+\t#define TX_BD_LONG_CFA_META_KEY_NONE\t\t(UINT32_C(0x0) << 28)\n+\t\t/*\n+\t\t * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]\n+\t\t * - PRI/DE value. - meta[11:0] - VID value.\n+\t\t */\n+\t#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG\t(UINT32_C(0x1) << 28)\n+\t#define TX_BD_LONG_CFA_META_KEY_LAST\tTX_BD_LONG_CFA_META_KEY_VLAN_TAG\n+\tuint32_t cfa_meta;\n+} __attribute__((packed));\n+\n+/* Completion Ring Structures */\n+/* Note: This structure is used by the HWRM to communicate HWRM Error. */\n+/* Base Completion Record (16 bytes) */\n+struct cmpl_base {\n+\t/* unused is 10 b */\n+\t/*\n+\t * This field indicates the exact type of the completion. By convention,\n+\t * the LSB identifies the length of the record in 16B units. Even values\n+\t * indicate 16B records. Odd values indicate 32B records.\n+\t */\n+\t#define CMPL_BASE_TYPE_MASK\t\t\tUINT32_C(0x3f)\n+\t#define CMPL_BASE_TYPE_SFT\t\t\t0\n+\t\t/* TX L2 completion: Completion of TX packet. Length = 16B */\n+\t#define CMPL_BASE_TYPE_TX_L2\t\t\t(UINT32_C(0x0) << 0)\n+\t\t/*\n+\t\t * RX L2 completion: Completion of and L2 RX packet.\n+\t\t * Length = 32B\n+\t\t*/\n+\t#define CMPL_BASE_TYPE_RX_L2\t\t\t(UINT32_C(0x11) << 0)\n+\t\t/*\n+\t\t * RX Aggregation Buffer completion : Completion of an L2\n+\t\t * aggregation buffer in support of TPA, HDS, or Jumbo packet\n+\t\t * completion. Length = 16B\n+\t\t */\n+\t#define CMPL_BASE_TYPE_RX_AGG\t\t\t(UINT32_C(0x12) << 0)\n+\t\t/*\n+\t\t * RX L2 TPA Start Completion: Completion at the beginning of a\n+\t\t * TPA operation. Length = 32B\n+\t\t */\n+\t#define CMPL_BASE_TYPE_RX_TPA_START\t\t(UINT32_C(0x13) << 0)\n+\t\t/*\n+\t\t * RX L2 TPA End Completion: Completion at the end of a TPA\n+\t\t * operation. Length = 32B\n+\t\t */\n+\t#define CMPL_BASE_TYPE_RX_TPA_END\t\t(UINT32_C(0x15) << 0)\n+\t\t/*\n+\t\t * Statistics Ejection Completion: Completion of statistics data\n+\t\t * ejection buffer. Length = 16B\n+\t\t */\n+\t#define CMPL_BASE_TYPE_STAT_EJECT\t\t(UINT32_C(0x1a) << 0)\n+\t\t/* HWRM Command Completion: Completion of an HWRM command. */\n+\t#define CMPL_BASE_TYPE_HWRM_DONE\t\t(UINT32_C(0x20) << 0)\n+\t\t/* Forwarded HWRM Request */\n+\t#define CMPL_BASE_TYPE_HWRM_FWD_REQ\t\t(UINT32_C(0x22) << 0)\n+\t\t/* Forwarded HWRM Response */\n+\t#define CMPL_BASE_TYPE_HWRM_FWD_RESP\t\t(UINT32_C(0x24) << 0)\n+\t\t/* HWRM Asynchronous Event Information */\n+\t#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT\t\t(UINT32_C(0x2e) << 0)\n+\t\t/* CQ Notification */\n+\t#define CMPL_BASE_TYPE_CQ_NOTIFICATION\t\t(UINT32_C(0x30) << 0)\n+\t\t/* SRQ Threshold Event */\n+\t#define CMPL_BASE_TYPE_SRQ_EVENT\t\t(UINT32_C(0x32) << 0)\n+\t\t/* DBQ Threshold Event */\n+\t#define CMPL_BASE_TYPE_DBQ_EVENT\t\t(UINT32_C(0x34) << 0)\n+\t\t/* QP Async Notification */\n+\t#define CMPL_BASE_TYPE_QP_EVENT\t\t\t(UINT32_C(0x38) << 0)\n+\t\t/* Function Async Notification */\n+\t#define CMPL_BASE_TYPE_FUNC_EVENT\t\t(UINT32_C(0x3a) << 0)\n+\tuint16_t type;\n+\n+\tuint16_t info1;\n+\tuint32_t info2;\n+\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue. The even passes will write 1.\n+\t * The odd passes will write 0.\n+\t */\n+\t#define CMPL_BASE_V\t\t\t\tUINT32_C(0x1)\n+\t/* info3 is 31 b */\n+\t#define CMPL_BASE_INFO3_MASK\t\t\tUINT32_C(0xfffffffe)\n+\t#define CMPL_BASE_INFO3_SFT\t\t\t1\n+\tuint32_t info3_v;\n+\n+\tuint32_t info4;\n+} __attribute__((packed));\n+\n+/* TX Completion Record (16 bytes) */\n+struct tx_cmpl {\n+\t/*\n+\t * This field indicates the exact type of the completion. By convention,\n+\t * the LSB identifies the length of the record in 16B units. Even values\n+\t * indicate 16B records. Odd values indicate 32B records.\n+\t */\n+\t#define TX_CMPL_TYPE_MASK\t\t\tUINT32_C(0x3f)\n+\t#define TX_CMPL_TYPE_SFT\t\t\t0\n+\t\t/* TX L2 completion: Completion of TX packet. Length = 16B */\n+\t#define TX_CMPL_TYPE_TX_L2\t\t\t(UINT32_C(0x0) << 0)\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an error of some\n+\t * type. Type of error is indicated in error_flags.\n+\t */\n+\t#define TX_CMPL_FLAGS_ERROR\t\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet completed was\n+\t * transmitted using the push acceleration data provided by the driver.\n+\t * When this bit is '0', it indicates that the packet had not push\n+\t * acceleration data written or was executed as a normal packet even\n+\t * though push data was provided.\n+\t */\n+\t#define TX_CMPL_FLAGS_PUSH\t\t\tUINT32_C(0x80)\n+\t#define TX_CMPL_FLAGS_MASK\t\t\tUINT32_C(0xffc0)\n+\t#define TX_CMPL_FLAGS_SFT\t\t\t6\n+\tuint16_t flags_type;\n+\n+\tuint16_t unused_0;\n+\n+\t/*\n+\t * This is a copy of the opaque field from the first TX BD of this\n+\t * transmitted packet.\n+\t */\n+\tuint32_t opaque;\n+\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue. The even passes will write 1.\n+\t * The odd passes will write 0.\n+\t */\n+\t#define TX_CMPL_V\t\t\t\tUINT32_C(0x1)\n+\t/*\n+\t * This error indicates that there was some sort of problem with the BDs\n+\t * for the packet.\n+\t */\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK\tUINT32_C(0xe)\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_SFT\t\t1\n+\t\t/* No error */\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR\t(UINT32_C(0x0) << 1)\n+\t\t/* Bad Format: BDs were not formatted correctly. */\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT\t(UINT32_C(0x2) << 1)\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\t\t\t\tTX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT\n+\t/*\n+\t * When this bit is '1', it indicates that the length of the packet was\n+\t * zero. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was longer than\n+\t * the programmed limit in TDI. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', it indicates that one or more of the BDs\n+\t * associated with this packet generated a PCI error. This probably\n+\t * means the address was not valid.\n+\t */\n+\t#define TX_CMPL_ERRORS_DMA_ERROR\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was longer than\n+\t * indicated by the hint. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_ERRORS_HINT_TOO_SHORT\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was dropped due to\n+\t * Poison TLP error on one or more of the TLPs in the PXP completion.\n+\t */\n+\t#define TX_CMPL_ERRORS_POISON_TLP_ERROR\t\tUINT32_C(0x100)\n+\t#define TX_CMPL_ERRORS_MASK\t\t\tUINT32_C(0xfffe)\n+\t#define TX_CMPL_ERRORS_SFT\t\t\t1\n+\tuint16_t errors_v;\n+\n+\tuint16_t unused_1;\n+\tuint32_t unused_2;\n+} __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;\n+\n /* HWRM Forwarded Request (16 bytes) */\n struct hwrm_fwd_req_cmpl {\n \t/* Length of forwarded request in bytes. */\n", "prefixes": [ "dpdk-dev", "v4", "13/39" ] }