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GET /api/patches/132140/?format=api
{ "id": 132140, "url": "http://patches.dpdk.org/api/patches/132140/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230928130913.2583907-2-shunh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230928130913.2583907-2-shunh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230928130913.2583907-2-shunh@nvidia.com", "date": "2023-09-28T13:09:11", "name": "[v1,1/3] net/mlx5/hws: add creation of packet reformat DevX obj", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3b9445700de3c767e5f8001b41b2e125382b434e", "submitter": { "id": 2212, "url": "http://patches.dpdk.org/api/people/2212/?format=api", "name": "Shun Hao", "email": "shunh@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230928130913.2583907-2-shunh@nvidia.com/mbox/", "series": [ { "id": 29682, "url": "http://patches.dpdk.org/api/series/29682/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29682", "date": "2023-09-28T13:09:10", "name": "Add HWS mirroring support", "version": 1, "mbox": "http://patches.dpdk.org/series/29682/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132140/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/132140/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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<hamdani@nvidia.com>,\n Alex Vesker <valex@nvidia.com>", "Subject": "[PATCH v1 1/3] net/mlx5/hws: add creation of packet reformat DevX obj", "Date": "Thu, 28 Sep 2023 16:09:11 +0300", "Message-ID": "<20230928130913.2583907-2-shunh@nvidia.com>", "X-Mailer": "git-send-email 2.20.0", "In-Reply-To": "<20230928130913.2583907-1-shunh@nvidia.com>", "References": "<20230928130913.2583907-1-shunh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail202.nvidia.com (10.129.68.7)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MN1PEPF0000ECD8:EE_|SJ2PR12MB9006:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f1aa06ba-3316-400d-b124-08dbc02433cc", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n S2S2wgfBDx6z0VrALmNcCeq8p0lEWh5m+u/qlMUzhas3FDGxgGiK7OtFH4Qgfa/8ukF8DSBxSZv0PDhC2W3iBt9GUCxlpAbHCKEXSMKv321uJPqXfOfzkr8SvmmG60DPMYEKG+IYeZtBJVxMx5kCkxcuOSor95qFCG7ilauKPaOfjxZWjkodcAaXIamR4mHRAbCDsFIKW4K1joDDPDxNzZIXxiHu5d4tVjmDpbXFGz1M102mHRbkgM72OavdyJhlrIMBDmje2lfLARjRH6En726ZyWdbXk3U55dgGechAwcdbRGxhO8BBdN8nhfLzONHRn7qHmxUSPz6mhinr0u044qrsZcnY+OwMT3bhGJpLHFO3foSLvZ82tiJ1L099YQ3RcEcW5e9chkbCD5Q3EJdzHC0P84/2Uc6rtSI3ZKopr4uhzOJWiFsP4ShzkUayOJPww+9JuCEGkrJ2IFhUkgQRaYtSuGMB5ttsiDjVYnDZB02HLezd+gFxodM5g6RB0/APHR+JAui/wjEjTBvP5wSyMkfP0UnNvBJzm1Si+PTGGWkz3rye//JZ7mJAiVcbgloBWwysgulYqDim7uYHIiVZRu2ScoctQMHrZoaP7IKMxkJKrGK4yxDH60s7IZR4uLRMXTclrHD2vy7gNSykEvln55mpfjKORPxWZdEzCiTNrckVgtOq0+RFFJavleBXyD/s/4BC1xcangoMsFgJQ8qJL4kl42uq0sQj5tG+OszV5GPxIcS1sTH1zzhJgb8RyF7", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(39860400002)(376002)(136003)(346002)(230922051799003)(1800799009)(64100799003)(82310400011)(186009)(451199024)(36840700001)(40470700004)(46966006)(40460700003)(66899024)(5660300002)(83380400001)(40480700001)(55016003)(316002)(41300700001)(6666004)(36756003)(8676002)(70586007)(70206006)(36860700001)(478600001)(6636002)(54906003)(8936002)(7636003)(110136005)(86362001)(47076005)(7696005)(82740400003)(2906002)(4326008)(356005)(426003)(2616005)(107886003)(26005)(6286002)(1076003)(336012)(16526019);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Sep 2023 13:09:52.1434 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f1aa06ba-3316-400d-b124-08dbc02433cc", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MN1PEPF0000ECD8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB9006", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nAdd support for creation of packet reformat object,\nvia the ALLOC_PACKET_REFORMAT_CONTEXT command.\n\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\nAcked-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 39 +++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 60 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 11 +++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 5 +++\n drivers/net/mlx5/hws/mlx5dr_send.c | 5 ---\n 5 files changed, 115 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 51f426c614..6749f2c037 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1213,6 +1213,8 @@ enum {\n \tMLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,\n \tMLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,\n \tMLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,\n+\tMLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,\n+\tMLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n \tMLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,\n@@ -5180,6 +5182,43 @@ struct mlx5_ifc_modify_flow_table_out_bits {\n \tu8 reserved_at_40[0x60];\n };\n \n+struct mlx5_ifc_packet_reformat_context_in_bits {\n+\tu8 reformat_type[0x8];\n+\tu8 reserved_at_8[0x4];\n+\tu8 reformat_param_0[0x4];\n+\tu8 reserved_at_16[0x6];\n+\tu8 reformat_data_size[0xa];\n+\n+\tu8 reformat_param_1[0x8];\n+\tu8 reserved_at_40[0x8];\n+\tu8 reformat_data[6][0x8];\n+\n+\tu8 more_reformat_data[][0x8];\n+};\n+\n+struct mlx5_ifc_alloc_packet_reformat_context_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\n+\tu8 reserved_at_40[0xa0];\n+\n+\tu8 packet_reformat_context[];\n+};\n+\n+struct mlx5_ifc_alloc_packet_reformat_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\n+\tu8 syndrome[0x20];\n+\n+\tu8 packet_reformat_id[0x20];\n+\n+\tu8 reserved_at_60[0x20];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex 7771aeb8cf..d20ec7f0c4 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -779,6 +779,66 @@ mlx5dr_cmd_sq_create(struct ibv_context *ctx,\n \treturn devx_obj;\n }\n \n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_packet_reformat_create(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_packet_reformat_create_attr *attr)\n+{\n+\tuint32_t out[DEVX_ST_SZ_DW(alloc_packet_reformat_out)] = {0};\n+\tsize_t insz, cmd_data_sz, cmd_total_sz;\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *prctx;\n+\tvoid *pdata;\n+\tvoid *in;\n+\n+\tcmd_total_sz = DEVX_ST_SZ_BYTES(alloc_packet_reformat_context_in);\n+\tcmd_total_sz += DEVX_ST_SZ_BYTES(packet_reformat_context_in);\n+\tcmd_data_sz = DEVX_FLD_SZ_BYTES(packet_reformat_context_in, reformat_data);\n+\tinsz = align(cmd_total_sz + attr->data_sz - cmd_data_sz, DW_SIZE);\n+\tin = simple_calloc(1, insz);\n+\tif (!in) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(alloc_packet_reformat_context_in, in, opcode,\n+\t\t MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT);\n+\n+\tprctx = DEVX_ADDR_OF(alloc_packet_reformat_context_in, in,\n+\t\t\t packet_reformat_context);\n+\tpdata = DEVX_ADDR_OF(packet_reformat_context_in, prctx, reformat_data);\n+\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_type, attr->type);\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_param_0, attr->reformat_param_0);\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_data_size, attr->data_sz);\n+\tmemcpy(pdata, attr->data, attr->data_sz);\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for packet reformat object\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto out_free_in;\n+\t}\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, insz, out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create packet reformat\");\n+\t\trte_errno = errno;\n+\t\tgoto out_free_devx;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(alloc_packet_reformat_out, out, packet_reformat_id);\n+\n+\tsimple_free(in);\n+\n+\treturn devx_obj;\n+\n+out_free_devx:\n+\tsimple_free(devx_obj);\n+out_free_in:\n+\tsimple_free(in);\n+\treturn NULL;\n+}\n+\n int mlx5dr_cmd_sq_modify_rdy(struct mlx5dr_devx_obj *devx_obj)\n {\n \tuint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex e57013c309..ee427c1829 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -155,6 +155,13 @@ struct mlx5dr_cmd_allow_other_vhca_access_attr {\n \tuint8_t access_key[ACCESS_KEY_LEN];\n };\n \n+struct mlx5dr_cmd_packet_reformat_create_attr {\n+\tuint8_t type;\n+\tsize_t data_sz;\n+\tvoid *data;\n+\tuint8_t reformat_param_0;\n+};\n+\n struct mlx5dr_cmd_query_ft_caps {\n \tuint8_t max_level;\n \tuint8_t reparse;\n@@ -270,6 +277,10 @@ mlx5dr_cmd_header_modify_pattern_create(struct ibv_context *ctx,\n \t\t\t\t\tuint32_t pattern_length,\n \t\t\t\t\tuint8_t *actions);\n \n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_packet_reformat_create(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_packet_reformat_create_attr *attr);\n+\n struct mlx5dr_devx_obj *\n mlx5dr_cmd_set_fte(struct ibv_context *ctx,\n \t\t uint32_t table_type,\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h\nindex c3c077667d..3770d28e62 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_internal.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_internal.h\n@@ -91,4 +91,9 @@ static inline uint64_t roundup_pow_of_two(uint64_t n)\n \treturn n == 1 ? 1 : 1ULL << log2above(n);\n }\n \n+static inline unsigned long align(unsigned long val, unsigned long align)\n+{\n+\treturn (val + align - 1) & ~(align - 1);\n+}\n+\n #endif /* MLX5DR_INTERNAL_H_ */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex e58fdeb117..622d574bfa 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -668,11 +668,6 @@ static int mlx5dr_send_ring_create_sq_obj(struct mlx5dr_context *ctx,\n \treturn err;\n }\n \n-static inline unsigned long align(unsigned long val, unsigned long align)\n-{\n-\treturn (val + align - 1) & ~(align - 1);\n-}\n-\n static int mlx5dr_send_ring_open_sq(struct mlx5dr_context *ctx,\n \t\t\t\t struct mlx5dr_send_engine *queue,\n \t\t\t\t struct mlx5dr_send_ring_sq *sq,\n", "prefixes": [ "v1", "1/3" ] }