Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 132091,
    "url": "http://patches.dpdk.org/api/patches/132091/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230928084458.2333663-6-yuying.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230928084458.2333663-6-yuying.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230928084458.2333663-6-yuying.zhang@intel.com",
    "date": "2023-09-28T08:44:54",
    "name": "[v9,5/9] net/cpfl: add FXP low level implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c6a7d94c16274becab6a7304c1fbb03c3ae2a6f3",
    "submitter": {
        "id": 1844,
        "url": "http://patches.dpdk.org/api/people/1844/?format=api",
        "name": "Zhang, Yuying",
        "email": "yuying.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230928084458.2333663-6-yuying.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 29669,
            "url": "http://patches.dpdk.org/api/series/29669/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29669",
            "date": "2023-09-28T08:44:49",
            "name": "add rte flow support for cpfl",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/29669/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/132091/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/132091/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 513964265E;\n\tThu, 28 Sep 2023 10:45:51 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 47D3E40DF6;\n\tThu, 28 Sep 2023 10:45:31 +0200 (CEST)",
            "from mgamail.intel.com (mgamail.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id B3F6840A6F\n for <dev@dpdk.org>; Thu, 28 Sep 2023 10:45:22 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Sep 2023 01:45:21 -0700",
            "from dpdk-wenjing-02.sh.intel.com ([10.67.119.3])\n by orsmga001.jf.intel.com with ESMTP; 28 Sep 2023 01:45:18 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695890722; x=1727426722;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=j2LUPx+MDnfN99SB7FvVkH4eU+R81KzsbkcomVRUAww=;\n b=fcqz+0KdVyS439fIx8aC6uttO4PG4zu0PpK2RQqT/ap8SAhS+OOqVJ1A\n P5mocUyfSXhv+MIxCwEU5y/x9dygIlFh5Q3gpTZSEwM/DD7Y9nZHQvWkq\n vO6s3+qJgE4DMC+jkp54oLgED0qhUWDp76zhabE2fyLWKaa3zhBR3iKd6\n wTlExeqyIEjG9yFo93Tek7kNDzMcXEfnnz1gP8I4+Hrf5AIZw9vOqZ/pd\n A4ipADxV8KXdfHPZ8g5hqJfmriSYj+wOImOaHV806oVm0GHQ7HoOq0Soi\n A7xRj7WMvZSh3EkBaYlE1tMBZu4sCPtN3iPSoCy2GH/6zi1KgGRLSCyPW w==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10846\"; a=\"468299505\"",
            "E=Sophos;i=\"6.03,183,1694761200\"; d=\"scan'208\";a=\"468299505\"",
            "E=McAfee;i=\"6600,9927,10846\"; a=\"784622209\"",
            "E=Sophos;i=\"6.03,183,1694761200\"; d=\"scan'208\";a=\"784622209\""
        ],
        "X-ExtLoop1": "1",
        "From": "yuying.zhang@intel.com",
        "To": "yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com,\n jingjing.wu@intel.com, beilei.xing@intel.com",
        "Subject": "[PATCH v9 5/9] net/cpfl: add FXP low level implementation",
        "Date": "Thu, 28 Sep 2023 08:44:54 +0000",
        "Message-Id": "<20230928084458.2333663-6-yuying.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20230928084458.2333663-1-yuying.zhang@intel.com>",
        "References": "<20230927125416.2308974-1-yuying.zhang@intel.com>\n <20230928084458.2333663-1-yuying.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Yuying Zhang <yuying.zhang@intel.com>\n\nAdd low level implementation for CPFL PMD to create / delete\nrules on IPU's Flexible Packet Processor(FXP).\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n drivers/net/cpfl/cpfl_actions.h | 858 ++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rules.c   | 127 +++++\n drivers/net/cpfl/cpfl_rules.h   | 306 ++++++++++++\n drivers/net/cpfl/meson.build    |   1 +\n 4 files changed, 1292 insertions(+)\n create mode 100644 drivers/net/cpfl/cpfl_actions.h\n create mode 100644 drivers/net/cpfl/cpfl_rules.c\n create mode 100644 drivers/net/cpfl/cpfl_rules.h",
    "diff": "diff --git a/drivers/net/cpfl/cpfl_actions.h b/drivers/net/cpfl/cpfl_actions.h\nnew file mode 100644\nindex 0000000000..7b82119e39\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_actions.h\n@@ -0,0 +1,858 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_ACTIONS_H_\n+#define _CPFL_ACTIONS_H_\n+\n+#include \"base/idpf_osdep.h\"\n+\n+#pragma pack(1)\n+\n+union cpfl_action_set {\n+\tuint32_t data;\n+\n+\tstruct {\n+\t\tuint32_t val : 24;\n+\t\tuint32_t idx : 4;\n+\t\tuint32_t tag : 1;\n+\t\tuint32_t prec : 3;\n+\t} set_24b_a;\n+\n+\tstruct {\n+\t\tuint32_t val : 24;\n+\t\tuint32_t idx : 3;\n+\t\tuint32_t tag : 2;\n+\t\tuint32_t prec : 3;\n+\t} set_24b_b;\n+\n+\tstruct {\n+\t\tuint32_t val : 16;\n+\t\tuint32_t idx : 4;\n+\t\tuint32_t unused : 6;\n+\t\tuint32_t tag : 3;\n+\t\tuint32_t prec : 3;\n+\t} set_16b;\n+\n+\tstruct {\n+\t\tuint32_t val_a : 8;\n+\t\tuint32_t val_b : 8;\n+\t\tuint32_t idx_a : 4;\n+\t\tuint32_t idx_b : 4;\n+\t\tuint32_t tag : 5;\n+\t\tuint32_t prec : 3;\n+\t} set_8b;\n+\n+\tstruct {\n+\t\tuint32_t val : 10;\n+\t\tuint32_t ena : 10;\n+\t\tuint32_t idx : 4;\n+\t\tuint32_t tag : 5;\n+\t\tuint32_t prec : 3;\n+\t} set_1b;\n+\n+\tstruct {\n+\t\tuint32_t val : 24;\n+\t\tuint32_t tag : 5;\n+\t\tuint32_t prec : 3;\n+\t} nop;\n+\n+\tstruct {\n+\t\tuint32_t val : 24;\n+\t\tuint32_t tag : 5;\n+\t\tuint32_t prec : 3;\n+\t} chained_24b;\n+\n+\tstruct {\n+\t\tuint32_t val : 24;\n+\t\tuint32_t tag : 5;\n+\t\tuint32_t prec : 3;\n+\t} aux_flags;\n+};\n+\n+struct cpfl_action_set_ext {\n+#define CPFL_ACTION_SET_EXT_CNT 2\n+\tunion cpfl_action_set acts[CPFL_ACTION_SET_EXT_CNT];\n+};\n+\n+#pragma pack()\n+\n+/**\n+ * cpfl_act_nop - Encode a NOP action\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_nop(void)\n+{\n+\tunion cpfl_action_set act;\n+\n+\tact.data = 0;\n+\treturn act;\n+}\n+\n+/**\n+ * cpfl_is_nop_action - Indicate if an action set is a NOP\n+ */\n+static inline bool\n+cpfl_is_nop_action(union cpfl_action_set *act)\n+{\n+\treturn act->data == cpfl_act_nop().data;\n+}\n+\n+#define CPFL_MAKE_MASK32(b, s)\t((((uint32_t)1 << (b)) - 1) << (s))\n+\n+#define CPFL_ACT_PREC_MAX\t7\n+#define CPFL_ACT_PREC_S\t\t29\n+#define CPFL_ACT_PREC_M\t\tCPFL_MAKE_MASK32(3, CPFL_ACT_PREC_S)\n+#define CPFL_ACT_PREC_SET(p)\t\\\n+\t(((uint32_t)(p) << CPFL_ACT_PREC_S) & CPFL_ACT_PREC_M)\n+#define CPFL_ACT_PREC_CHECK(p)\t((p) > 0 && (p) <= CPFL_ACT_PREC_MAX)\n+\n+#define CPFL_METADATA_ID_CNT\t\t32\t/* Max number of metadata IDs */\n+#define CPFL_METADATA_STRUCT_MAX_SZ\t128\t/* Max metadata size per ID */\n+\n+/*******************************************************************************\n+ * 1-Bit Actions\n+ ******************************************************************************/\n+#define CPFL_ACT_1B_OP_S\t24\n+#define CPFL_ACT_1B_OP_M\tCPFL_MAKE_MASK32(5, CPFL_ACT_1B_OP_S)\n+#define CPFL_ACT_1B_OP\t\t((uint32_t)(0x01) << CPFL_ACT_1B_OP_S)\n+\n+#define CPFL_ACT_1B_VAL_S\t0\n+#define CPFL_ACT_1B_VAL_M\tCPFL_MAKE_MASK32(10, CPFL_ACT_1B_VAL_S)\n+#define CPFL_ACT_1B_EN_S\t10\n+#define CPFL_ACT_1B_EN_M\tCPFL_MAKE_MASK32(10, CPFL_ACT_1B_EN_S)\n+#define CPFL_ACT_1B_INDEX_S\t20\n+#define CPFL_ACT_1B_INDEX_M\tCPFL_MAKE_MASK32(4, CPFL_ACT_1B_INDEX_S)\n+\n+/* 1-bit actions currently uses only INDEX of 0 */\n+#define CPFL_ACT_MAKE_1B(prec, en, val) \\\n+\t((CPFL_ACT_PREC_SET(prec)) | CPFL_ACT_1B_OP | \\\n+\t ((((uint32_t)0) << CPFL_ACT_1B_INDEX_S) & CPFL_ACT_1B_INDEX_M) | \\\n+\t (((uint32_t)(en) << CPFL_ACT_1B_EN_S) & CPFL_ACT_1B_EN_M) | \\\n+\t (((uint32_t)(val) << CPFL_ACT_1B_VAL_S) & CPFL_ACT_1B_VAL_M))\n+\n+enum cpfl_act_1b_op {\n+\tCPFL_ACT_1B_OP_DROP\t\t= 0x01,\n+\tCPFL_ACT_1B_OP_HDR_SPLIT\t= 0x02,\n+\tCPFL_ACT_1B_OP_DIR_CHANGE\t= 0x04,\n+\tCPFL_ACT_1B_OP_DEFER_DROP\t= 0x08,\n+\tCPFL_ACT_1B_OP_ORIG_MIR_MD\t= 0x80\n+};\n+\n+#define CPFL_ACT_1B_COMMIT_MODE_S\t4\n+#define CPFL_ACT_1B_COMMIT_MODE_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_1B_COMMIT_MODE_S)\n+\n+/**\n+ * cpfl_act_commit_mode - action commit mode for certain action classes\n+ */\n+enum cpfl_act_commit_mode {\n+\t/* Action processing for the initial classification pass */\n+\tCPFL_ACT_COMMIT_ALL\t\t= 0, /* Commit all actions */\n+\tCPFL_ACT_COMMIT_PRE_MOD\t\t= 1, /* Commit only pre-modify actions*/\n+\tCPFL_ACT_COMMIT_NONE\t\t= 2, /* Commit no action */\n+\t/* Action processing for deferred actions in a recirculation pass */\n+\tCPFL_ACT_COMMIT_RECIR_ALL\t= 4, /* Commit all actions */\n+\tCPFL_ACT_COMMIT_RECIR_PRE_MOD\t= 5, /* Commit only pre-modify actions*/\n+\tCPFL_ACT_COMMIT_RECIR_NONE\t= 6  /* Commit no action */\n+};\n+\n+/*******************************************************************************\n+ * 8-Bit Actions\n+ ******************************************************************************/\n+#define CPFL_ACT_OP_8B_S\t24\n+#define CPFL_ACT_OP_8B_M\tCPFL_MAKE_MASK32(5, CPFL_ACT_OP_8B_S)\n+#define CPFL_ACT_OP_8B\t\t((uint32_t)(0x02) << CPFL_ACT_OP_8B_S)\n+\n+#define CPFL_ACT_8B_A_VAL_S\t0\n+#define CPFL_ACT_8B_A_VAL_M\tCPFL_MAKE_MASK32(8, CPFL_ACT_8B_A_VAL_S)\n+#define CPFL_ACT_8B_A_INDEX_S\t16\n+#define CPFL_ACT_8B_A_INDEX_M\tCPFL_MAKE_MASK32(4, CPFL_ACT_8B_A_INDEX_S)\n+\n+#define CPFL_ACT_8B_B_VAL_S\t8\n+#define CPFL_ACT_8B_B_VAL_M\tCPFL_MAKE_MASK32(8, CPFL_ACT_8B_B_VAL_S)\n+#define CPFL_ACT_8B_B_INDEX_S\t20\n+#define CPFL_ACT_8B_B_INDEX_M\tCPFL_MAKE_MASK32(4, CPFL_ACT_8B_B_INDEX_S)\n+\n+/* Unless combining two 8-bit actions into an action set, both A and B fields\n+ * must be the same,\n+ */\n+#define CPFL_ACT_MAKE_8B(prec, idx, val) \\\n+\t((CPFL_ACT_PREC_SET(prec)) | CPFL_ACT_OP_8B | \\\n+\t (((idx) << CPFL_ACT_8B_A_INDEX_S) & CPFL_ACT_8B_A_INDEX_M) | \\\n+\t (((idx) << CPFL_ACT_8B_B_INDEX_S) & CPFL_ACT_8B_B_INDEX_M) | \\\n+\t (((val) << CPFL_ACT_8B_A_VAL_S) & CPFL_ACT_8B_A_VAL_M) | \\\n+\t (((val) << CPFL_ACT_8B_B_VAL_S) & CPFL_ACT_8B_B_VAL_M))\n+\n+/* 8-Bit Action Indices */\n+#define CPFL_ACT_8B_INDEX_MOD_META\t\t9\n+\n+/* 8-Bit Action Miscellaneous */\n+#define CPFL_ACT_8B_MOD_META_PROF_CNT\t\t16\n+#define CPFL_ACT_8B_MOD_META_VALID\t\t0x80\n+\n+/*******************************************************************************\n+ * 16-Bit Actions\n+ ******************************************************************************/\n+#define CPFL_ACT_OP_16B_S\t26\n+#define CPFL_ACT_OP_16B_M\tCPFL_MAKE_MASK32(3, CPFL_ACT_OP_16B_S)\n+#define CPFL_ACT_OP_16B\t\t((uint32_t)0x1 << CPFL_ACT_OP_16B_S)\n+\n+#define CPFL_ACT_16B_INDEX_S\t16\n+#define CPFL_ACT_16B_INDEX_M\tCPFL_MAKE_MASK32(4, CPFL_ACT_16B_INDEX_S)\n+#define CPFL_ACT_16B_VAL_S\t0\n+#define CPFL_ACT_16B_VAL_M\tCPFL_MAKE_MASK32(16, CPFL_ACT_16B_VAL_S)\n+\n+#define CPFL_ACT_MAKE_16B(prec, idx, val) \\\n+\t((CPFL_ACT_PREC_SET(prec)) | CPFL_ACT_OP_16B | \\\n+\t (((uint32_t)(idx) << CPFL_ACT_16B_INDEX_S) & CPFL_ACT_16B_INDEX_M) | \\\n+\t (((uint32_t)(val) << CPFL_ACT_16B_VAL_S) & CPFL_ACT_16B_VAL_M))\n+\n+/* 16-Bit Action Indices */\n+#define CPFL_ACT_16B_INDEX_COUNT_SET\t\t0\n+#define CPFL_ACT_16B_INDEX_SET_MCAST_IDX\t1\n+#define CPFL_ACT_16B_INDEX_SET_VSI\t\t2\n+#define CPFL_ACT_16B_INDEX_DEL_MD\t\t4\n+#define CPFL_ACT_16B_INDEX_MOD_VSI_LIST\t\t5\n+\n+/* 16-Bit Action Miscellaneous */\n+#define CPFL_ACT_16B_COUNT_SET_CNT\t\t2048 /* TODO: Value from NSL */\n+#define CPFL_ACT_16B_SET_VSI_SLOTS\t\t2\n+#define CPFL_ACT_16B_FWD_VSI_CNT\t\t1032 /* TODO: Value from NSL */\n+#define CPFL_ACT_16B_FWD_VSI_LIST_CNT\t\t256\n+#define CPFL_ACT_16B_MOD_VSI_LIST_CNT\t\t1024\n+#define CPFL_ACT_16B_FWD_PORT_CNT\t\t4\n+#define CPFL_ACT_16B_DEL_MD_MID_CNT\t\t32\n+#define CPFL_ACT_16B_MOD_VSI_LIST_SLOTS\t\t4\n+\n+/* 16-Bit SET_MCAST_IDX Action */\n+#define CPFL_ACT_16B_SET_MCAST_VALID\t((uint32_t)1 << 15)\n+\n+/* 16-Bit SET_VSI Action Variants */\n+#define CPFL_ACT_16B_SET_VSI_VAL_S\t\t0\n+#define CPFL_ACT_16B_SET_VSI_VAL_M\t\t\\\n+\tCPFL_MAKE_MASK32(11, CPFL_ACT_16B_SET_VSI_VAL_S)\n+#define CPFL_ACT_16B_SET_VSI_PE_S\t\t11\n+#define CPFL_ACT_16B_SET_VSI_PE_M\t\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_16B_SET_VSI_PE_S)\n+#define CPFL_ACT_16B_SET_VSI_TYPE_S\t\t14\n+#define CPFL_ACT_16B_SET_VSI_TYPE_M\t\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_16B_SET_VSI_TYPE_S)\n+\n+/* 16-Bit DEL_MD Action */\n+#define CPFL_ACT_16B_DEL_MD_0_S\t\t0\n+#define CPFL_ACT_16B_DEL_MD_1_S\t\t5\n+\n+/* 16-Bit MOD_VSI_LIST Actions */\n+#define CPFL_ACT_16B_MOD_VSI_LIST_ID_S\t0\n+#define CPFL_ACT_16B_MOD_VSI_LIST_ID_M\t\\\n+\tCPFL_MAKE_MASK32(10, CPFL_ACT_16B_MOD_VSI_LIST_ID_S)\n+#define CPFL_ACT_16B_MOD_VSI_LIST_OP_S\t14\n+#define CPFL_ACT_16B_MOD_VSI_LIST_OP_M\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_16B_MOD_VSI_LIST_OP_S)\n+#define CPFL_MAKE_16B_MOD_VSI_LIST(op, id) \\\n+\t((((uint32_t)(op) << CPFL_ACT_16B_MOD_VSI_LIST_OP_S) & \\\n+\t\tCPFL_ACT_16B_MOD_VSI_LIST_OP_M) | \\\n+\t (((uint32_t)(id) << CPFL_ACT_16B_MOD_VSI_LIST_ID_S) & \\\n+\t\tCPFL_ACT_16B_MOD_VSI_LIST_ID_M))\n+\n+#define CPFL_ACT_16B_MAKE_SET_VSI(type, pe, val) \\\n+\t((((uint32_t)(type) << CPFL_ACT_16B_SET_VSI_TYPE_S) & \\\n+\t\tCPFL_ACT_16B_SET_VSI_TYPE_M) | \\\n+\t (((uint32_t)(pe) << CPFL_ACT_16B_SET_VSI_PE_S) & \\\n+\t\tCPFL_ACT_16B_SET_VSI_PE_M) | \\\n+\t (((uint32_t)(val) << CPFL_ACT_16B_SET_VSI_VAL_S) & \\\n+\t\tCPFL_ACT_16B_SET_VSI_VAL_M))\n+\n+enum cpfl_prot_eng {\n+\tCPFL_PE_LAN = 0,\n+\tCPFL_PE_RDMA,\n+\tCPFL_PE_CRT\n+};\n+\n+enum cpfl_act_fwd_type {\n+\tCPFL_ACT_FWD_VSI,\n+\tCPFL_ACT_FWD_VSI_LIST,\n+\tCPFL_ACT_FWD_PORT\n+};\n+\n+/*******************************************************************************\n+ * 24-Bit Actions\n+ ******************************************************************************/\n+/* Group A */\n+#define CPFL_ACT_OP_24B_A_S\t28\n+#define CPFL_ACT_OP_24B_A_M\tCPFL_MAKE_MASK32(1, CPFL_ACT_OP_24B_A_S)\n+#define CPFL_ACT_24B_A_INDEX_S\t24\n+#define CPFL_ACT_24B_A_INDEX_M\tCPFL_MAKE_MASK32(4, CPFL_ACT_24B_A_INDEX_S)\n+#define CPFL_ACT_24B_A_VAL_S\t0\n+#define CPFL_ACT_24B_A_VAL_M\tCPFL_MAKE_MASK32(24, CPFL_ACT_24B_A_VAL_S)\n+\n+#define CPFL_ACT_OP_24B_A\t((uint32_t)1 << CPFL_ACT_OP_24B_A_S)\n+\n+#define CPFL_ACT_MAKE_24B_A(prec, idx, val) \\\n+\t((CPFL_ACT_PREC_SET(prec)) | CPFL_ACT_OP_24B_A | \\\n+\t (((uint32_t)(idx) << CPFL_ACT_24B_A_INDEX_S) & CPFL_ACT_24B_A_INDEX_M) | \\\n+\t (((uint32_t)(val) << CPFL_ACT_24B_A_VAL_S) & CPFL_ACT_24B_A_VAL_M))\n+\n+#define CPFL_ACT_24B_INDEX_MOD_ADDR\t0\n+#define CPFL_ACT_24B_INDEX_MIRROR_FIRST\t1\n+#define CPFL_ACT_24B_INDEX_COUNT\t2\n+#define CPFL_ACT_24B_INDEX_SET_Q\t8\n+#define CPFL_ACT_24B_INDEX_MOD_PROFILE\t9\n+#define CPFL_ACT_24B_INDEX_METER\t10\n+\n+#define CPFL_ACT_24B_COUNT_SLOTS\t6\n+#define CPFL_ACT_24B_METER_SLOTS\t6\n+\n+#define CPFL_ACT_24B_MOD_ADDR_CNT\t(16 * 1024 * 1024)\n+#define CPFL_ACT_24B_COUNT_ID_CNT\t((uint32_t)1 << 24)\n+#define CPFL_ACT_24B_SET_Q_CNT\t\t(12 * 1024)\n+#define CPFL_ACT_24B_SET_Q_Q_RGN_BITS\t3\n+\n+/* 24-Bit SET_Q Action */\n+#define CPFL_ACT_24B_SET_Q_Q_S\t\t0\n+#define CPFL_ACT_24B_SET_Q_Q_M\t\t\\\n+\tCPFL_MAKE_MASK32(14, CPFL_ACT_24B_SET_Q_Q_S)\n+#define CPFL_ACT_24B_SET_Q_Q_RGN_S\t14\n+#define CPFL_ACT_24B_SET_Q_Q_RGN_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_SET_Q_Q_RGN_S)\n+#define CPFL_ACT_24B_SET_Q_IMPLICIT_VSI_DIS\tCPFL_MAKE_MASK32(1, 17)\n+#define CPFL_ACT_24B_SET_Q_DST_PE_S\t21\n+#define CPFL_ACT_24B_SET_Q_DST_PE_M\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_24B_SET_Q_DST_PE_S)\n+#define CPFL_ACT_24B_SET_Q_VALID\tCPFL_MAKE_MASK32(1, 23)\n+\n+/* 24-Bit MOD_PROFILE Action */\n+enum cpfl_act_mod_profile_hint {\n+\tCPFL_ACT_MOD_PROFILE_NO_ADDR = 0, /* No associated MOD_ADDR action */\n+\tCPFL_ACT_MOD_PROFILE_PREFETCH_128B, /* Prefetch 128B using MOD_ADDR */\n+\tCPFL_ACT_MOD_PROFILE_PREFETCH_256B, /* Prefetch 256B using MOD_ADDR */\n+};\n+\n+#define CPFL_ACT_24B_MOD_PROFILE_PROF_S\t\t0\n+#define CPFL_ACT_24B_MOD_PROFILE_PROF_M\t\t\\\n+\tCPFL_MAKE_MASK32(11, CPFL_ACT_24B_MOD_PROFILE_PROF_S)\n+#define CPFL_ACT_24B_MOD_PROFILE_XTLN_IDX_S\t12\n+#define CPFL_ACT_24B_MOD_PROFILE_XTLN_IDX_M\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_24B_MOD_PROFILE_XTLN_IDX_S)\n+#define CPFL_ACT_24B_MOD_PROFILE_HINT_S\t\t14\n+#define CPFL_ACT_24B_MOD_PROFILE_HINT_M\t\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_24B_MOD_PROFILE_HINT_S)\n+#define CPFL_ACT_24B_MOD_PROFILE_APPEND_ACT_BUS\t\t((uint32_t)1 << 16)\n+#define CPFL_ACT_24B_MOD_PROFILE_SET_MISS_PREPEND\t((uint32_t)1 << 17)\n+#define CPFL_ACT_24B_MOD_PROFILE_VALID\t\t\t((uint32_t)1 << 23)\n+\n+#define CPFL_ACT_24B_MOD_PROFILE_PTYPE_XLTN_INDEXES\t4\n+#define CPFL_ACT_24B_MOD_PROFILE_PROF_CNT\t\t2048\n+\n+/* 24-Bit METER Actions */\n+#define CPFL_ACT_24B_METER_INDEX_S\t0\n+#define CPFL_ACT_24B_METER_INDEX_M\t\\\n+\tCPFL_MAKE_MASK32(20, CPFL_ACT_24B_METER_INDEX_S)\n+#define CPFL_ACT_24B_METER_BANK_S\t20\n+#define CPFL_ACT_24B_METER_BANK_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_METER_BANK_S)\n+#define CPFL_ACT_24B_METER_VALID\t((uint32_t)1 << 23)\n+\n+#define CPFL_ACT_24B_METER_BANK_CNT\t6\n+#define CPFL_ACT_24B_METER_INDEX_CNT\t((uint32_t)1 << 20)\n+\n+/* Group B */\n+#define CPFL_ACT_OP_24B_B_S\t27\n+#define CPFL_ACT_OP_24B_B_M\tCPFL_MAKE_MASK32(2, CPFL_ACT_OP_24B_B_S)\n+#define CPFL_ACT_24B_B_INDEX_S\t24\n+#define CPFL_ACT_24B_B_INDEX_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_B_INDEX_S)\n+#define CPFL_ACT_24B_B_VAL_S\t0\n+#define CPFL_ACT_24B_B_VAL_M\tCPFL_MAKE_MASK32(24, CPFL_ACT_24B_B_VAL_S)\n+\n+#define CPFL_ACT_OP_24B_B\t((uint32_t)1 << CPFL_ACT_OP_24B_B_S)\n+\n+#define CPFL_ACT_MAKE_24B_B(prec, idx, val) \\\n+\t((CPFL_ACT_PREC_SET(prec)) | CPFL_ACT_OP_24B_B | \\\n+\t (((uint32_t)(idx) << CPFL_ACT_24B_B_INDEX_S) & CPFL_ACT_24B_B_INDEX_M) | \\\n+\t (((uint32_t)(val) << CPFL_ACT_24B_B_VAL_S) & CPFL_ACT_24B_B_VAL_M))\n+\n+#define CPFL_ACT_24B_INDEX_SET_MD\t0\n+#define CPFL_ACT_24B_INDEX_RANGE_CHECK\t6\n+#define CPFL_ACT_24B_SET_MD_SLOTS\t6\n+\n+/* Set/Add/Delete Metadata Actions - SET_MD[0-5], DEL_MD */\n+/* 8-Bit SET_MD */\n+#define CPFL_ACT_24B_SET_MD8_VAL_S\t0\n+#define CPFL_ACT_24B_SET_MD8_VAL_M\t\\\n+\tCPFL_MAKE_MASK32(8, CPFL_ACT_24B_SET_MD8_VAL_S)\n+#define CPFL_ACT_24B_SET_MD8_MASK_S\t8\n+#define CPFL_ACT_24B_SET_MD8_MASK_M\t\\\n+\tCPFL_MAKE_MASK32(8, CPFL_ACT_24B_SET_MD8_MASK_S)\n+#define CPFL_ACT_24B_SET_MD8_OFFSET_S\t16\n+#define CPFL_ACT_24B_SET_MD8_OFFSET_M\t\\\n+\tCPFL_MAKE_MASK32(4, CPFL_ACT_24B_SET_MD8_OFFSET_S)\n+#define CPFL_ACT_24B_SET_MD8_TYPE_ID_S\t20\n+#define CPFL_ACT_24B_SET_MD8_TYPE_ID_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_SET_MD8_TYPE_ID_S)\n+/* 16-Bit SET_MD */\n+#define CPFL_ACT_24B_SET_MD16_VAL_S\t0\n+#define CPFL_ACT_24B_SET_MD16_VAL_M\t\\\n+\tCPFL_MAKE_MASK32(16, CPFL_ACT_24B_SET_MD16_VAL_S)\n+#define CPFL_ACT_24B_SET_MD16_MASK_L_S\t16 /* For chained action */\n+#define CPFL_ACT_24B_SET_MD16_MASK_L_M\t\\\n+\tCPFL_MAKE_MASK32(8, CPFL_ACT_24B_SET_MD16_MASK_L_S)\n+#define CPFL_ACT_24B_SET_MD16_MASK_H_SR\t8\n+#define CPFL_ACT_24B_SET_MD16_MASK_H_M\t0xff\n+#define CPFL_ACT_24B_SET_MD16_OFFSET_S\t16\n+#define CPFL_ACT_24B_SET_MD16_OFFSET_M\t\\\n+\tCPFL_MAKE_MASK32(4, CPFL_ACT_24B_SET_MD16_OFFSET_S)\n+#define CPFL_ACT_24B_SET_MD16_TYPE_ID_S\t20\n+#define CPFL_ACT_24B_SET_MD16_TYPE_ID_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_SET_MD16_TYPE_ID_S)\n+#define CPFL_ACT_24B_SET_MD16\t\t((uint32_t)1 << 23)\n+\n+#define CPFL_ACT_24B_SET_MD32_VAL_L_M\tCPFL_MAKE_MASK32(24, 0)\n+\n+#define CPFL_ACT_24B_SET_MD8_OFFSET_MAX\t\t15\n+#define CPFL_ACT_24B_SET_MD8_TYPE_ID_MAX\t7\n+#define CPFL_ACT_24B_SET_MD16_OFFSET_MAX\t15\n+#define CPFL_ACT_24B_SET_MD16_TYPE_ID_MAX\t7\n+\n+/* RANGE_CHECK Action */\n+enum cpfl_rule_act_rc_mode {\n+\tCPFL_RULE_ACT_RC_1_RANGE = 0,\n+\tCPFL_RULE_ACT_RC_2_RANGES = 1,\n+\tCPFL_RULE_ACT_RC_4_RANGES = 2,\n+\tCPFL_RULE_ACT_RC_8_RANGES = 3\n+};\n+\n+#define CPFL_ACT_24B_RC_TBL_IDX_S\t0\n+#define CPFL_ACT_24B_RC_TBL_IDX_M\t\\\n+\tCPFL_MAKE_MASK32(13, CPFL_ACT_24B_RC_TBL_IDX_S)\n+#define CPFL_ACT_24B_RC_START_BANK_S\t13\n+#define CPFL_ACT_24B_RC_START_BANK_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_24B_RC_START_BANK_S)\n+#define CPFL_ACT_24B_RC_MODE_S\t\t16\n+#define CPFL_ACT_24B_RC_MODE_M\t\t\\\n+\tCPFL_MAKE_MASK32(2, CPFL_ACT_24B_RC_MODE_S)\n+#define CPFL_ACT_24B_RC_XTRACT_PROF_S\t18\n+#define CPFL_ACT_24B_RC_XTRACT_PROF_M\t\\\n+\tCPFL_MAKE_MASK32(6, CPFL_ACT_24B_RC_XTRACT_PROF_S)\n+\n+#define CPFL_ACT_24B_RC_TBL_INDEX_CNT\t(8 * 1024)\n+#define CPFL_ACT_24B_RC_BANK_CNT\t8\n+#define CPFL_ACT_24B_RC_XTRACT_PROF_CNT\t64\n+\n+/*******************************************************************************\n+ * 24-Bit Chained Auxiliary Actions\n+ ******************************************************************************/\n+\n+/* TODO: HAS is being updated.  Revise the order of chained and base action\n+ * when the HAS has it finalized.\n+ */\n+/**\n+ * 24-Bit Chained SET_MD Actions\n+ *\n+ * Chained SET_MD actions consume two consecutive action sets.  The first one is\n+ * the chained AUX action set.  The second one is the base/parent action set.\n+ * Chained SET_MD actions can add and/or update metadata structure with IDs from\n+ * 0 to 31 while the non-chained SET_MD variants can only update existing meta-\n+ * data IDs below 16.\n+ */\n+\n+#define CPFL_ACT_24B_SET_MD_AUX_OFFSET_S\t8\n+#define CPFL_ACT_24B_SET_MD_AUX_OFFSET_M\t\\\n+\tCPFL_MAKE_MASK32(7, CPFL_ACT_24B_SET_MD_AUX_OFFSET_S)\n+#define CPFL_ACT_24B_SET_MD_AUX_ADD\t\t((uint32_t)1 << 15)\n+#define CPFL_ACT_24B_SET_MD_AUX_TYPE_ID_S\t16\n+#define CPFL_ACT_24B_SET_MD_AUX_TYPE_ID_M\t\\\n+\tCPFL_MAKE_MASK32(5, CPFL_ACT_24B_SET_MD_AUX_TYPE_ID_S)\n+#define CPFL_ACT_24B_SET_MD_AUX_DATA_S\t\t0\n+#define CPFL_ACT_24B_SET_MD_AUX_DATA_M\t\t\\\n+\tCPFL_MAKE_MASK32(8, CPFL_ACT_24B_SET_MD_AUX_DATA_S)\n+\n+#define CPFL_ACT_24B_SET_MD_AUX_16B_MASK_H_S\t0\n+#define CPFL_ACT_24B_SET_MD_AUX_16B_MASK_H_M\t\\\n+\tCPFL_MAKE_MASK32(8, CPFL_ACT_24B_SET_MD_AUX_16B_MASK_H_S)\n+#define CPFL_ACT_24B_SET_MD_AUX_32B_VAL_H_SR\t24 /* Upper 8 bits of MD32 */\n+#define CPFL_ACT_24B_SET_MD_AUX_32B_VAL_H_M\t0xff\n+\n+#define CPFL_ACT_TYPE_CHAIN_DATA_S\t29\n+#define CPFL_ACT_TYPE_CHAIN_DATA_M\t\\\n+\tCPFL_MAKE_MASK32(3, CPFL_ACT_TYPE_CHAIN_DATA_S)\n+#define CPFL_ACT_TYPE_CHAIN_DATA\t((uint32_t)1 << CPFL_ACT_TYPE_CHAIN_DATA_S)\n+\n+#define CPFL_ACT_24B_SET_MD_OP_S\t21\n+#define CPFL_ACT_24B_SET_MD_OP_8B\t((uint32_t)0 << CPFL_ACT_24B_SET_MD_OP_S)\n+#define CPFL_ACT_24B_SET_MD_OP_16B\t((uint32_t)1 << CPFL_ACT_24B_SET_MD_OP_S)\n+#define CPFL_ACT_24B_SET_MD_OP_32B\t((uint32_t)2 << CPFL_ACT_24B_SET_MD_OP_S)\n+\n+#define CPFL_ACT_24B_SET_MD_AUX_MAKE(op, mid, off, data) \\\n+\t(CPFL_ACT_TYPE_CHAIN_DATA | (op) | \\\n+\t (((uint32_t)(mid) << CPFL_ACT_24B_SET_MD_AUX_TYPE_ID_S) & \\\n+\t\tCPFL_ACT_24B_SET_MD_AUX_TYPE_ID_M) | \\\n+\t (((uint32_t)(off) << CPFL_ACT_24B_SET_MD_AUX_OFFSET_S) & \\\n+\t\tCPFL_ACT_24B_SET_MD_AUX_OFFSET_M) | \\\n+\t (((uint32_t)(data) << CPFL_ACT_24B_SET_MD_AUX_DATA_S) & \\\n+\t\tCPFL_ACT_24B_SET_MD_AUX_DATA_M))\n+\n+/*******************************************************************************\n+ * 1-Bit Action Factory\n+ ******************************************************************************/\n+\n+/**\n+ * cpfl_act_drop - Encode a 1-bit DROP action\n+ *\n+ * The DROP action has precedence over the DEFER_DOP action.\n+ * Affect of ACT_COMMIT action on the DROP action:\n+ *  - CPFL_ACT_COMMIT_ALL: Packet is dropped.\n+ *  - CPFL_ACT_COMMIT_PRE_MOD or CPFL_ACT_COMMIT_NONE: Packet is not dropped.\n+ *  - CPFL_ACT_COMMIT_RECIR_ALL: Packet is dropped.  Recirculation is canceled.\n+ *  - CPFL_ACT_COMMIT_RECIR_PRE_MOD or CPFL_ACT_COMMIT_RECIR_NONE: Packet is not\n+ *    dropped. Recirculation continues.\n+ *\n+ * Once a DROP action is set, it cannot be reverted during the classification\n+ * process of a network packet.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_drop(uint8_t prec)\n+{\n+\tunion cpfl_action_set a;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec))\n+\t\treturn cpfl_act_nop();\n+\ta.data = CPFL_ACT_MAKE_1B(prec, CPFL_ACT_1B_OP_DROP, 1);\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_commit_mode - Encode a 1-bit ACT_COMMIT action\n+ * An ACT_COMMIT action specifies if and when all actions are committed.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_set_commit_mode(uint8_t prec, enum cpfl_act_commit_mode mode)\n+{\n+\tunion cpfl_action_set a;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec))\n+\t\treturn cpfl_act_nop();\n+\ta.data = CPFL_ACT_MAKE_1B(prec, CPFL_ACT_1B_COMMIT_MODE_M,\n+\t\t\t\t  (uint32_t)mode << CPFL_ACT_1B_COMMIT_MODE_S);\n+\treturn a;\n+}\n+\n+/*******************************************************************************\n+ * 8-Bit Action Factory\n+ ******************************************************************************/\n+\n+/**\n+ * cpfl_act_mod_meta - Encode an 8-bit MOD_META action\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_mod_meta(uint8_t prec, uint8_t prof)\n+{\n+\tunion cpfl_action_set a;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || prof >= CPFL_ACT_8B_MOD_META_PROF_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\ta.data = CPFL_ACT_MAKE_8B(prec, CPFL_ACT_8B_INDEX_MOD_META,\n+\t\t\t\t  CPFL_ACT_8B_MOD_META_VALID | prof);\n+\n+\treturn a;\n+}\n+\n+/*******************************************************************************\n+ * 16-Bit Action Factory\n+ ******************************************************************************/\n+\n+/**\n+ * cpfl_act_fwd_vsi - Encode a 16-bit SET_VSI action (forward to a VSI)\n+ *\n+ * This encodes the \"Forward to Single VSI\" variant of SET_VSI action.\n+ * SEM can use both SET_VSI action slots.  The other classification blocks can\n+ * only use slot 0.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_fwd_vsi(uint8_t slot, uint8_t prec, enum cpfl_prot_eng pe, uint16_t vsi)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || slot >= CPFL_ACT_16B_SET_VSI_SLOTS ||\n+\t    vsi >= CPFL_ACT_16B_FWD_VSI_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_16B_MAKE_SET_VSI(CPFL_ACT_FWD_VSI, pe, vsi);\n+\ta.data = CPFL_ACT_MAKE_16B(prec, CPFL_ACT_16B_INDEX_SET_VSI + slot,\n+\t\t\t\t   val);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_fwd_port - Encode a 16-bit SET_VSI action (forward to a port)\n+ *\n+ * This encodes the \"Forward to a port\" variant of SET_VSI action.\n+ * SEM can use both SET_VSI action slots.  The other classification blocks can\n+ * only use slot 0.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_fwd_port(uint8_t slot, uint8_t prec, enum cpfl_prot_eng pe, uint8_t port)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || slot >= CPFL_ACT_16B_SET_VSI_SLOTS ||\n+\t    port >= CPFL_ACT_16B_FWD_PORT_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_16B_MAKE_SET_VSI(CPFL_ACT_FWD_PORT, pe, port);\n+\ta.data = CPFL_ACT_MAKE_16B(prec, CPFL_ACT_16B_INDEX_SET_VSI + slot,\n+\t\t\t\t   val);\n+\n+\treturn a;\n+}\n+\n+/*******************************************************************************\n+ * 24-Bit Action Factory\n+ ******************************************************************************/\n+\n+/**\n+ * cpfl_act_mod_addr - Encode a 24-bit MOD_ADDR action\n+ *\n+ * This MOD_ADDR specifies the index of the MOD content entry an accompanying\n+ * MOD_PROFILE action uses.  Some MOD_PROFILE actions may need to use extra\n+ * information from a Modify content entry, and requires an accompanying\n+ * MOD_ADDR action.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_mod_addr(uint8_t prec, uint32_t mod_addr)\n+{\n+\tunion cpfl_action_set a;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || mod_addr >= CPFL_ACT_24B_MOD_ADDR_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\ta.data = CPFL_ACT_MAKE_24B_A(prec, CPFL_ACT_24B_INDEX_MOD_ADDR,\n+\t\t\t\t     mod_addr);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_hash_queue - Encode a 24-bit SET_Q action (one queue variant)\n+ *\n+ * This action is a \"Forward to a single queue\" variant of the SET_Q action.\n+ *\n+ * SEM performs Implicit VSI for SET_Q action when \"no_impliciti_vsi\" is false.\n+ * WCM and LEM never perform Implicit VSI for SET_Q actions.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_set_hash_queue(uint8_t prec, enum cpfl_prot_eng pe, uint16_t q,\n+\t\t\tbool no_implicit_vsi)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || q >= CPFL_ACT_24B_SET_Q_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_24B_SET_Q_VALID | (uint32_t)q |\n+\t\t(((uint32_t)pe << CPFL_ACT_24B_SET_Q_DST_PE_S) &\n+\t\t\tCPFL_ACT_24B_SET_Q_DST_PE_M);\n+\tif (no_implicit_vsi)\n+\t\tval |= CPFL_ACT_24B_SET_Q_IMPLICIT_VSI_DIS;\n+\ta.data = CPFL_ACT_MAKE_24B_A(prec, CPFL_ACT_24B_INDEX_SET_Q, val);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_hash_queue_region - Encode a 24-bit SET_Q action (queue region)\n+ *\n+ * This action is a \"Forward to a queue region\" variant of the SET_Q action.\n+ *\n+ * SEM performs Implicit VSI for SET_Q action when \"no_impliciti_vsi\" is false.\n+ * WCM and LEM never perform Implicit VSI for SET_Q actions.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_set_hash_queue_region(uint8_t prec, enum cpfl_prot_eng pe, uint16_t q_base,\n+\t\t\t       uint8_t q_rgn_bits, bool no_implicit_vsi)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || q_base >= CPFL_ACT_24B_SET_Q_CNT ||\n+\t    q_rgn_bits > CPFL_ACT_24B_SET_Q_Q_RGN_BITS)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_24B_SET_Q_VALID | (uint32_t)q_base |\n+\t\t((uint32_t)q_rgn_bits << CPFL_ACT_24B_SET_Q_Q_RGN_S) |\n+\t\t(((uint32_t)pe << CPFL_ACT_24B_SET_Q_DST_PE_S) &\n+\t\t\tCPFL_ACT_24B_SET_Q_DST_PE_M);\n+\tif (no_implicit_vsi)\n+\t\tval |= CPFL_ACT_24B_SET_Q_IMPLICIT_VSI_DIS;\n+\ta.data = CPFL_ACT_MAKE_24B_A(prec, CPFL_ACT_24B_INDEX_SET_Q, val);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_mod_profile - Encode a 24-bit MOD_PROFILE action\n+ *\n+ * This action specifies a Modify profile to use for modifying the network\n+ * packet being classified.  In addition, it also provides a hint to whether\n+ * or not an accompanied MOD_ADDR action is expected and should be prefetched.\n+ *\n+ * There is only one MOD_PROFILE action slot.  If multiple classification blocks\n+ * emit this action, the precedence value and auxiliary precedence value will be\n+ * used to select one with higher precedence.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_mod_profile(uint8_t prec, uint16_t prof, uint8_t ptype_xltn_idx, bool append_act_bus,\n+\t\t     bool miss_prepend, enum cpfl_act_mod_profile_hint hint)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) ||\n+\t    prof >= CPFL_ACT_24B_MOD_PROFILE_PROF_CNT ||\n+\t    ptype_xltn_idx >= CPFL_ACT_24B_MOD_PROFILE_PTYPE_XLTN_INDEXES)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_24B_MOD_PROFILE_VALID |\n+\t\t(((uint32_t)hint << CPFL_ACT_24B_MOD_PROFILE_HINT_S) &\n+\t\t\tCPFL_ACT_24B_MOD_PROFILE_HINT_M) |\n+\t\t(((uint32_t)ptype_xltn_idx << CPFL_ACT_24B_MOD_PROFILE_XTLN_IDX_S) &\n+\t\t\tCPFL_ACT_24B_MOD_PROFILE_XTLN_IDX_M) |\n+\t\t((uint32_t)prof << CPFL_ACT_24B_MOD_PROFILE_PROF_S);\n+\tif (append_act_bus)\n+\t\tval |= CPFL_ACT_24B_MOD_PROFILE_APPEND_ACT_BUS;\n+\tif (miss_prepend)\n+\t\tval |= CPFL_ACT_24B_MOD_PROFILE_SET_MISS_PREPEND;\n+\n+\ta.data = CPFL_ACT_MAKE_24B_A(prec, CPFL_ACT_24B_INDEX_MOD_PROFILE, val);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_meter - Encode a 24-bit METER action\n+ *\n+ * Return NOP if any given input parameter is invalid.\n+ *\n+ * A bank can only be used by one of the METER action slots.  If multiple METER\n+ * actions select the same bank, the action with the highest action slot wins.\n+ * In Policer mode, METER actions at the higher indexes have precedence over\n+ * ones at lower indexes.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_meter(uint8_t slot, uint8_t prec, uint32_t idx, uint8_t bank)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t val;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || slot >= CPFL_ACT_24B_METER_SLOTS  ||\n+\t    idx >= CPFL_ACT_24B_METER_INDEX_CNT ||\n+\t    bank >= CPFL_ACT_24B_METER_BANK_CNT)\n+\t\treturn cpfl_act_nop();\n+\n+\tval = CPFL_ACT_24B_METER_VALID |\n+\t\t(uint32_t)idx << CPFL_ACT_24B_METER_INDEX_S |\n+\t\t(uint32_t)bank << CPFL_ACT_24B_METER_BANK_S;\n+\ta.data = CPFL_ACT_MAKE_24B_A(prec, CPFL_ACT_24B_INDEX_METER + slot,\n+\t\t\t\t     val);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_md8 - Encode a 24-bit SET_MD/8 action for an action slot\n+ *\n+ * This SET_MD action sets/updates a byte of a given metadata ID structure\n+ * using one of the SET_MD action slots.  This action variant can only set\n+ * one the first 16 bytes of any of the first 7 metadata types.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_set_md8(uint8_t slot, uint8_t prec, uint8_t mid, uint8_t off, uint8_t val, uint8_t mask)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t tmp;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || slot >= CPFL_ACT_24B_SET_MD_SLOTS ||\n+\t    mid > CPFL_ACT_24B_SET_MD8_TYPE_ID_MAX ||\n+\t    off > CPFL_ACT_24B_SET_MD8_OFFSET_MAX)\n+\t\treturn cpfl_act_nop();\n+\n+\ttmp = ((uint32_t)mid << CPFL_ACT_24B_SET_MD8_TYPE_ID_S) |\n+\t\t((uint32_t)off << CPFL_ACT_24B_SET_MD8_OFFSET_S) |\n+\t\t((uint32_t)mask << CPFL_ACT_24B_SET_MD8_MASK_S) |\n+\t\t((uint32_t)val << CPFL_ACT_24B_SET_MD8_VAL_S);\n+\ta.data = CPFL_ACT_MAKE_24B_B(prec, CPFL_ACT_24B_INDEX_SET_MD + slot,\n+\t\t\t\t     tmp);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_md16 - Encode a 24-bit SET_MD/16 action for an action slot\n+ *\n+ * This SET_MD action sets/updates a word of a given metadata ID structure\n+ * using one of the SET_MD action slots.  This action variant can only set\n+ * one the first 16 words of any of the first 7 metadata types.\n+ */\n+static inline union cpfl_action_set\n+cpfl_act_set_md16(uint8_t slot, uint8_t prec, uint8_t mid, uint8_t word_off, uint16_t val)\n+{\n+\tunion cpfl_action_set a;\n+\tuint32_t tmp;\n+\n+\tif (!CPFL_ACT_PREC_CHECK(prec) || slot >= CPFL_ACT_24B_SET_MD_SLOTS ||\n+\t    mid > CPFL_ACT_24B_SET_MD16_TYPE_ID_MAX ||\n+\t    word_off > CPFL_ACT_24B_SET_MD16_OFFSET_MAX)\n+\t\treturn cpfl_act_nop();\n+\n+\ttmp = ((uint32_t)CPFL_ACT_24B_SET_MD16) |\n+\t\t((uint32_t)mid << CPFL_ACT_24B_SET_MD16_TYPE_ID_S) |\n+\t\t((uint32_t)word_off << CPFL_ACT_24B_SET_MD16_OFFSET_S) |\n+\t\t((uint32_t)val << CPFL_ACT_24B_SET_MD16_VAL_S);\n+\ta.data = CPFL_ACT_MAKE_24B_B(prec, CPFL_ACT_24B_INDEX_SET_MD + slot,\n+\t\t\t\t     tmp);\n+\n+\treturn a;\n+}\n+\n+/**\n+ * cpfl_act_set_md32_ext - Encode a 24-bit SET_MD/32 action for an action slot\n+ *\n+ * This SET_MD action sets/updates a dword of a given metadata ID structure\n+ * using one of the SET_MD action slots.  This action is made up of 2 chained\n+ * action sets.  The chained action set is the first.  The base/parent action\n+ * sets is the second.\n+ */\n+static inline void\n+cpfl_act_set_md32_ext(struct cpfl_action_set_ext *ext, uint8_t slot, uint8_t prec, uint8_t mid,\n+\t\t      uint8_t off, uint32_t val)\n+{\n+\tif (slot >= CPFL_ACT_24B_SET_MD_SLOTS || !CPFL_ACT_PREC_CHECK(prec) ||\n+\t    mid >= CPFL_METADATA_ID_CNT ||\n+\t    (off + sizeof(uint32_t)) > CPFL_METADATA_STRUCT_MAX_SZ) {\n+\t\text->acts[0] = cpfl_act_nop();\n+\t\text->acts[1] = cpfl_act_nop();\n+\t} else {\n+\t\tuint32_t tmp;\n+\n+\t\t/* Chained action set comes first */\n+\t\ttmp = val >> CPFL_ACT_24B_SET_MD_AUX_32B_VAL_H_SR;\n+\t\text->acts[0].data =\n+\t\t\tCPFL_ACT_24B_SET_MD_AUX_MAKE(CPFL_ACT_24B_SET_MD_OP_32B,\n+\t\t\t\t\t\t     mid, off, tmp);\n+\n+\t\t/* Lower 24 bits of value */\n+\t\ttmp = val & CPFL_ACT_24B_SET_MD32_VAL_L_M;\n+\t\text->acts[1].data =\n+\t\t\tCPFL_ACT_MAKE_24B_B(prec,\n+\t\t\t\t\t    CPFL_ACT_24B_INDEX_SET_MD + slot,\n+\t\t\t\t\t    tmp);\n+\t}\n+}\n+\n+#endif /* _CPFL_ACTIONS_H_ */\ndiff --git a/drivers/net/cpfl/cpfl_rules.c b/drivers/net/cpfl/cpfl_rules.c\nnew file mode 100644\nindex 0000000000..3d259d3da8\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_rules.c\n@@ -0,0 +1,127 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2023 Intel Corporation\n+ */\n+\n+#include <base/idpf_controlq.h>\n+#include <stdint.h>\n+#include \"cpfl_rules.h\"\n+\n+ /**\n+  * cpfl_prep_rule_desc_common_ctx - get bit common context for descriptor\n+  */\n+static inline uint64_t\n+cpfl_prep_rule_desc_common_ctx(struct cpfl_rule_cfg_data_common *cmn_cfg)\n+{\n+\tuint64_t context = 0;\n+\n+\tswitch (cmn_cfg->opc) {\n+\tcase cpfl_ctlq_mod_query_rule:\n+\tcase cpfl_ctlq_mod_add_update_rule:\n+\t\t/* fallthrough */\n+\tcase cpfl_ctlq_sem_query_rule_hash_addr:\n+\tcase cpfl_ctlq_sem_query_del_rule_hash_addr:\n+\tcase cpfl_ctlq_sem_add_rule:\n+\tcase cpfl_ctlq_sem_del_rule:\n+\tcase cpfl_ctlq_sem_query_rule:\n+\tcase cpfl_ctlq_sem_update_rule:\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->time_sel,\n+\t\t\t\t       MEV_RULE_TIME_SEL);\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->time_sel_val,\n+\t\t\t\t       MEV_RULE_TIME_SEL_VAL);\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->host_id,\n+\t\t\t\t       MEV_RULE_HOST_ID);\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->port_num,\n+\t\t\t\t       MEV_RULE_PORT_NUM);\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->resp_req,\n+\t\t\t\t       MEV_RULE_RESP_REQ);\n+\t\tcontext |= SHIFT_VAL64(cmn_cfg->cache_wr_thru,\n+\t\t\t\t       MEV_RULE_CACHE_WR_THRU);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn context;\n+}\n+\n+/**\n+ * cpfl_prep_rule_desc_ctx - get bit context for descriptor\n+ */\n+static inline uint64_t\n+cpfl_prep_rule_desc_ctx(struct cpfl_rule_cfg_data *cfg_data)\n+{\n+\tuint64_t context = 0;\n+\n+\tcontext |= cpfl_prep_rule_desc_common_ctx(&cfg_data->common);\n+\n+\tswitch (cfg_data->common.opc) {\n+\tcase cpfl_ctlq_mod_query_rule:\n+\tcase cpfl_ctlq_mod_add_update_rule:\n+\t\tcontext |= SHIFT_VAL64(cfg_data->ext.mod_content.obj_size,\n+\t\t\t\t       MEV_RULE_MOD_OBJ_SIZE);\n+\t\tcontext |= SHIFT_VAL64(cfg_data->ext.mod_content.pin_content,\n+\t\t\t\t       MEV_RULE_PIN_MOD_CONTENT);\n+\t\tcontext |= SHIFT_VAL64(cfg_data->ext.mod_content.index,\n+\t\t\t\t       MEV_RULE_MOD_INDEX);\n+\t\tbreak;\n+\tcase cpfl_ctlq_sem_query_rule_hash_addr:\n+\tcase cpfl_ctlq_sem_query_del_rule_hash_addr:\n+\t\tcontext |= SHIFT_VAL64(cfg_data->ext.query_del_addr.obj_id,\n+\t\t\t\t       MEV_RULE_OBJ_ID);\n+\t\tcontext |= SHIFT_VAL64(cfg_data->ext.query_del_addr.obj_addr,\n+\t\t\t\t       MEV_RULE_OBJ_ADDR);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn context;\n+}\n+\n+/**\n+ * cpfl_prep_rule_desc - build descriptor data from rule config data\n+ *\n+ * note: call this function before sending rule to HW via fast path\n+ */\n+void\n+cpfl_prep_rule_desc(struct cpfl_rule_cfg_data *cfg_data,\n+\t\t    struct idpf_ctlq_msg *ctlq_msg)\n+{\n+\tuint64_t context;\n+\tuint64_t *ctlq_ctx = (uint64_t *)&ctlq_msg->ctx.indirect.context[0];\n+\n+\tcontext = cpfl_prep_rule_desc_ctx(cfg_data);\n+\t*ctlq_ctx = CPU_TO_LE64(context);\n+\tmemcpy(&ctlq_msg->cookie, &cfg_data->common.cookie, sizeof(uint64_t));\n+\tctlq_msg->opcode = (uint16_t)cfg_data->common.opc;\n+\tctlq_msg->data_len = cfg_data->common.buf_len;\n+\tctlq_msg->status = 0;\n+\tctlq_msg->ctx.indirect.payload = cfg_data->common.payload;\n+}\n+\n+/**\n+ * cpfl_prep_sem_rule_blob - build SEM rule blob data from rule entry info\n+ * note: call this function before sending rule to HW via fast path\n+ */\n+void\n+cpfl_prep_sem_rule_blob(const uint8_t *key,\n+\t\t\tuint8_t key_byte_len,\n+\t\t\tconst uint8_t *act_bytes,\n+\t\t\tuint8_t act_byte_len,\n+\t\t\tuint16_t cfg_ctrl,\n+\t\t\tunion cpfl_rule_cfg_pkt_record *rule_blob)\n+{\n+\tuint32_t *act_dst = (uint32_t *)&rule_blob->sem_rule.actions;\n+\tconst uint32_t *act_src = (const uint32_t *)act_bytes;\n+\tuint32_t i;\n+\n+\tidpf_memset(rule_blob, 0, sizeof(*rule_blob), IDPF_DMA_MEM);\n+\tidpf_memcpy(rule_blob->sem_rule.key, key, key_byte_len,\n+\t\t    CPFL_NONDMA_TO_DMA);\n+\n+\tfor (i = 0; i < act_byte_len / sizeof(uint32_t); i++)\n+\t\t*act_dst++ = CPU_TO_LE32(*act_src++);\n+\n+\trule_blob->sem_rule.cfg_ctrl[0] = cfg_ctrl & 0xFF;\n+\trule_blob->sem_rule.cfg_ctrl[1] = (cfg_ctrl >> 8) & 0xFF;\n+}\ndiff --git a/drivers/net/cpfl/cpfl_rules.h b/drivers/net/cpfl/cpfl_rules.h\nnew file mode 100644\nindex 0000000000..d23eae8e91\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_rules.h\n@@ -0,0 +1,306 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_RULES_API_H_\n+#define _CPFL_RULES_API_H_\n+\n+#include <base/idpf_controlq_api.h>\n+#include \"cpfl_actions.h\"\n+#include \"cpfl_controlq.h\"\n+\n+/* Common Bit Mask Macros */\n+#define CPFL_BIT(b)\t\t\t(1 << (b))\n+\n+#define MAKE_MASK(type, mask, shift)\t((u##type) (mask) << (shift))\n+#define SHIFT_VAL_LT(type, val, field)\t\t\\\n+\t\t(((u##type)(val) << field##_S) & field##_M)\n+#define SHIFT_VAL_RT(type, val, field)\t\t\\\n+\t\t(((u##type)(val) & field##_M) >> field##_S)\n+\n+#define MAKE_MASK_VAL(type, bit_len)\t(((u##type)0x01 << (bit_len)) - 1)\n+#define MAKE_MASK_VAL16(bit_len)\tMAKE_MASK_VAL(16, bit_len)\n+#define MAKE_MASK_VAL64(bit_len)\tMAKE_MASK_VAL(64, bit_len)\n+\n+#define MAKE_MASK64(mask, shift)\tMAKE_MASK(64, mask, shift)\n+#define MAKE_MASK16(mask, shift)\tMAKE_MASK(16, mask, shift)\n+#define MAKE_MASK32(mask, shift)\tMAKE_MASK(32, mask, shift)\n+\n+/* Make masks with bit length and left-shifting count */\n+#define MAKE_SMASK(type, bits, shift)\t\\\n+\t((((u##type)1 << (bits)) - 1) << (shift))\n+#define MAKE_SMASK64(bits, shift)\tMAKE_SMASK(64, bits, shift)\n+#define MAKE_SMASK32(bits, shift)\tMAKE_SMASK(32, bits, shift)\n+#define MAKE_SMASK16(bits, shift)\tMAKE_SMASK(16, bits, shift)\n+\n+#define SHIFT_VAL64(val, field)\t\tSHIFT_VAL_LT(64, val, field)\n+#define SHIFT_VAL32(val, field)\t\tSHIFT_VAL_LT(32, val, field)\n+#define SHIFT_VAL16(val, field)\t\tSHIFT_VAL_LT(16, val, field)\n+\n+/* Rule Config queue opcodes */\n+enum cpfl_ctlq_rule_cfg_opc {\n+\tcpfl_ctlq_sem_add_rule\t\t\t\t= 0x1303,\n+\tcpfl_ctlq_sem_update_rule\t\t\t= 0x1304,\n+\tcpfl_ctlq_sem_del_rule\t\t\t\t= 0x1305,\n+\tcpfl_ctlq_sem_query_rule\t\t\t= 0x1306,\n+\tcpfl_ctlq_sem_query_rule_hash_addr\t\t= 0x1307,\n+\tcpfl_ctlq_sem_query_del_rule_hash_addr\t\t= 0x1308,\n+\n+\tcpfl_ctlq_mod_add_update_rule\t\t\t= 0x1360,\n+\tcpfl_ctlq_mod_query_rule\t\t\t= 0x1361,\n+};\n+\n+enum cpfl_cfg_pkt_error_code {\n+\tCPFL_CFG_PKT_ERR_OK = 0,\n+\tCPFL_CFG_PKT_ERR_ESRCH = 1,     /* Bad opcode */\n+\tCPFL_CFG_PKT_ERR_EEXIST = 2,    /* Entry Already exists */\n+\tCPFL_CFG_PKT_ERR_ENOSPC = 4,    /* No space left in the table*/\n+\tCPFL_CFG_PKT_ERR_ERANGE = 5,    /* Parameter out of range */\n+\tCPFL_CFG_PKT_ERR_ESBCOMP = 6,   /* Completion Error */\n+\tCPFL_CFG_PKT_ERR_ENOPIN = 7,    /* Entry cannot be pinned in cache */\n+\tCPFL_CFG_PKT_ERR_ENOTFND = 8,   /* Entry Not exists */\n+\tCPFL_CFG_PKT_ERR_EMAXCOL = 9    /* Max Hash Collision */\n+};\n+\n+/* macros for creating context for rule descriptor */\n+#define MEV_RULE_VSI_ID_S\t\t0\n+#define MEV_RULE_VSI_ID_M\t\t\\\n+\t\tMAKE_MASK64(0x7FF, MEV_RULE_VSI_ID_S)\n+\n+#define MEV_RULE_TIME_SEL_S\t\t13\n+#define MEV_RULE_TIME_SEL_M\t\t\\\n+\t\tMAKE_MASK64(0x3, MEV_RULE_TIME_SEL_S)\n+\n+#define MEV_RULE_TIME_SEL_VAL_S\t\t15\n+#define MEV_RULE_TIME_SEL_VAL_M\t\t\\\n+\t\tMAKE_MASK64(0x1, MEV_RULE_TIME_SEL_VAL_S)\n+\n+#define MEV_RULE_PORT_NUM_S\t\t16\n+#define MEV_RULE_HOST_ID_S\t\t18\n+#define MEV_RULE_PORT_NUM_M\t\t\\\n+\t\tMAKE_MASK64(0x3, MEV_RULE_PORT_NUM_S)\n+#define MEV_RULE_HOST_ID_M\t\t\\\n+\t\tMAKE_MASK64(0x7, MEV_RULE_HOST_ID_S)\n+\n+#define MEV_RULE_CACHE_WR_THRU_S\t21\n+#define MEV_RULE_CACHE_WR_THRU_M\t\\\n+\t\tMAKE_MASK64(0x1, MEV_RULE_CACHE_WR_THRU_S)\n+\n+#define MEV_RULE_RESP_REQ_S\t\t22\n+#define MEV_RULE_RESP_REQ_M\t\t\\\n+\t\tMAKE_MASK64(0x3, MEV_RULE_RESP_REQ_S)\n+#define MEV_RULE_OBJ_ADDR_S\t\t24\n+#define MEV_RULE_OBJ_ADDR_M\t\t\\\n+\t\tMAKE_MASK64(0x7FFFFFF, MEV_RULE_OBJ_ADDR_S)\n+#define MEV_RULE_OBJ_ID_S\t\t59\n+#define MEV_RULE_OBJ_ID_M\t\t\\\n+\t\tMAKE_MASK64((uint64_t)0x3, MEV_RULE_OBJ_ID_S)\n+\n+/* macros for creating CFG_CTRL for sem/lem rule blob */\n+#define MEV_RULE_CFG_CTRL_PROF_ID_S\t\t\t0\n+#define MEV_RULE_CFG_CTRL_PROF_ID_M\t\t\t\\\n+\t\tMAKE_MASK16(0x7FF, MEV_RULE_CFG_CTRL_PROF_ID_S)\n+\n+#define MEV_RULE_CFG_CTRL_SUB_PROF_ID_S\t\t11\n+#define MEV_RULE_CFG_CTRL_SUB_PROF_ID_M\t\t\\\n+\t\tMAKE_MASK16(0x3, MEV_RULE_CFG_CTRL_SUB_PROF_ID_S)\n+#define MEV_RULE_CFG_CTRL_PIN_CACHE_S\t\t13\n+#define MEV_RULE_CFG_CTRL_PIN_CACHE_M\t\t\\\n+\t\tMAKE_MASK16(0x1, MEV_RULE_CFG_CTRL_PIN_CACHE_S)\n+#define MEV_RULE_CFG_CTRL_CLEAR_MIRROR_S\t14\n+#define MEV_RULE_CFG_CTRL_CLEAR_MIRROR_M\t\\\n+\t\tMAKE_MASK16(0x1, MEV_RULE_CFG_CTRL_CLEAR_MIRROR_S)\n+#define MEV_RULE_CFG_CTRL_FIXED_FETCH_S\t\t15\n+#define MEV_RULE_CFG_CTRL_FIXED_FETCH_M\t\t\\\n+\t\tMAKE_MASK16(0x1, MEV_RULE_CFG_CTRL_FIXED_FETCH_S)\n+\n+/**\n+ * macro to build the CFG_CTRL for rule packet data, which is one of\n+ * cpfl_prep_sem_rule_blob()'s input parameter.\n+ */\n+ /* build SEM CFG_CTRL*/\n+#define CPFL_GET_MEV_SEM_RULE_CFG_CTRL(prof_id, sub_prof_id,\t\t       \\\n+\t\t\t\t       pin_to_cache, fixed_fetch)\t       \\\n+\t\t(SHIFT_VAL16((prof_id), MEV_RULE_CFG_CTRL_PROF_ID)\t     | \\\n+\t\t SHIFT_VAL16((sub_prof_id), MEV_RULE_CFG_CTRL_SUB_PROF_ID)   | \\\n+\t\t SHIFT_VAL16((pin_to_cache), MEV_RULE_CFG_CTRL_PIN_CACHE)    | \\\n+\t\t SHIFT_VAL16((fixed_fetch), MEV_RULE_CFG_CTRL_FIXED_FETCH))\n+\n+/* build LEM CFG_CTRL*/\n+#define CPFL_GET_MEV_LEM_RULE_CFG_CTRL(prof_id, pin_to_cache, clear_mirror)    \\\n+\t\t(SHIFT_VAL16(prof_id, MEV_RULE_CFG_CTRL_PROF_ID)             | \\\n+\t\t SHIFT_VAL16(pin_to_cache, MEV_RULE_CFG_CTRL_PIN_CACHE)      | \\\n+\t\t SHIFT_VAL16(clear_mirror, MEV_RULE_CFG_CTRL_CLEAR_MIRROR))\n+\n+/* macros for creating mod content config packets */\n+#define MEV_RULE_MOD_INDEX_S\t\t24\n+#define MEV_RULE_MOD_INDEX_M\t\t\\\n+\t\tMAKE_MASK64(0xFFFFFFFF, MEV_RULE_MOD_INDEX_S)\n+\n+#define MEV_RULE_PIN_MOD_CONTENT_S\t62\n+#define MEV_RULE_PIN_MOD_CONTENT_M\t\\\n+\t\tMAKE_MASK64((uint64_t)0x1, MEV_RULE_PIN_MOD_CONTENT_S)\n+#define MEV_RULE_MOD_OBJ_SIZE_S\t\t63\n+#define MEV_RULE_MOD_OBJ_SIZE_M\t\t\\\n+\t\tMAKE_MASK64((uint64_t)0x1, MEV_RULE_MOD_OBJ_SIZE_S)\n+\n+/**\n+ * struct cpfl_sem_rule_cfg_pkt - Describes rule information for SEM\n+ * note: The key may be in mixed big/little endian format, the rest of members\n+ * are in little endian\n+ */\n+struct cpfl_sem_rule_cfg_pkt {\n+#define MEV_SEM_RULE_KEY_SIZE 128\n+\tuint8_t key[MEV_SEM_RULE_KEY_SIZE];\n+\n+#define MEV_SEM_RULE_ACT_SIZE 72\n+\tuint8_t actions[MEV_SEM_RULE_ACT_SIZE];\n+\n+\t/* Bit(s):\n+\t * 10:0 : PROFILE_ID\n+\t * 12:11: SUB_PROF_ID (used for SEM only)\n+\t * 13   : pin the SEM key content into the cache\n+\t * 14   : Reserved\n+\t * 15   : Fixed_fetch\n+\t */\n+\tuint8_t cfg_ctrl[2];\n+\n+\t/* Bit(s):\n+\t * 0:     valid\n+\t * 15:1:  Hints\n+\t * 26:16: PROFILE_ID, the profile associated with the entry\n+\t * 31:27: PF\n+\t * 55:32: FLOW ID (assigned by HW)\n+\t * 63:56: EPOCH\n+\t */\n+\tuint8_t ctrl_word[8];\n+\tuint8_t padding[46];\n+};\n+\n+/**\n+ * union cpfl_rule_cfg_pkt_record - Describes rule data blob\n+ */\n+union cpfl_rule_cfg_pkt_record {\n+\tstruct cpfl_sem_rule_cfg_pkt sem_rule;\n+\tuint8_t pkt_data[256];\n+\tuint8_t mod_blob[256];\n+};\n+\n+/**\n+ * cpfl_rule_query_addr - LEM/SEM Rule Query Address structure\n+ */\n+struct cpfl_rule_query_addr {\n+\tuint8_t\tobj_id;\n+\tuint32_t\tobj_addr;\n+};\n+\n+/**\n+ * cpfl_rule_query_del_addr - Rule Query and Delete Address\n+ */\n+struct cpfl_rule_query_del_addr {\n+\tuint8_t\tobj_id;\n+\tuint32_t\tobj_addr;\n+};\n+\n+/**\n+ * cpfl_rule_mod_content - MOD Rule Content\n+ */\n+struct cpfl_rule_mod_content {\n+\tuint8_t\tobj_size;\n+\tuint8_t\tpin_content;\n+\tuint32_t\tindex;\n+};\n+\n+/**\n+ * cpfl_rule_cfg_data_common - data struct for all rule opcodes\n+ *note: some rules may only require part of structure\n+ */\n+struct cpfl_rule_cfg_data_common {\n+\tenum cpfl_ctlq_rule_cfg_opc opc;\n+\tuint64_t\tcookie;\n+\tuint16_t\tvsi_id;\n+\tuint8_t\tport_num;\n+\tuint8_t\thost_id;\n+\tuint8_t\ttime_sel;\n+\tuint8_t\ttime_sel_val;\n+\tuint8_t\tcache_wr_thru;\n+\tuint8_t\tresp_req;\n+\tuint32_t\tret_val;\n+\tuint16_t\tbuf_len;\n+\tstruct idpf_dma_mem *payload;\n+};\n+\n+/**\n+ * cpfl_rule_cfg_data - rule config data\n+ * note: Before sending rule to HW, caller needs to fill\n+ *       in this struct then call cpfl_prep_rule_desc().\n+ */\n+struct cpfl_rule_cfg_data {\n+\tstruct cpfl_rule_cfg_data_common common;\n+\tunion {\n+\t\tstruct cpfl_rule_query_addr query_addr;\n+\t\tstruct cpfl_rule_query_del_addr query_del_addr;\n+\t\tstruct cpfl_rule_mod_content mod_content;\n+\t} ext;\n+};\n+\n+/**\n+ * cpfl_fill_rule_mod_content - fill info for mod content\n+ */\n+static inline void\n+cpfl_fill_rule_mod_content(uint8_t mod_obj_size,\n+\t\t\t   uint8_t pin_mod_content,\n+\t\t\t   uint32_t mod_index,\n+\t\t\t   struct cpfl_rule_mod_content *mod_content)\n+{\n+\tmod_content->obj_size = mod_obj_size;\n+\tmod_content->pin_content = pin_mod_content;\n+\tmod_content->index = mod_index;\n+}\n+\n+/**\n+ * cpfl_fill_rule_cfg_data_common - fill in rule config data for all opcodes\n+ * note: call this function before calls cpfl_prep_rule_desc()\n+ */\n+static inline void\n+cpfl_fill_rule_cfg_data_common(enum cpfl_ctlq_rule_cfg_opc opc,\n+\t\t\t       uint64_t cookie,\n+\t\t\t       uint16_t vsi_id,\n+\t\t\t       uint8_t port_num,\n+\t\t\t       uint8_t host_id,\n+\t\t\t       uint8_t time_sel,\n+\t\t\t       uint8_t time_sel_val,\n+\t\t\t       uint8_t cache_wr_thru,\n+\t\t\t       uint8_t resp_req,\n+\t\t\t       uint16_t payload_len,\n+\t\t\t       struct idpf_dma_mem *payload,\n+\t\t\t       struct cpfl_rule_cfg_data_common *cfg_cmn)\n+{\n+\tcfg_cmn->opc = opc;\n+\tcfg_cmn->cookie = cookie;\n+\tcfg_cmn->vsi_id = vsi_id;\n+\tcfg_cmn->port_num = port_num;\n+\tcfg_cmn->resp_req = resp_req;\n+\tcfg_cmn->ret_val = 0;\n+\tcfg_cmn->host_id = host_id;\n+\tcfg_cmn->time_sel = time_sel;\n+\tcfg_cmn->time_sel_val = time_sel_val;\n+\tcfg_cmn->cache_wr_thru = cache_wr_thru;\n+\n+\tcfg_cmn->buf_len = payload_len;\n+\tcfg_cmn->payload = payload;\n+}\n+\n+void\n+cpfl_prep_rule_desc(struct cpfl_rule_cfg_data *cfg_data,\n+\t\t    struct idpf_ctlq_msg *ctlq_msg);\n+\n+void\n+cpfl_prep_sem_rule_blob(const uint8_t *key,\n+\t\t\tuint8_t key_byte_len,\n+\t\t\tconst uint8_t *act_bytes,\n+\t\t\tuint8_t act_byte_len,\n+\t\t\tuint16_t cfg_ctrl,\n+\t\t\tunion cpfl_rule_cfg_pkt_record *rule_blob);\n+\n+#endif /* _CPFL_RULES_API_H_ */\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex 290ff1e655..e2b6621cea 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -19,6 +19,7 @@ sources = files(\n         'cpfl_vchnl.c',\n         'cpfl_representor.c',\n         'cpfl_controlq.c',\n+\t'cpfl_rules.c',\n )\n \n if arch_subdir == 'x86'\n",
    "prefixes": [
        "v9",
        "5/9"
    ]
}