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GET /api/patches/131981/?format=api
{ "id": 131981, "url": "http://patches.dpdk.org/api/patches/131981/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230926181703.2268199-9-yuying.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230926181703.2268199-9-yuying.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230926181703.2268199-9-yuying.zhang@intel.com", "date": "2023-09-26T18:17:03", "name": "[v7,8/8] net/cpfl: add flow support for representor", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bd2b7383311cabd29e55130f792b3f54191016f0", "submitter": { "id": 1844, "url": "http://patches.dpdk.org/api/people/1844/?format=api", "name": "Zhang, Yuying", "email": "yuying.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230926181703.2268199-9-yuying.zhang@intel.com/mbox/", "series": [ { "id": 29645, "url": "http://patches.dpdk.org/api/series/29645/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29645", "date": "2023-09-26T18:16:55", "name": "add rte flow support for cpfl", "version": 7, "mbox": "http://patches.dpdk.org/series/29645/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131981/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/131981/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 094EA42646;\n\tTue, 26 Sep 2023 20:18:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C1C1A40A87;\n\tTue, 26 Sep 2023 20:17:49 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id D99CE40A75\n for <dev@dpdk.org>; Tue, 26 Sep 2023 20:17:43 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Sep 2023 11:17:43 -0700", "from dpdk-wenjing-02.sh.intel.com ([10.67.119.3])\n by fmsmga008.fm.intel.com with ESMTP; 26 Sep 2023 11:17:41 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695752264; x=1727288264;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=SoaS14R8mUz0gegsQmu6UX8VMQv1SueqYO3jhJVrpCc=;\n b=K3xQTQbdrduEvNrrG1YCP09kefFk4DqgsjesSfJ+Vv6pzQuKjmN5vtkL\n xO/nO6Hh9dvCDAyuDEWm48J0XvvMNUmey/JMnhDiIyVLtT+T+P3XXkiW6\n KBwyaIfT4GwiRHUoby22DEtMA7WlJyuXCQUtwE6CXM1WR6n8otUPEyQil\n N28/+CJZS9hJVPKClQz90c4HAVpJmto3aSKsefNuFezkdxnY41JXqomEl\n WNFATrIJJIWmQwQ+EOzfdDPdrvbyaq08922m28NPdCkl+iJGWy1a12UuT\n du/2ebgWeLB/tvUWwJ5pomyDZJJec2we+epGMsMoZKK762Yh3x21djqHt Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10845\"; a=\"412549763\"", "E=Sophos;i=\"6.03,178,1694761200\"; d=\"scan'208\";a=\"412549763\"", "E=McAfee;i=\"6600,9927,10845\"; a=\"814576874\"", "E=Sophos;i=\"6.03,178,1694761200\"; d=\"scan'208\";a=\"814576874\"" ], "X-ExtLoop1": "1", "From": "yuying.zhang@intel.com", "To": "yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com,\n jingjing.wu@intel.com, beilei.xing@intel.com", "Subject": "[PATCH v7 8/8] net/cpfl: add flow support for representor", "Date": "Tue, 26 Sep 2023 18:17:03 +0000", "Message-Id": "<20230926181703.2268199-9-yuying.zhang@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230926181703.2268199-1-yuying.zhang@intel.com>", "References": "<20230822010226.17783-1-yuying.zhang@intel.com>\n <20230926181703.2268199-1-yuying.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yuying Zhang <yuying.zhang@intel.com>\n\nAdd flow support for representor, so representor can\ncreate, destroy, validate and flush rules.\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n doc/guides/nics/cpfl.rst | 19 +++++-\n doc/guides/rel_notes/release_23_11.rst | 1 +\n drivers/net/cpfl/cpfl_flow_engine_fxp.c | 88 ++++++++++++++++++++++++-\n drivers/net/cpfl/cpfl_representor.c | 29 ++++++++\n 4 files changed, 133 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst\nindex e17347d15c..ee2fabd99c 100644\n--- a/doc/guides/nics/cpfl.rst\n+++ b/doc/guides/nics/cpfl.rst\n@@ -197,8 +197,23 @@ low level hardware resources.\n \n * For Ubuntu, it can be installed using `apt install libjansson-dev`\n \n-- run testpmd with the json file\n+- run testpmd with the json file, create two vports and two VF representors\n \n .. code-block:: console\n \n- dpdk-testpmd -c 0x3 -n 4 -a 0000:af:00.6,vport=[0],flow_parser=\"refpkg.json\" -- -i\n+ dpdk-testpmd -c 0x3 -n 4 -a 0000:af:00.6,vport=[0-1],representor=vf[0,1],flow_parser=\"refpkg.json\" -- -i\n+\n+#. Create one flow to forward ETH-IPV4-TCP from I/O port to a local(CPF's) vport. Flow should be created on\n+ vport X. Group M should match fxp module. Action port_representor Y means forward packet to local vport Y.\n+ If want to send a packet to VF representor, action represented_port can be used::\n+\n+ .. code-block:: console\n+\n+ flow create X ingress group M pattern eth dst is 00:01:00:00:03:14 / ipv4 src is 192.168.0.1 \\\n+ dst is 192.168.0.2 / tcp / end actions port_representor port_id Y / end\n+\n+#. Send a matched packet, and it should be displayed on PMD::\n+\n+ .. code-block:: console\n+\n+ sendp(Ether(dst='00:01:00:00:03:14')/IP(src='192.168.0.1',dst='192.168.0.2')/TCP(),iface=\"ens25f0\")\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 3d9be208d0..bad71ad3fd 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -81,6 +81,7 @@ New Features\n * **Updated Intel cpfl driver.**\n \n * Added support for port representor.\n+ * Added support for rte_flow.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/cpfl/cpfl_flow_engine_fxp.c b/drivers/net/cpfl/cpfl_flow_engine_fxp.c\nindex 154af5bd35..fed18d8349 100644\n--- a/drivers/net/cpfl/cpfl_flow_engine_fxp.c\n+++ b/drivers/net/cpfl/cpfl_flow_engine_fxp.c\n@@ -73,6 +73,7 @@ cpfl_fxp_create(struct rte_eth_dev *dev,\n \tstruct cpfl_adapter_ext *ad = itf->adapter;\n \tstruct cpfl_rule_info_meta *rim = meta;\n \tstruct cpfl_vport *vport;\n+\tstruct cpfl_repr *repr;\n \n \tif (!rim)\n \t\treturn ret;\n@@ -83,6 +84,10 @@ cpfl_fxp_create(struct rte_eth_dev *dev,\n \t\t * Even index is tx queue and odd index is rx queue.\n \t\t */\n \t\tcpq_id = vport->base.devarg_id * 2;\n+\t} else if (itf->type == CPFL_ITF_TYPE_REPRESENTOR) {\n+\t\trepr = (struct cpfl_repr *)itf;\n+\t\tcpq_id = ((repr->repr_id.pf_id + repr->repr_id.vf_id) &\n+\t\t\t (CPFL_TX_CFGQ_NUM - 1)) * 2;\n \t} else {\n \t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n \t\t\t\t \"fail to find correct control queue\");\n@@ -122,6 +127,7 @@ cpfl_fxp_destroy(struct rte_eth_dev *dev,\n \tstruct cpfl_rule_info_meta *rim;\n \tuint32_t i;\n \tstruct cpfl_vport *vport;\n+\tstruct cpfl_repr *repr;\n \n \trim = flow->rule;\n \tif (!rim) {\n@@ -135,6 +141,10 @@ cpfl_fxp_destroy(struct rte_eth_dev *dev,\n \tif (itf->type == CPFL_ITF_TYPE_VPORT) {\n \t\tvport = (struct cpfl_vport *)itf;\n \t\tcpq_id = vport->base.devarg_id * 2;\n+\t} else if (itf->type == CPFL_ITF_TYPE_REPRESENTOR) {\n+\t\trepr = (struct cpfl_repr *)itf;\n+\t\tcpq_id = ((repr->repr_id.pf_id + repr->repr_id.vf_id) &\n+\t\t\t (CPFL_TX_CFGQ_NUM - 1)) * 2;\n \t} else {\n \t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n \t\t\t\t \"fail to find correct control queue\");\n@@ -257,6 +267,7 @@ cpfl_fxp_parse_action(struct cpfl_itf *itf,\n \tint queue_id = -1;\n \tbool fwd_vsi = false;\n \tbool fwd_q = false;\n+\tbool is_vsi;\n \tuint32_t i;\n \tstruct cpfl_rule_info *rinfo = &rim->rules[index];\n \tunion cpfl_action_set *act_set = (void *)rinfo->act_bytes;\n@@ -267,6 +278,7 @@ cpfl_fxp_parse_action(struct cpfl_itf *itf,\n \t\taction_type = action->type;\n \t\tswitch (action_type) {\n \t\tcase RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:\n+\t\tcase RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:\n \t\t\tif (!fwd_vsi)\n \t\t\t\tfwd_vsi = true;\n \t\t\telse\n@@ -285,12 +297,20 @@ cpfl_fxp_parse_action(struct cpfl_itf *itf,\n \t\t\t\tqueue_id = CPFL_INVALID_QUEUE_ID;\n \t\t\t}\n \n-\t\t\tdev_id = cpfl_get_vsi_id(dst_itf);\n+\t\t\tis_vsi = (action_type == RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR ||\n+\t\t\t\t dst_itf->type == CPFL_ITF_TYPE_REPRESENTOR);\n+\t\t\tif (is_vsi)\n+\t\t\t\tdev_id = cpfl_get_vsi_id(dst_itf);\n+\t\t\telse\n+\t\t\t\tdev_id = cpfl_get_port_id(dst_itf);\n \n \t\t\tif (dev_id == CPFL_INVALID_HW_ID)\n \t\t\t\tgoto err;\n \n-\t\t\t*act_set = cpfl_act_fwd_vsi(0, priority, 0, dev_id);\n+\t\t\tif (is_vsi)\n+\t\t\t\t*act_set = cpfl_act_fwd_vsi(0, priority, 0, dev_id);\n+\t\t\telse\n+\t\t\t\t*act_set = cpfl_act_fwd_port(0, priority, 0, dev_id);\n \t\t\tact_set++;\n \t\t\trinfo->act_byte_len += sizeof(union cpfl_action_set);\n \t\t\tbreak;\n@@ -414,6 +434,64 @@ cpfl_is_mod_action(const struct rte_flow_action actions[])\n \treturn false;\n }\n \n+static bool\n+cpfl_fxp_get_metadata_port(struct cpfl_itf *itf,\n+\t\t\t const struct rte_flow_action actions[])\n+{\n+\tconst struct rte_flow_action *action;\n+\tenum rte_flow_action_type action_type;\n+\tconst struct rte_flow_action_ethdev *ethdev;\n+\tstruct cpfl_itf *target_itf;\n+\tbool ret;\n+\n+\tif (itf->type == CPFL_ITF_TYPE_VPORT) {\n+\t\tret = cpfl_metadata_write_port_id(itf);\n+\t\tif (!ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"fail to write port id\");\n+\t\t\treturn false;\n+\t\t}\n+\t}\n+\n+\tret = cpfl_metadata_write_sourcevsi(itf);\n+\tif (!ret) {\n+\t\tPMD_DRV_LOG(ERR, \"fail to write source vsi id\");\n+\t\treturn false;\n+\t}\n+\n+\tret = cpfl_metadata_write_vsi(itf);\n+\tif (!ret) {\n+\t\tPMD_DRV_LOG(ERR, \"fail to write vsi id\");\n+\t\treturn false;\n+\t}\n+\n+\tif (!actions || actions->type == RTE_FLOW_ACTION_TYPE_END)\n+\t\treturn false;\n+\n+\tfor (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {\n+\t\taction_type = action->type;\n+\t\tswitch (action_type) {\n+\t\tcase RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:\n+\t\tcase RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:\n+\t\t\tethdev = (const struct rte_flow_action_ethdev *)action->conf;\n+\t\t\ttarget_itf = cpfl_get_itf_by_port_id(ethdev->port_id);\n+\t\t\tif (!target_itf) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"fail to get target_itf by port id\");\n+\t\t\t\treturn false;\n+\t\t\t}\n+\t\t\tret = cpfl_metadata_write_targetvsi(target_itf);\n+\t\t\tif (!ret) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"fail to write target vsi id\");\n+\t\t\t\treturn false;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n+\t\t}\n+\t}\n+\n+\treturn true;\n+}\n+\n static int\n cpfl_fxp_parse_pattern_action(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_attr *attr,\n@@ -430,6 +508,12 @@ cpfl_fxp_parse_pattern_action(struct rte_eth_dev *dev,\n \tstruct cpfl_rule_info_meta *rim;\n \tint ret;\n \n+\tret = cpfl_fxp_get_metadata_port(itf, actions);\n+\tif (!ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to save metadata.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \tret = cpfl_flow_parse_items(itf, adapter->flow_parser, pattern, attr, &pr_action);\n \tif (ret) {\n \t\tPMD_DRV_LOG(ERR, \"No Match pattern support.\");\ndiff --git a/drivers/net/cpfl/cpfl_representor.c b/drivers/net/cpfl/cpfl_representor.c\nindex 4d15a26c80..de3b426727 100644\n--- a/drivers/net/cpfl/cpfl_representor.c\n+++ b/drivers/net/cpfl/cpfl_representor.c\n@@ -4,6 +4,8 @@\n \n #include \"cpfl_representor.h\"\n #include \"cpfl_rxtx.h\"\n+#include \"cpfl_flow.h\"\n+#include \"cpfl_rules.h\"\n \n static int\n cpfl_repr_allowlist_update(struct cpfl_adapter_ext *adapter,\n@@ -374,6 +376,22 @@ cpfl_repr_link_update(struct rte_eth_dev *ethdev,\n \treturn 0;\n }\n \n+static int\n+cpfl_dev_repr_flow_ops_get(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_ops **ops)\n+{\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+#ifdef RTE_HAS_JANSSON\n+\t*ops = &cpfl_flow_ops;\n+#else\n+\t*ops = NULL;\n+\tPMD_DRV_LOG(NOTICE, \"not support rte_flow, please install json-c library.\");\n+#endif\n+\treturn 0;\n+}\n+\n static const struct eth_dev_ops cpfl_repr_dev_ops = {\n \t.dev_start\t\t= cpfl_repr_dev_start,\n \t.dev_stop\t\t= cpfl_repr_dev_stop,\n@@ -385,6 +403,7 @@ static const struct eth_dev_ops cpfl_repr_dev_ops = {\n \t.tx_queue_setup\t\t= cpfl_repr_tx_queue_setup,\n \n \t.link_update\t\t= cpfl_repr_link_update,\n+\t.flow_ops_get\t\t= cpfl_dev_repr_flow_ops_get,\n };\n \n static int\n@@ -393,6 +412,7 @@ cpfl_repr_init(struct rte_eth_dev *eth_dev, void *init_param)\n \tstruct cpfl_repr *repr = CPFL_DEV_TO_REPR(eth_dev);\n \tstruct cpfl_repr_param *param = init_param;\n \tstruct cpfl_adapter_ext *adapter = param->adapter;\n+\tint ret;\n \n \trepr->repr_id = param->repr_id;\n \trepr->vport_info = param->vport_info;\n@@ -402,6 +422,15 @@ cpfl_repr_init(struct rte_eth_dev *eth_dev, void *init_param)\n \tif (repr->vport_info->vport.info.vport_status == CPCHNL2_VPORT_STATUS_ENABLED)\n \t\trepr->func_up = true;\n \n+\tTAILQ_INIT(&repr->itf.flow_list);\n+\tmemset(repr->itf.dma, 0, sizeof(repr->itf.dma));\n+\tmemset(repr->itf.msg, 0, sizeof(repr->itf.msg));\n+\tret = cpfl_alloc_dma_mem_batch(&repr->itf.flow_dma, repr->itf.dma,\n+\t\t\t\t sizeof(union cpfl_rule_cfg_pkt_record),\n+\t\t\t\t CPFL_FLOW_BATCH_SIZE);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \teth_dev->dev_ops = &cpfl_repr_dev_ops;\n \n \teth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;\n", "prefixes": [ "v7", "8/8" ] }