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GET /api/patches/131865/?format=api
{ "id": 131865, "url": "http://patches.dpdk.org/api/patches/131865/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230925103324.4137053-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230925103324.4137053-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230925103324.4137053-2-qi.z.zhang@intel.com", "date": "2023-09-25T10:33:20", "name": "[v4,1/5] net/ice: remove pipeline mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3adb96d92a62c256b96fa20eaa4bc1454996e601", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230925103324.4137053-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 29613, "url": "http://patches.dpdk.org/api/series/29613/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29613", "date": "2023-09-25T10:33:19", "name": "net/ice: refactor rte_flow", "version": 4, "mbox": "http://patches.dpdk.org/series/29613/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131865/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 52C9742630;\n\tMon, 25 Sep 2023 04:13:20 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 966C7402D9;\n\tMon, 25 Sep 2023 04:13:19 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 1F287402CD\n for <dev@dpdk.org>; Mon, 25 Sep 2023 04:13:16 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Sep 2023 19:13:16 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.37])\n by orsmga008.jf.intel.com with ESMTP; 24 Sep 2023 19:13:14 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695607997; x=1727143997;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=eX4Pfc9cCveVnLUF4SqH94EjaG5vFZZ5TbdoheiPqC4=;\n b=jQlKauyi6JDNyaP5R8lM3XfBqDN85TKzyo7cVH6Mpnc9bre0XD0nurYu\n ozjHFHDqNYW+f1gCsQdgVTEzoNCXOr8Gc2XrSFcWbmwf/rGX4q0GlE26z\n XCitMG1Nkopb5IsvvJZ1Y3bofxYcvrGQZs3y8Qsar7CmVkJUQIsKhtC99\n NBJcF38JLCHANApEPW3hrpGKvqjsEud+MGGNufLisbVcQPBSRnb659Yw9\n keCRUPksWp309E2TrJmAzJt+AY/I/HR8FkXKkb1NaZJAuW8tLebPiTm6i\n QVUFmWUrRnUw1KJ4SgBoEB/QJkRdqRyTgD5iFl/40WJKLQmNAnQrv7jSz g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10843\"; a=\"384978671\"", "E=Sophos;i=\"6.03,174,1694761200\"; d=\"scan'208\";a=\"384978671\"", "E=McAfee;i=\"6600,9927,10843\"; a=\"777501952\"", "E=Sophos;i=\"6.03,174,1694761200\"; d=\"scan'208\";a=\"777501952\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "zhichaox.zeng@intel.com,\n\tdev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>", "Subject": "[PATCH v4 1/5] net/ice: remove pipeline mode", "Date": "Mon, 25 Sep 2023 06:33:20 -0400", "Message-Id": "<20230925103324.4137053-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20230925103324.4137053-1-qi.z.zhang@intel.com>", "References": "<20230814202616.3346652-1-qi.z.zhang@intel.com>\n <20230925103324.4137053-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This marks the initial phase of refactoring the ice rte_flow\nimplementation.\n\nThe combination of switch and fdir rules within the same syntax has led\nto inconvenient user experiences. Naturally, the switch filter and fdir\nfilter represent distinct pipeline stages with differing hardware\ncapabilities.\n\nTo address this, we have made the decision to assign each stage to a\nseparate rte_flow group. This will allow users to clearly specify their\nintentions when creating a rule. Consequently, the need for a pipeline\nmode can be removed.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n doc/guides/nics/ice.rst | 19 -----\n drivers/net/ice/ice_ethdev.c | 8 --\n drivers/net/ice/ice_ethdev.h | 2 -\n drivers/net/ice/ice_fdir_filter.c | 2 +-\n drivers/net/ice/ice_generic_flow.c | 120 ++++++++--------------------\n drivers/net/ice/ice_generic_flow.h | 6 +-\n drivers/net/ice/ice_switch_filter.c | 118 +--------------------------\n 7 files changed, 40 insertions(+), 235 deletions(-)", "diff": "diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst\nindex c351c6bd74..5a47109c3f 100644\n--- a/doc/guides/nics/ice.rst\n+++ b/doc/guides/nics/ice.rst\n@@ -90,25 +90,6 @@ Runtime Configuration\n NOTE: In Safe mode, only very limited features are available, features like RSS,\n checksum, fdir, tunneling ... are all disabled.\n \n-- ``Generic Flow Pipeline Mode Support`` (default ``0``)\n-\n- In pipeline mode, a flow can be set at one specific stage by setting parameter\n- ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with\n- priority 0 located at the first pipeline stage which typically be used as a firewall\n- to drop the packet on a blocklist(we called it permission stage). At this stage,\n- flow rules are created for the device's exact match engine: switch. Flows with priority\n- !0 located at the second stage, typically packets are classified here and be steered to\n- specific queue or queue group (we called it distribution stage), At this stage, flow\n- rules are created for device's flow director engine.\n- For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director\n- rule or a switch rule depends on its pattern/action and the resource allocation situation,\n- all flows are virtually at the same pipeline stage.\n- By default, generic flow API is enabled in none-pipeline mode, user can choose to\n- use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``,\n- for example::\n-\n- -a 80:00.0,pipeline-mode-support=1\n-\n - ``Default MAC Disable`` (default ``0``)\n \n Disable the default MAC make the device drop all packets by default,\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 4bad39c2c1..036b068c22 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -27,7 +27,6 @@\n \n /* devargs */\n #define ICE_SAFE_MODE_SUPPORT_ARG \"safe-mode-support\"\n-#define ICE_PIPELINE_MODE_SUPPORT_ARG \"pipeline-mode-support\"\n #define ICE_DEFAULT_MAC_DISABLE \"default-mac-disable\"\n #define ICE_PROTO_XTR_ARG \"proto_xtr\"\n #define ICE_FIELD_OFFS_ARG\t\t \"field_offs\"\n@@ -43,7 +42,6 @@ int ice_timestamp_dynfield_offset = -1;\n \n static const char * const ice_valid_args[] = {\n \tICE_SAFE_MODE_SUPPORT_ARG,\n-\tICE_PIPELINE_MODE_SUPPORT_ARG,\n \tICE_PROTO_XTR_ARG,\n \tICE_FIELD_OFFS_ARG,\n \tICE_FIELD_NAME_ARG,\n@@ -2103,11 +2101,6 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)\n \tif (ret)\n \t\tgoto bail;\n \n-\tret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,\n-\t\t\t\t &parse_bool, &ad->devargs.pipe_mode_support);\n-\tif (ret)\n-\t\tgoto bail;\n-\n \tret = rte_kvargs_process(kvlist, ICE_DEFAULT_MAC_DISABLE,\n \t\t\t\t&parse_bool, &ad->devargs.default_mac_disable);\n \tif (ret)\n@@ -6549,7 +6542,6 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ice,\n \t\t\t ICE_HW_DEBUG_MASK_ARG \"=0xXXX\"\n \t\t\t ICE_PROTO_XTR_ARG \"=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>\"\n \t\t\t ICE_SAFE_MODE_SUPPORT_ARG \"=<0|1>\"\n-\t\t\t ICE_PIPELINE_MODE_SUPPORT_ARG \"=<0|1>\"\n \t\t\t ICE_DEFAULT_MAC_DISABLE \"=<0|1>\"\n \t\t\t ICE_RX_LOW_LATENCY_ARG \"=<0|1>\");\n \ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 9789cb8525..1f88becd19 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -542,7 +542,6 @@ struct ice_pf {\n \tstruct ice_flow_list flow_list;\n \trte_spinlock_t flow_ops_lock;\n \tstruct ice_parser_list rss_parser_list;\n-\tstruct ice_parser_list perm_parser_list;\n \tstruct ice_parser_list dist_parser_list;\n \tbool init_link_up;\n \tuint64_t old_rx_bytes;\n@@ -563,7 +562,6 @@ struct ice_devargs {\n \tint rx_low_latency;\n \tint safe_mode_support;\n \tuint8_t proto_xtr_dflt;\n-\tint pipe_mode_support;\n \tuint8_t default_mac_disable;\n \tuint8_t proto_xtr[ICE_MAX_QUEUE_NUM];\n \tuint8_t pin_idx;\ndiff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c\nindex e8842bc242..e9ee5a57d6 100644\n--- a/drivers/net/ice/ice_fdir_filter.c\n+++ b/drivers/net/ice/ice_fdir_filter.c\n@@ -2467,7 +2467,7 @@ ice_fdir_parse(struct ice_adapter *ad,\n \titem = ice_search_pattern_match_item(ad, pattern, array, array_len,\n \t\t\t\t\t error);\n \n-\tif (!ad->devargs.pipe_mode_support && priority >= 1)\n+\tif (priority >= 1)\n \t\treturn -rte_errno;\n \n \tif (!item)\ndiff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c\nindex 91bf1d6fcb..6695457bbd 100644\n--- a/drivers/net/ice/ice_generic_flow.c\n+++ b/drivers/net/ice/ice_generic_flow.c\n@@ -18,16 +18,6 @@\n #include \"ice_ethdev.h\"\n #include \"ice_generic_flow.h\"\n \n-/**\n- * Non-pipeline mode, fdir and switch both used as distributor,\n- * fdir used first, switch used as fdir's backup.\n- */\n-#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY 0\n-/*Pipeline mode, switch used at permission stage*/\n-#define ICE_FLOW_CLASSIFY_STAGE_PERMISSION 1\n-/*Pipeline mode, fdir used at distributor stage*/\n-#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR 2\n-\n #define ICE_FLOW_ENGINE_DISABLED(mask, type) ((mask) & BIT(type))\n \n static struct ice_engine_list engine_list =\n@@ -1829,7 +1819,6 @@ ice_flow_init(struct ice_adapter *ad)\n \n \tTAILQ_INIT(&pf->flow_list);\n \tTAILQ_INIT(&pf->rss_parser_list);\n-\tTAILQ_INIT(&pf->perm_parser_list);\n \tTAILQ_INIT(&pf->dist_parser_list);\n \trte_spinlock_init(&pf->flow_ops_lock);\n \n@@ -1898,11 +1887,6 @@ ice_flow_uninit(struct ice_adapter *ad)\n \t\trte_free(p_parser);\n \t}\n \n-\twhile ((p_parser = TAILQ_FIRST(&pf->perm_parser_list))) {\n-\t\tTAILQ_REMOVE(&pf->perm_parser_list, p_parser, node);\n-\t\trte_free(p_parser);\n-\t}\n-\n \twhile ((p_parser = TAILQ_FIRST(&pf->dist_parser_list))) {\n \t\tTAILQ_REMOVE(&pf->dist_parser_list, p_parser, node);\n \t\trte_free(p_parser);\n@@ -1925,9 +1909,6 @@ ice_get_parser_list(struct ice_flow_parser *parser,\n \tcase ICE_FLOW_STAGE_RSS:\n \t\tlist = &pf->rss_parser_list;\n \t\tbreak;\n-\tcase ICE_FLOW_STAGE_PERMISSION:\n-\t\tlist = &pf->perm_parser_list;\n-\t\tbreak;\n \tcase ICE_FLOW_STAGE_DISTRIBUTOR:\n \t\tlist = &pf->dist_parser_list;\n \t\tbreak;\n@@ -1958,38 +1939,34 @@ ice_register_parser(struct ice_flow_parser *parser,\n \tif (list == NULL)\n \t\treturn -EINVAL;\n \n-\tif (ad->devargs.pipe_mode_support) {\n-\t\tTAILQ_INSERT_TAIL(list, parser_node, node);\n-\t} else {\n-\t\tif (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) {\n-\t\t\tRTE_TAILQ_FOREACH_SAFE(existing_node, list,\n-\t\t\t\t\t node, temp) {\n-\t\t\t\tif (existing_node->parser->engine->type ==\n-\t\t\t\t ICE_FLOW_ENGINE_ACL) {\n-\t\t\t\t\tTAILQ_INSERT_AFTER(list, existing_node,\n-\t\t\t\t\t\t\t parser_node, node);\n-\t\t\t\t\tgoto DONE;\n-\t\t\t\t}\n+\tif (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) {\n+\t\tRTE_TAILQ_FOREACH_SAFE(existing_node, list,\n+\t\t\t\t node, temp) {\n+\t\t\tif (existing_node->parser->engine->type ==\n+\t\t\t ICE_FLOW_ENGINE_ACL) {\n+\t\t\t\tTAILQ_INSERT_AFTER(list, existing_node,\n+\t\t\t\t\t\t parser_node, node);\n+\t\t\t\tgoto DONE;\n \t\t\t}\n-\t\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n-\t\t} else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) {\n-\t\t\tRTE_TAILQ_FOREACH_SAFE(existing_node, list,\n-\t\t\t\t\t node, temp) {\n-\t\t\t\tif (existing_node->parser->engine->type ==\n-\t\t\t\t ICE_FLOW_ENGINE_SWITCH) {\n-\t\t\t\t\tTAILQ_INSERT_AFTER(list, existing_node,\n-\t\t\t\t\t\t\t parser_node, node);\n-\t\t\t\t\tgoto DONE;\n-\t\t\t\t}\n+\t\t}\n+\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n+\t} else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) {\n+\t\tRTE_TAILQ_FOREACH_SAFE(existing_node, list,\n+\t\t\t\t node, temp) {\n+\t\t\tif (existing_node->parser->engine->type ==\n+\t\t\t ICE_FLOW_ENGINE_SWITCH) {\n+\t\t\t\tTAILQ_INSERT_AFTER(list, existing_node,\n+\t\t\t\t\t\t parser_node, node);\n+\t\t\t\tgoto DONE;\n \t\t\t}\n-\t\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n-\t\t} else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) {\n-\t\t\tTAILQ_INSERT_TAIL(list, parser_node, node);\n-\t\t} else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) {\n-\t\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n-\t\t} else {\n-\t\t\treturn -EINVAL;\n \t\t}\n+\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n+\t} else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) {\n+\t\tTAILQ_INSERT_TAIL(list, parser_node, node);\n+\t} else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) {\n+\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n+\t} else {\n+\t\treturn -EINVAL;\n \t}\n DONE:\n \treturn 0;\n@@ -2016,10 +1993,8 @@ ice_unregister_parser(struct ice_flow_parser *parser,\n }\n \n static int\n-ice_flow_valid_attr(struct ice_adapter *ad,\n-\t\tconst struct rte_flow_attr *attr,\n-\t\tint *ice_pipeline_stage,\n-\t\tstruct rte_flow_error *error)\n+ice_flow_valid_attr(const struct rte_flow_attr *attr,\n+\t\t struct rte_flow_error *error)\n {\n \t/* Must be input direction */\n \tif (!attr->ingress) {\n@@ -2045,23 +2020,11 @@ ice_flow_valid_attr(struct ice_adapter *ad,\n \t\treturn -rte_errno;\n \t}\n \n-\t/* Check pipeline mode support to set classification stage */\n-\tif (ad->devargs.pipe_mode_support) {\n-\t\tif (attr->priority == 0)\n-\t\t\t*ice_pipeline_stage =\n-\t\t\t\tICE_FLOW_CLASSIFY_STAGE_PERMISSION;\n-\t\telse\n-\t\t\t*ice_pipeline_stage =\n-\t\t\t\tICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR;\n-\t} else {\n-\t\t*ice_pipeline_stage =\n-\t\t\tICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY;\n-\t\tif (attr->priority > 1) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,\n-\t\t\t\t\tattr, \"Only support priority 0 and 1.\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n+\tif (attr->priority > 1) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,\n+\t\t\t\t attr, \"Only support priority 0 and 1.\");\n+\t\treturn -rte_errno;\n \t}\n \n \t/* Not supported */\n@@ -2407,7 +2370,6 @@ ice_flow_process_filter(struct rte_eth_dev *dev,\n \tstruct ice_adapter *ad =\n \t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tint ice_pipeline_stage = 0;\n \n \tif (!pattern) {\n \t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,\n@@ -2429,7 +2391,7 @@ ice_flow_process_filter(struct rte_eth_dev *dev,\n \t\treturn -rte_errno;\n \t}\n \n-\tret = ice_flow_valid_attr(ad, attr, &ice_pipeline_stage, error);\n+\tret = ice_flow_valid_attr(attr, error);\n \tif (ret)\n \t\treturn ret;\n \n@@ -2438,20 +2400,8 @@ ice_flow_process_filter(struct rte_eth_dev *dev,\n \tif (*engine != NULL)\n \t\treturn 0;\n \n-\tswitch (ice_pipeline_stage) {\n-\tcase ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY:\n-\tcase ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR:\n-\t\t*engine = ice_parse_engine(ad, flow, &pf->dist_parser_list,\n-\t\t\t\tattr->priority, pattern, actions, error);\n-\t\tbreak;\n-\tcase ICE_FLOW_CLASSIFY_STAGE_PERMISSION:\n-\t\t*engine = ice_parse_engine(ad, flow, &pf->perm_parser_list,\n-\t\t\t\tattr->priority, pattern, actions, error);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n+\t*engine = ice_parse_engine(ad, flow, &pf->dist_parser_list,\n+\t\t\t\t attr->priority, pattern, actions, error);\n \tif (*engine == NULL)\n \t\treturn -EINVAL;\n \ndiff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h\nindex 11f51a5c15..471f255bd6 100644\n--- a/drivers/net/ice/ice_generic_flow.h\n+++ b/drivers/net/ice/ice_generic_flow.h\n@@ -418,15 +418,13 @@ enum ice_flow_engine_type {\n };\n \n /**\n- * classification stages.\n- * for non-pipeline mode, we have two classification stages: Distributor/RSS\n- * for pipeline-mode we have three classification stages:\n+ * Classification stages.\n+ * We have two classification stages: Distributor/RSS\n * Permission/Distributor/RSS\n */\n enum ice_flow_classification_stage {\n \tICE_FLOW_STAGE_NONE = 0,\n \tICE_FLOW_STAGE_RSS,\n-\tICE_FLOW_STAGE_PERMISSION,\n \tICE_FLOW_STAGE_DISTRIBUTOR,\n \tICE_FLOW_STAGE_MAX,\n };\ndiff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 110d8895fe..88d599068f 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -202,7 +202,6 @@ struct ice_switch_filter_conf {\n };\n \n static struct ice_flow_parser ice_switch_dist_parser;\n-static struct ice_flow_parser ice_switch_perm_parser;\n \n static struct\n ice_pattern_match_item ice_switch_pattern_dist_list[] = {\n@@ -288,90 +287,6 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {\n \t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n };\n \n-static struct\n-ice_pattern_match_item ice_switch_pattern_perm_list[] = {\n-\t{pattern_any,\t\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_ethertype,\t\t\t\tICE_SW_INSET_ETHER,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_ethertype_vlan,\t\t\tICE_SW_INSET_MAC_VLAN,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_ethertype_qinq,\t\t\tICE_SW_INSET_MAC_QINQ,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_arp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4,\t\t\t\tICE_SW_INSET_MAC_IPV4,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp,\t\t\t\tICE_SW_INSET_MAC_IPV4_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV4_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6,\t\t\t\tICE_SW_INSET_MAC_IPV6,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp,\t\t\t\tICE_SW_INSET_MAC_IPV6_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV6_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp,\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp,\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_udp,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_tcp,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes,\t\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_esp,\t\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_esp,\t\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_ah,\t\t\t\tICE_SW_INSET_MAC_IPV4_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_ah,\t\t\t\tICE_SW_INSET_MAC_IPV6_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_ah,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV4_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV6_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv4,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_QINQ_IPV4_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv4_udp,\t\t\tICE_SW_INSET_MAC_QINQ_IPV4_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv6,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_QINQ_IPV6_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv6_udp,\t\t\tICE_SW_INSET_MAC_QINQ_IPV6_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n-};\n-\n static int\n ice_switch_create(struct ice_adapter *ad,\n \t\tstruct rte_flow *flow,\n@@ -2139,33 +2054,13 @@ ice_switch_redirect(struct ice_adapter *ad,\n static int\n ice_switch_init(struct ice_adapter *ad)\n {\n-\tint ret = 0;\n-\tstruct ice_flow_parser *dist_parser;\n-\tstruct ice_flow_parser *perm_parser;\n-\n-\tif (ad->devargs.pipe_mode_support) {\n-\t\tperm_parser = &ice_switch_perm_parser;\n-\t\tret = ice_register_parser(perm_parser, ad);\n-\t} else {\n-\t\tdist_parser = &ice_switch_dist_parser;\n-\t\tret = ice_register_parser(dist_parser, ad);\n-\t}\n-\treturn ret;\n+\treturn ice_register_parser(&ice_switch_dist_parser, ad);\n }\n \n static void\n ice_switch_uninit(struct ice_adapter *ad)\n {\n-\tstruct ice_flow_parser *dist_parser;\n-\tstruct ice_flow_parser *perm_parser;\n-\n-\tif (ad->devargs.pipe_mode_support) {\n-\t\tperm_parser = &ice_switch_perm_parser;\n-\t\tice_unregister_parser(perm_parser, ad);\n-\t} else {\n-\t\tdist_parser = &ice_switch_dist_parser;\n-\t\tice_unregister_parser(dist_parser, ad);\n-\t}\n+\tice_unregister_parser(&ice_switch_dist_parser, ad);\n }\n \n static struct\n@@ -2189,15 +2084,6 @@ ice_flow_parser ice_switch_dist_parser = {\n \t.stage = ICE_FLOW_STAGE_DISTRIBUTOR,\n };\n \n-static struct\n-ice_flow_parser ice_switch_perm_parser = {\n-\t.engine = &ice_switch_engine,\n-\t.array = ice_switch_pattern_perm_list,\n-\t.array_len = RTE_DIM(ice_switch_pattern_perm_list),\n-\t.parse_pattern_action = ice_switch_parse_pattern_action,\n-\t.stage = ICE_FLOW_STAGE_PERMISSION,\n-};\n-\n RTE_INIT(ice_sw_engine_init)\n {\n \tstruct ice_flow_engine *engine = &ice_switch_engine;\n", "prefixes": [ "v4", "1/5" ] }