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GET /api/patches/131800/?format=api
{ "id": 131800, "url": "http://patches.dpdk.org/api/patches/131800/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230822010226.17783-7-yuying.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230822010226.17783-7-yuying.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230822010226.17783-7-yuying.zhang@intel.com", "date": "2023-08-22T01:02:24", "name": "[v6,6/8] net/cpfl: add fxp rule module", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "941bd12971e4c65cca25add8001655bedd8c6a54", "submitter": { "id": 1844, "url": "http://patches.dpdk.org/api/people/1844/?format=api", "name": "Zhang, Yuying", "email": "yuying.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230822010226.17783-7-yuying.zhang@intel.com/mbox/", "series": [ { "id": 29591, "url": "http://patches.dpdk.org/api/series/29591/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29591", "date": "2023-08-22T01:02:18", "name": "add rte flow support for cpfl", "version": 6, "mbox": "http://patches.dpdk.org/series/29591/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131800/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/131800/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 78E9942608;\n\tThu, 21 Sep 2023 18:59:35 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 54C8A40E4A;\n\tThu, 21 Sep 2023 18:59:16 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 4548F40DF8\n for <dev@dpdk.org>; Thu, 21 Sep 2023 18:59:12 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2023 09:59:10 -0700", "from dpdk-pengyuan-mev.sh.intel.com ([10.67.119.128])\n by fmsmga004.fm.intel.com with ESMTP; 21 Sep 2023 09:59:05 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695315552; x=1726851552;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=5MrIbFIaDyu0R4GHKNSzQxaKMWE6b5NfVAjAjCbTre8=;\n b=F+rUpxHFL95tcXCV1Q/53HucFwEQ1Bl/YNID6ndDx5skiAVjfm4VQ762\n jtYO8OCru9q/4EJwh+DS9GPPqmrcvDMNOqY4L9XLkCeVBygLiOf8A8No5\n FLHh74PxTrqP7J3zP+ptD80fD/WW+/OmAVWPnz9THwZCzTooPX1V57jLz\n jOxl9TZoczNZ1CBZa9KC0jisTm2fAxoOPgvYEc6XPDxqy4tLZ70hKitb5\n m7bD84w2KMeJEoNVjIF8GphoZEN8yGKblApRXsZx7J+mjwBg7lGZ6fad0\n 8C1M/iMOxF5KUcOcwV4Gj5kNLHjXPqWdS1yCjD8aHdmbJjV6VCn/BMmuW Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10840\"; a=\"379468321\"", "E=Sophos;i=\"6.03,165,1694761200\"; d=\"scan'208\";a=\"379468321\"", "E=McAfee;i=\"6600,9927,10840\"; a=\"817472301\"", "E=Sophos;i=\"6.03,165,1694761200\"; d=\"scan'208\";a=\"817472301\"" ], "X-ExtLoop1": "1", "From": "\"Zhang, Yuying\" <yuying.zhang@intel.com>", "To": "yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com,\n jingjing.wu@intel.com, beilei.xing@intel.com", "Subject": "[PATCH v6 6/8] net/cpfl: add fxp rule module", "Date": "Tue, 22 Aug 2023 01:02:24 +0000", "Message-Id": "<20230822010226.17783-7-yuying.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230822010226.17783-1-yuying.zhang@intel.com>", "References": "<20230915100047.90153-1-yuying.zhang@intel.com>\n <20230822010226.17783-1-yuying.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yuying Zhang <yuying.zhang@intel.com>\n\nAdded low level fxp module for rule packing / creation / destroying.\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 31 ++++\n drivers/net/cpfl/cpfl_ethdev.h | 6 +\n drivers/net/cpfl/cpfl_fxp_rule.c | 296 +++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_fxp_rule.h | 68 +++++++\n drivers/net/cpfl/meson.build | 1 +\n 5 files changed, 402 insertions(+)\n create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c\n create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex a2bc6784d0..da78e79652 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -16,6 +16,7 @@\n #include <ethdev_private.h>\n #include \"cpfl_rxtx.h\"\n #include \"cpfl_flow.h\"\n+#include \"cpfl_rules.h\"\n \n #define CPFL_REPRESENTOR\t\"representor\"\n #define CPFL_TX_SINGLE_Q\t\"tx_single\"\n@@ -1127,6 +1128,7 @@ cpfl_dev_close(struct rte_eth_dev *dev)\n \tadapter->cur_vport_nb--;\n \tdev->data->dev_private = NULL;\n \tadapter->vports[vport->sw_idx] = NULL;\n+\tidpf_free_dma_mem(NULL, &cpfl_vport->itf.flow_dma);\n \trte_free(cpfl_vport);\n \n \treturn 0;\n@@ -2466,6 +2468,26 @@ cpfl_p2p_queue_info_init(struct cpfl_vport *cpfl_vport,\n \treturn 0;\n }\n \n+int\n+cpfl_alloc_dma_mem_batch(struct idpf_dma_mem *orig_dma, struct idpf_dma_mem *dma, uint32_t size,\n+\t\t\t int batch_size)\n+{\n+\tint i;\n+\n+\tif (!idpf_alloc_dma_mem(NULL, orig_dma, size * (1 + batch_size))) {\n+\t\tPMD_INIT_LOG(ERR, \"Could not alloc dma memory\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (i = 0; i < batch_size; i++) {\n+\t\tdma[i].va = (void *)((uint64_t)orig_dma->va + size * (i + 1));\n+\t\tdma[i].pa = orig_dma->pa + size * (i + 1);\n+\t\tdma[i].size = size;\n+\t\tdma[i].zone = NULL;\n+\t}\n+\treturn 0;\n+}\n+\n static int\n cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n {\n@@ -2515,6 +2537,15 @@ cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n \trte_ether_addr_copy((struct rte_ether_addr *)vport->default_mac_addr,\n \t\t\t &dev->data->mac_addrs[0]);\n \n+\tmemset(cpfl_vport->itf.dma, 0, sizeof(cpfl_vport->itf.dma));\n+\tmemset(cpfl_vport->itf.msg, 0, sizeof(cpfl_vport->itf.msg));\n+\tret = cpfl_alloc_dma_mem_batch(&cpfl_vport->itf.flow_dma,\n+\t\t\t\t cpfl_vport->itf.dma,\n+\t\t\t\t sizeof(union cpfl_rule_cfg_pkt_record),\n+\t\t\t\t CPFL_FLOW_BATCH_SIZE);\n+\tif (ret < 0)\n+\t\tgoto err_mac_addrs;\n+\n \tif (!adapter->base.is_rx_singleq && !adapter->base.is_tx_singleq) {\n \t\tmemset(&p2p_queue_grps_info, 0, sizeof(p2p_queue_grps_info));\n \t\tret = cpfl_p2p_q_grps_add(vport, &p2p_queue_grps_info, p2p_q_vc_out_info);\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex 7f83d170d7..8eeeac9910 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -147,10 +147,14 @@ enum cpfl_itf_type {\n \n TAILQ_HEAD(cpfl_flow_list, rte_flow);\n \n+#define CPFL_FLOW_BATCH_SIZE 490\n struct cpfl_itf {\n \tenum cpfl_itf_type type;\n \tstruct cpfl_adapter_ext *adapter;\n \tstruct cpfl_flow_list flow_list;\n+\tstruct idpf_dma_mem flow_dma;\n+\tstruct idpf_dma_mem dma[CPFL_FLOW_BATCH_SIZE];\n+\tstruct idpf_ctlq_msg msg[CPFL_FLOW_BATCH_SIZE];\n \tvoid *data;\n };\n \n@@ -240,6 +244,8 @@ int cpfl_cc_vport_info_get(struct cpfl_adapter_ext *adapter,\n int cpfl_vc_create_ctrl_vport(struct cpfl_adapter_ext *adapter);\n int cpfl_config_ctlq_rx(struct cpfl_adapter_ext *adapter);\n int cpfl_config_ctlq_tx(struct cpfl_adapter_ext *adapter);\n+int cpfl_alloc_dma_mem_batch(struct idpf_dma_mem *orig_dma, struct idpf_dma_mem *dma,\n+\t\t\t uint32_t size, int batch_size);\n \n #define CPFL_DEV_TO_PCI(eth_dev)\t\t\\\n \tRTE_DEV_TO_PCI((eth_dev)->device)\ndiff --git a/drivers/net/cpfl/cpfl_fxp_rule.c b/drivers/net/cpfl/cpfl_fxp_rule.c\nnew file mode 100644\nindex 0000000000..50fac55432\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_fxp_rule.c\n@@ -0,0 +1,296 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+#include \"cpfl_ethdev.h\"\n+\n+#include \"cpfl_fxp_rule.h\"\n+#include \"cpfl_logs.h\"\n+\n+#define CTLQ_SEND_RETRIES 100\n+#define CTLQ_RECEIVE_RETRIES 100\n+\n+int\n+cpfl_send_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg,\n+\t\t struct idpf_ctlq_msg q_msg[])\n+{\n+\tstruct idpf_ctlq_msg **msg_ptr_list;\n+\tu16 clean_count = 0;\n+\tint num_cleaned = 0;\n+\tint retries = 0;\n+\tint ret = 0;\n+\n+\tmsg_ptr_list = calloc(num_q_msg, sizeof(struct idpf_ctlq_msg *));\n+\tif (!msg_ptr_list) {\n+\t\tPMD_INIT_LOG(ERR, \"no memory for cleaning ctlq\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tret = cpfl_vport_ctlq_send(hw, cq, num_q_msg, q_msg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"cpfl_vport_ctlq_send() failed with error: 0x%4x\", ret);\n+\t\tgoto send_err;\n+\t}\n+\n+\twhile (retries <= CTLQ_SEND_RETRIES) {\n+\t\tclean_count = num_q_msg - num_cleaned;\n+\t\tret = cpfl_vport_ctlq_clean_sq(cq, &clean_count,\n+\t\t\t\t\t &msg_ptr_list[num_cleaned]);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"clean ctlq failed: 0x%4x\", ret);\n+\t\t\tgoto send_err;\n+\t\t}\n+\n+\t\tnum_cleaned += clean_count;\n+\t\tretries++;\n+\t\tif (num_cleaned >= num_q_msg)\n+\t\t\tbreak;\n+\t\trte_delay_us_sleep(10);\n+\t}\n+\n+\tif (retries > CTLQ_SEND_RETRIES) {\n+\t\tPMD_INIT_LOG(ERR, \"timed out while polling for completions\");\n+\t\tret = -1;\n+\t\tgoto send_err;\n+\t}\n+\n+send_err:\n+\tif (msg_ptr_list)\n+\t\tfree(msg_ptr_list);\n+err:\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_process_rx_ctlq_msg(u16 num_q_msg, struct idpf_ctlq_msg *q_msg)\n+{\n+\tu16 i;\n+\n+\tif (!num_q_msg || !q_msg)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < num_q_msg; i++) {\n+\t\tif (q_msg[i].status == CPFL_CFG_PKT_ERR_OK) {\n+\t\t\tcontinue;\n+\t\t} else if (q_msg[i].status == CPFL_CFG_PKT_ERR_EEXIST &&\n+\t\t\t q_msg[i].opcode == cpfl_ctlq_sem_add_rule) {\n+\t\t\tPMD_INIT_LOG(ERR, \"The rule has confliction with already existed one\");\n+\t\t\treturn -EINVAL;\n+\t\t} else if (q_msg[i].status == CPFL_CFG_PKT_ERR_ENOTFND &&\n+\t\t\t q_msg[i].opcode == cpfl_ctlq_sem_del_rule) {\n+\t\t\tPMD_INIT_LOG(ERR, \"The rule has already deleted\");\n+\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(ERR, \"Invalid rule\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+cpfl_receive_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg,\n+\t\t struct idpf_ctlq_msg q_msg[])\n+{\n+\tint retries = 0;\n+\tstruct idpf_dma_mem *dma;\n+\tu16 i;\n+\tuint16_t buff_cnt;\n+\tint ret = 0, handle_rule = 0;\n+\n+\tretries = 0;\n+\twhile (retries <= CTLQ_RECEIVE_RETRIES) {\n+\t\trte_delay_us_sleep(10);\n+\t\tret = cpfl_vport_ctlq_recv(cq, &num_q_msg, &q_msg[0]);\n+\n+\t\tif (ret && ret != CPFL_ERR_CTLQ_NO_WORK &&\n+\t\t ret != CPFL_ERR_CTLQ_ERROR) {\n+\t\t\tPMD_INIT_LOG(ERR, \"failed to recv ctrlq msg. err: 0x%4x\\n\", ret);\n+\t\t\tretries++;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ret == CPFL_ERR_CTLQ_NO_WORK) {\n+\t\t\tretries++;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ret == CPFL_ERR_CTLQ_EMPTY)\n+\t\t\tbreak;\n+\n+\t\tret = cpfl_process_rx_ctlq_msg(num_q_msg, q_msg);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"failed to process rx_ctrlq msg\");\n+\t\t\thandle_rule = ret;\n+\t\t}\n+\n+\t\tfor (i = 0; i < num_q_msg; i++) {\n+\t\t\tif (q_msg[i].data_len > 0)\n+\t\t\t\tdma = q_msg[i].ctx.indirect.payload;\n+\t\t\telse\n+\t\t\t\tdma = NULL;\n+\n+\t\t\tbuff_cnt = dma ? 1 : 0;\n+\t\t\tret = cpfl_vport_ctlq_post_rx_buffs(hw, cq, &buff_cnt, &dma);\n+\t\t\tif (ret)\n+\t\t\t\tPMD_INIT_LOG(WARNING, \"could not posted recv bufs\\n\");\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tif (retries > CTLQ_RECEIVE_RETRIES) {\n+\t\tPMD_INIT_LOG(ERR, \"timed out while polling for receive response\");\n+\t\tret = -1;\n+\t}\n+\n+\treturn ret + handle_rule;\n+}\n+\n+static int\n+cpfl_mod_rule_pack(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,\n+\t\t struct idpf_ctlq_msg *msg)\n+{\n+\tstruct cpfl_mod_rule_info *minfo = &rinfo->mod;\n+\tunion cpfl_rule_cfg_pkt_record *blob = NULL;\n+\tstruct cpfl_rule_cfg_data cfg = {0};\n+\n+\t/* prepare rule blob */\n+\tif (!dma->va) {\n+\t\tPMD_INIT_LOG(ERR, \"dma mem passed to %s is null\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\tblob = (union cpfl_rule_cfg_pkt_record *)dma->va;\n+\tmemset(blob, 0, sizeof(*blob));\n+\tmemset(&cfg, 0, sizeof(cfg));\n+\n+\t/* fill info for both query and add/update */\n+\tcpfl_fill_rule_mod_content(minfo->mod_obj_size,\n+\t\t\t\t minfo->pin_mod_content,\n+\t\t\t\t minfo->mod_index,\n+\t\t\t\t &cfg.ext.mod_content);\n+\n+\t/* only fill content for add/update */\n+\tmemcpy(blob->mod_blob, minfo->mod_content,\n+\t minfo->mod_content_byte_len);\n+\n+#define NO_HOST_NEEDED 0\n+\t/* pack message */\n+\tcpfl_fill_rule_cfg_data_common(cpfl_ctlq_mod_add_update_rule,\n+\t\t\t\t rinfo->cookie,\n+\t\t\t\t 0, /* vsi_id not used for mod */\n+\t\t\t\t rinfo->port_num,\n+\t\t\t\t NO_HOST_NEEDED,\n+\t\t\t\t 0, /* time_sel */\n+\t\t\t\t 0, /* time_sel_val */\n+\t\t\t\t 0, /* cache_wr_thru */\n+\t\t\t\t rinfo->resp_req,\n+\t\t\t\t (u16)sizeof(*blob),\n+\t\t\t\t (void *)dma,\n+\t\t\t\t &cfg.common);\n+\tcpfl_prep_rule_desc(&cfg, msg);\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_default_rule_pack(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,\n+\t\t struct idpf_ctlq_msg *msg, bool add)\n+{\n+\tunion cpfl_rule_cfg_pkt_record *blob = NULL;\n+\tenum cpfl_ctlq_rule_cfg_opc opc;\n+\tstruct cpfl_rule_cfg_data cfg;\n+\tuint16_t cfg_ctrl;\n+\n+\tif (!dma->va) {\n+\t\tPMD_INIT_LOG(ERR, \"dma mem passed to %s is null\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\tblob = (union cpfl_rule_cfg_pkt_record *)dma->va;\n+\tmemset(blob, 0, sizeof(*blob));\n+\tmemset(msg, 0, sizeof(*msg));\n+\n+\tif (rinfo->type == CPFL_RULE_TYPE_SEM) {\n+\t\tcfg_ctrl = CPFL_GET_MEV_SEM_RULE_CFG_CTRL(rinfo->sem.prof_id,\n+\t\t\t\t\t\t\t rinfo->sem.sub_prof_id,\n+\t\t\t\t\t\t\t rinfo->sem.pin_to_cache,\n+\t\t\t\t\t\t\t rinfo->sem.fixed_fetch);\n+\t\tcpfl_prep_sem_rule_blob(rinfo->sem.key, rinfo->sem.key_byte_len,\n+\t\t\t\t\trinfo->act_bytes, rinfo->act_byte_len,\n+\t\t\t\t\tcfg_ctrl, blob);\n+\t\topc = add ? cpfl_ctlq_sem_add_rule : cpfl_ctlq_sem_del_rule;\n+\t} else {\n+\t\tPMD_INIT_LOG(ERR, \"not support %d rule.\", rinfo->type);\n+\t\treturn -1;\n+\t}\n+\n+\tcpfl_fill_rule_cfg_data_common(opc,\n+\t\t\t\t rinfo->cookie,\n+\t\t\t\t rinfo->vsi,\n+\t\t\t\t rinfo->port_num,\n+\t\t\t\t rinfo->host_id,\n+\t\t\t\t 0, /* time_sel */\n+\t\t\t\t 0, /* time_sel_val */\n+\t\t\t\t 0, /* cache_wr_thru */\n+\t\t\t\t rinfo->resp_req,\n+\t\t\t\t sizeof(union cpfl_rule_cfg_pkt_record),\n+\t\t\t\t dma,\n+\t\t\t\t &cfg.common);\n+\tcpfl_prep_rule_desc(&cfg, msg);\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_rule_pack(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,\n+\t struct idpf_ctlq_msg *msg, bool add)\n+{\n+\tint ret = 0;\n+\n+\tif (rinfo->type == CPFL_RULE_TYPE_SEM) {\n+\t\tif (cpfl_default_rule_pack(rinfo, dma, msg, add) < 0)\n+\t\t\tret = -1;\n+\t} else if (rinfo->type == CPFL_RULE_TYPE_MOD) {\n+\t\tif (cpfl_mod_rule_pack(rinfo, dma, msg) < 0)\n+\t\t\tret = -1;\n+\t} else {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid type of rule\");\n+\t\tret = -1;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int\n+cpfl_rule_process(struct cpfl_itf *itf,\n+\t\t struct idpf_ctlq_info *tx_cq,\n+\t\t struct idpf_ctlq_info *rx_cq,\n+\t\t struct cpfl_rule_info *rinfo,\n+\t\t int rule_num,\n+\t\t bool add)\n+{\n+\tstruct idpf_hw *hw = &itf->adapter->base.hw;\n+\tint i;\n+\tint ret = 0;\n+\n+\tif (rule_num == 0)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < rule_num; i++) {\n+\t\tret = cpfl_rule_pack(&rinfo[i], &itf->dma[i], &itf->msg[i], add);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Could not pack rule\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\tret = cpfl_send_ctlq_msg(hw, tx_cq, rule_num, itf->msg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to send control message\");\n+\t\treturn ret;\n+\t}\n+\tret = cpfl_receive_ctlq_msg(hw, rx_cq, rule_num, itf->msg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to update rule\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/cpfl/cpfl_fxp_rule.h b/drivers/net/cpfl/cpfl_fxp_rule.h\nnew file mode 100644\nindex 0000000000..ed757b80b1\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_fxp_rule.h\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_FXP_RULE_H_\n+#define _CPFL_FXP_RULE_H_\n+\n+#include \"cpfl_rules.h\"\n+\n+#define CPFL_MAX_KEY_LEN 128\n+#define CPFL_MAX_RULE_ACTIONS 32\n+\n+struct cpfl_sem_rule_info {\n+\tuint16_t prof_id;\n+\tuint8_t sub_prof_id;\n+\tuint8_t key[CPFL_MAX_KEY_LEN];\n+\tuint8_t key_byte_len;\n+\tuint8_t pin_to_cache;\n+\tuint8_t fixed_fetch;\n+};\n+\n+#define CPFL_MAX_MOD_CONTENT_LEN 256\n+struct cpfl_mod_rule_info {\n+\tuint8_t mod_content[CPFL_MAX_MOD_CONTENT_LEN];\n+\tuint8_t mod_content_byte_len;\n+\tuint32_t mod_index;\n+\tuint8_t pin_mod_content;\n+\tuint8_t mod_obj_size;\n+};\n+\n+enum cpfl_rule_type {\n+\tCPFL_RULE_TYPE_NONE,\n+\tCPFL_RULE_TYPE_SEM,\n+\tCPFL_RULE_TYPE_MOD\n+};\n+\n+struct cpfl_rule_info {\n+\tenum cpfl_rule_type type;\n+\tuint64_t cookie;\n+\tuint8_t host_id;\n+\tuint8_t port_num;\n+\tuint8_t resp_req;\n+\t/* TODO: change this to be dynamically allocated/reallocated */\n+\tuint8_t act_bytes[CPFL_MAX_RULE_ACTIONS * sizeof(union cpfl_action_set)];\n+\tuint8_t act_byte_len;\n+\t/* vsi is used for lem and lpm rules */\n+\tuint16_t vsi;\n+\tuint8_t clear_mirror_1st_state;\n+\t/* mod related fields */\n+\tunion {\n+\t\tstruct cpfl_mod_rule_info mod;\n+\t\tstruct cpfl_sem_rule_info sem;\n+\t};\n+};\n+\n+extern struct cpfl_vport_ext *vport;\n+\n+int cpfl_rule_process(struct cpfl_itf *itf,\n+\t\t struct idpf_ctlq_info *tx_cq,\n+\t\t struct idpf_ctlq_info *rx_cq,\n+\t\t struct cpfl_rule_info *rinfo,\n+\t\t int rule_num,\n+\t\t bool add);\n+int cpfl_send_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg,\n+\t\t struct idpf_ctlq_msg q_msg[]);\n+int cpfl_receive_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg,\n+\t\t\t struct idpf_ctlq_msg q_msg[]);\n+#endif /*CPFL_FXP_RULE_H*/\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex e2b6621cea..6118a16329 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -45,6 +45,7 @@ if dpdk_conf.has('RTE_HAS_JANSSON')\n sources += files(\n \t 'cpfl_flow.c',\n 'cpfl_flow_parser.c',\n+\t 'cpfl_fxp_rule.c',\n )\n ext_deps += jansson_dep\n endif\n", "prefixes": [ "v6", "6/8" ] }