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GET /api/patches/131710/?format=api
{ "id": 131710, "url": "http://patches.dpdk.org/api/patches/131710/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230920101222.767408-2-rbhansali@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230920101222.767408-2-rbhansali@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230920101222.767408-2-rbhansali@marvell.com", "date": "2023-09-20T10:12:22", "name": "[2/2] net/cnxk: separate callback for Rx flush on CN10k", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c0d75b3bbc832f5a2e843e9eb9e77131c710dc1d", "submitter": { "id": 2436, "url": "http://patches.dpdk.org/api/people/2436/?format=api", "name": "Rahul Bhansali", "email": "rbhansali@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230920101222.767408-2-rbhansali@marvell.com/mbox/", "series": [ { "id": 29568, "url": "http://patches.dpdk.org/api/series/29568/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29568", "date": "2023-09-20T10:12:21", "name": "[1/2] common/cnxk: reserve last LMT line for control ops", "version": 1, "mbox": "http://patches.dpdk.org/series/29568/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131710/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/131710/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2275A425EF;\n\tWed, 20 Sep 2023 12:12:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 158F641151;\n\tWed, 20 Sep 2023 12:12:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A794C41143\n for <dev@dpdk.org>; Wed, 20 Sep 2023 12:12:38 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 38K9FbWa028048 for <dev@dpdk.org>; Wed, 20 Sep 2023 03:12:38 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3t7htathb1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 20 Sep 2023 03:12:37 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 20 Sep 2023 03:12:35 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 20 Sep 2023 03:12:35 -0700", "from localhost.localdomain (unknown [10.28.36.158])\n by maili.marvell.com (Postfix) with ESMTP id BC7D93F705A;\n Wed, 20 Sep 2023 03:12:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=1I168SWP+6ODE6aoCKSznSUwJDk+8VL9b4vMo/cUitA=;\n b=MRKcnudS1pE1x37a8fds+j7xyUZWaq4thh/OZ3seqmWYTjOqDeomf5ITDyUA+/yP2CZy\n zfh+AKBdpH9ftbwdiwz8cW3JEee44lfgD3iLtXsYsOhiDnUTtFLy3wnuaYVWERgdZUoJ\n JyWtwVnh/kVOQajSPvT60Swl2dZ/gGCGHlWBob6WBfwOL7lb5FZ0PriE9bbUjJDANTM5\n 0TcOg9vThzV/yy7o9qCRaFTyiyobUBPLK0955F54K1FspvQQCf2jfQHs5O5H+UN3IhvB\n KfFOAIb/ceLpUMQmHcbtSg2zCSVTWDsS3jsN5louaJyA4lSaBbJgnBgTCoUHFtk63Wla nw==", "From": "Rahul Bhansali <rbhansali@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>", "Subject": "[PATCH 2/2] net/cnxk: separate callback for Rx flush on CN10k", "Date": "Wed, 20 Sep 2023 15:42:22 +0530", "Message-ID": "<20230920101222.767408-2-rbhansali@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230920101222.767408-1-rbhansali@marvell.com>", "References": "<20230920101222.767408-1-rbhansali@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "Kp8AYbMczwbdOXT4aFpKqzoLCaaKOSer", "X-Proofpoint-GUID": "Kp8AYbMczwbdOXT4aFpKqzoLCaaKOSer", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26\n definitions=2023-09-20_05,2023-09-19_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In dev stop case, Rx packet flush callback uses LMT lines to bulk free\nof the meta buffers. If dev stop is called from non EAL core then LMT\naddress will not be valid.\nTo avoid this, A separate callback for Rx packets flush is added,\nwhich will use NPA aura free API on individual meta packets.\n\nSigned-off-by: Rahul Bhansali <rbhansali@marvell.com>\n---\n drivers/net/cnxk/cn10k_rx.h | 93 ++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn10k_rx_select.c | 10 +++-\n 2 files changed, 101 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex 41d11349fd..1d7c5215a7 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -1007,6 +1007,99 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \treturn nb_pkts;\n }\n \n+static __rte_always_inline uint16_t\n+cn10k_nix_flush_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n+\t\t\t const uint16_t flags)\n+{\n+\tstruct cn10k_eth_rxq *rxq = rx_queue;\n+\tconst uint64_t mbuf_init = rxq->mbuf_initializer;\n+\tconst void *lookup_mem = rxq->lookup_mem;\n+\tconst uint64_t data_off = rxq->data_off;\n+\tstruct rte_mempool *meta_pool = NULL;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tconst uintptr_t desc = rxq->desc;\n+\tuint64_t lbase = rxq->lmt_base;\n+\tuint16_t packets = 0, nb_pkts;\n+\tuint16_t lmt_id __rte_unused;\n+\tuint32_t head = rxq->head;\n+\tstruct nix_cqe_hdr_s *cq;\n+\tstruct rte_mbuf *mbuf;\n+\tuint64_t sa_base = 0;\n+\tuintptr_t cpth = 0;\n+\tuint8_t loff = 0;\n+\tuint64_t laddr;\n+\n+\tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\tsa_base = rxq->sa_base;\n+\t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n+\t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n+\t\tladdr = lbase;\n+\t\tladdr += 8;\n+\t\tif (flags & NIX_RX_REAS_F)\n+\t\t\tmeta_pool = (struct rte_mempool *)rxq->meta_pool;\n+\t}\n+\n+\twhile (packets < nb_pkts) {\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(desc + (CQE_SZ((head + 2) & qmask))));\n+\t\tcq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));\n+\n+\t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n+\n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n+\t\t/* Translate meta to mbuf */\n+\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n+\t\t\tconst uint64_t cq_w1 = *((const uint64_t *)cq + 1);\n+\t\t\tconst uint64_t cq_w5 = *((const uint64_t *)cq + 5);\n+\t\t\tstruct rte_mbuf *meta_buf = mbuf;\n+\n+\t\t\tcpth = ((uintptr_t)meta_buf + (uint16_t)data_off);\n+\n+\t\t\t/* Update mempool pointer for full mode pkt */\n+\t\t\tif ((flags & NIX_RX_REAS_F) && (cq_w1 & BIT(11)) &&\n+\t\t\t !((*(uint64_t *)cpth) & BIT(15)))\n+\t\t\t\tmeta_buf->pool = meta_pool;\n+\n+\t\t\tmbuf = nix_sec_meta_to_mbuf_sc(cq_w1, cq_w5, sa_base, laddr, &loff,\n+\t\t\t\t\t\t meta_buf, data_off, flags, mbuf_init);\n+\t\t\t/* Free Meta mbuf, not use LMT line for flush as this will be called\n+\t\t\t * from non-datapath i.e. dev_stop case.\n+\t\t\t */\n+\t\t\tif (loff) {\n+\t\t\t\troc_npa_aura_op_free(meta_buf->pool->pool_id, 0,\n+\t\t\t\t\t\t (uint64_t)meta_buf);\n+\t\t\t\tloff = 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\tcn10k_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,\n+\t\t\t\t cpth, sa_base, flags);\n+\t\tcn10k_nix_mbuf_to_tstamp(mbuf, rxq->tstamp,\n+\t\t\t\t\t(flags & NIX_RX_OFFLOAD_TSTAMP_F),\n+\t\t\t\t\t(uint64_t *)((uint8_t *)mbuf + data_off));\n+\t\trx_pkts[packets++] = mbuf;\n+\t\troc_prefetch_store_keep(mbuf);\n+\t\thead++;\n+\t\thead &= qmask;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= nb_pkts;\n+\n+\t/* Free all the CQs that we've processed */\n+\tplt_write64((wdata | nb_pkts), rxq->cq_door);\n+\n+\tif (flags & NIX_RX_OFFLOAD_SECURITY_F)\n+\t\trte_io_wmb();\n+\n+\treturn nb_pkts;\n+}\n+\n #if defined(RTE_ARCH_ARM64)\n \n static __rte_always_inline uint64_t\ndiff --git a/drivers/net/cnxk/cn10k_rx_select.c b/drivers/net/cnxk/cn10k_rx_select.c\nindex 1d44f2924e..6a5c34287e 100644\n--- a/drivers/net/cnxk/cn10k_rx_select.c\n+++ b/drivers/net/cnxk/cn10k_rx_select.c\n@@ -22,6 +22,13 @@ pick_rx_func(struct rte_eth_dev *eth_dev,\n \trte_atomic_thread_fence(__ATOMIC_RELEASE);\n }\n \n+static uint16_t __rte_noinline __rte_hot __rte_unused\n+cn10k_nix_flush_rx(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts)\n+{\n+\tconst uint16_t flags = NIX_RX_MULTI_SEG_F | NIX_RX_REAS_F | NIX_RX_OFFLOAD_SECURITY_F;\n+\treturn cn10k_nix_flush_recv_pkts(rx_queue, rx_pkts, pkts, flags);\n+}\n+\n void\n cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n {\n@@ -82,8 +89,7 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n \n \t/* Copy multi seg version with security for tear down sequence */\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\tdev->rx_pkt_burst_no_offload =\n-\t\t\tnix_eth_rx_burst_mseg_reas[NIX_RX_OFFLOAD_SECURITY_F];\n+\t\tdev->rx_pkt_burst_no_offload = cn10k_nix_flush_rx;\n \n \tif (dev->scalar_ena) {\n \t\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {\n", "prefixes": [ "2/2" ] }