Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/131616/?format=api
{ "id": 131616, "url": "http://patches.dpdk.org/api/patches/131616/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230919095440.45445-9-chaoyong.he@corigine.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230919095440.45445-9-chaoyong.he@corigine.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230919095440.45445-9-chaoyong.he@corigine.com", "date": "2023-09-19T09:54:22", "name": "[v5,08/26] net/nfp: standard the blank character", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "42a26b3fd538be0ae2409173e7c7e730af068692", "submitter": { "id": 2554, "url": "http://patches.dpdk.org/api/people/2554/?format=api", "name": "Chaoyong He", "email": "chaoyong.he@corigine.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230919095440.45445-9-chaoyong.he@corigine.com/mbox/", "series": [ { "id": 29547, "url": "http://patches.dpdk.org/api/series/29547/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29547", "date": "2023-09-19T09:54:14", "name": "refact the nfpcore module", "version": 5, "mbox": "http://patches.dpdk.org/series/29547/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131616/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/131616/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7AAD942600;\n\tTue, 19 Sep 2023 11:58:23 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C7F9E4113D;\n\tTue, 19 Sep 2023 11:56:15 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2120.outbound.protection.outlook.com [40.107.220.120])\n by mails.dpdk.org (Postfix) with ESMTP id E802E41141\n for <dev@dpdk.org>; Tue, 19 Sep 2023 11:56:13 +0200 (CEST)", "from SJ0PR13MB5545.namprd13.prod.outlook.com (2603:10b6:a03:424::5)\n by PH7PR13MB5868.namprd13.prod.outlook.com (2603:10b6:510:15a::6)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.26; Tue, 19 Sep\n 2023 09:55:34 +0000", "from SJ0PR13MB5545.namprd13.prod.outlook.com\n ([fe80::7a1c:2887:348a:84bd]) by SJ0PR13MB5545.namprd13.prod.outlook.com\n ([fe80::7a1c:2887:348a:84bd%6]) with mapi id 15.20.6792.026; Tue, 19 Sep 2023\n 09:55:34 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=cxbxa7gOIREntY9CTdEik2YbpFI1KO6GIzUZu8L7386CvlqLPMgxQCEpe2XGYlLj1uMOwK+kMce/pU00m9221fHOSWvkhnoV3rqp7NmL5dacRPzdBSzOui4jJbxTUKZV54JTM3UhEfMtXUeOzA2rLgesZmGrqBBlo97Tc0AR+lOJrLwHJW5ogqpt1vkVcZLOu29Ycp8XXANiboUGBVTahszH9LF7GiizBTlzXA4E+a6tB0CHnyZB0iVk/seiVkAyK5BegJa4CFkBYho41ulDxzBXvPPIhLHm4ZLduzo8F93VXFE9eruP7Vitau4uZ5pcu+ge6qktkjmlvbFZXZgIUg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=igIr1n0s0VuNP1NOjrAS48m2KT6xEZPa2r1+YXu42hs=;\n b=D5IRHgf22DvYB5inlu28wCGd6NrFG/pgVeAMnXEGALyAoqmk5SnuI40W2bi6++6uG3O7RgMVtYRzSAHZA7QtrlUv6Q8A3CJ8LeblyEUqFPnMsJ409UQsbaUqKlf2KZs9yn5mvLLUeGF+ZBYrIIh2ZsdZHYvlyyZyhFsay5tTmTTR2nLL2Cs8RQvYuthMi5I+37mcDA7PBJ3u4dIXomAyD+BBCUC4vHPLtzAbr54YOosN0EliVzRBH+D6/unpnyvbr4rk5wTjzIC5F3PxZKNHMvC76CdsLEYT6vRXfPA1e9uLxZyPXVhwkRs6kVh+Pt+aunOhpz0uEEIaCPHXrTRQgA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=corigine.com; dmarc=pass action=none header.from=corigine.com;\n dkim=pass header.d=corigine.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=corigine.onmicrosoft.com; s=selector2-corigine-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=igIr1n0s0VuNP1NOjrAS48m2KT6xEZPa2r1+YXu42hs=;\n b=RZ85W0gMyFCQUS0e+It3MWgWOlGj30CTZX4Ba2chHtMZ8+cylBrgfMQIxN7Eh5tutB38ZuAMf9Xj2hqTJGv4Rh2y2cdUPxFClkgm2935JDeExmXY0fRZLFJSVfWFp5lLlgQXHP1OFYyINDbrgrDuuOG+cHNxsu0PI5uNShvGWB8=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=corigine.com;", "From": "Chaoyong He <chaoyong.he@corigine.com>", "To": "dev@dpdk.org", "Cc": "oss-drivers@corigine.com,\n\tChaoyong He <chaoyong.he@corigine.com>", "Subject": "[PATCH v5 08/26] net/nfp: standard the blank character", "Date": "Tue, 19 Sep 2023 17:54:22 +0800", "Message-Id": "<20230919095440.45445-9-chaoyong.he@corigine.com>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230919095440.45445-1-chaoyong.he@corigine.com>", "References": "<20230918024612.1600536-1-chaoyong.he@corigine.com>\n <20230919095440.45445-1-chaoyong.he@corigine.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BY5PR04CA0014.namprd04.prod.outlook.com\n (2603:10b6:a03:1d0::24) To SJ0PR13MB5545.namprd13.prod.outlook.com\n (2603:10b6:a03:424::5)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ0PR13MB5545:EE_|PH7PR13MB5868:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ca22bf30-8dbc-48e3-4728-08dbb8f6913a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n J4wsS62PZD/T/+q1cnWu8HbfUe66i850zg+MvG5TCRaWnOMC2U1OQv9+uW+HAWML1ALCMPHIP9q51NuyOMSm7irrkIE4Yq/8fw+J9nauWiDiy4ohd4gztavpfqXjTY5ng2eIeg79GDHJwNOXnP/Yz3cdkUvkWAVfJSCNnU3E66TcemfNfyoDLO+rxvoaneoH1xSekC9YP6kK+isRb6hULwb0PRS/a83pycGOvrCToT8wUAHvyiW/CrSgXuo37g0LcAz87JCgW/1aITExuS+OUISQD1Gwbquv67MoQQCoTY1CfIRcJFJPhIIp/ZamX1R/DOINq+p+cgkNp+jE59RtSUPTB/mEa+mX8I8AfVp9ibcVnS5qP9W0aX45CMJS0CvGKpuDn59AxRZQr8xCkVGsCXeoGFghkA6rqvS+j7dOQ0QI3LTMbOH9xQCowUgA2rW5USi9q3JCExLRkBKIA3IawqlDcOAJZGek5+Yzezzh1c15h0mg5b60TqSKi88LKgU72M54Fs6caISLC7W1JgMv2lSXIlZk/StS/2PvKw+nzG0NXoMyU6d/CKJU3jV5wRogZIPN0ihLOiHxPI0aHOW0+LDLYBWzzfOJDi7oVsFXUP8uhz14Wkk5xaOjbAJL9B09cu3vyiulTbjh4ajPLKAcH76g+3MYqMwDFKQNgJiUK+4=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:SJ0PR13MB5545.namprd13.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230031)(136003)(39830400003)(366004)(346002)(376002)(396003)(1800799009)(186009)(451199024)(26005)(8936002)(2616005)(1076003)(8676002)(4326008)(107886003)(83380400001)(2906002)(30864003)(36756003)(44832011)(86362001)(52116002)(6506007)(6486002)(478600001)(5660300002)(6666004)(6916009)(316002)(6512007)(38100700002)(66946007)(66476007)(41300700001)(66556008)(38350700002);\n DIR:OUT; SFP:1102;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n ovgG7wzCZR8ED9etca7U+GDMquw4hiVMa9mVXPgAKRyFk2cgr1RC6QM3EnwMHc2EYi/saVspEOehEqErogxOZY6wsBolNksbnpcCv2tINDZTeqLvQmez5vf9NssQMXQjHrdeiB2dQdWG9WwmP0N88RjY3pJ7xpV9bvN/uxJhmlDT3ewF+KN+WyEMy1CHIcu3GX9c6aiejR9XqUnHuB4ky1qSpF02vmzPD7N03zg53UO6saaqvmQyBEiMldCfNa9TSAvD25UdxHeaUztWpmW3189tzHlO43qg9/AxePrtq2cCIYAoDfvkfeWVuWOooRRjy+ja0hC2iTarqpthdaTTaEAtCSO1EUg87zhQxyA6ciDeNJ9ydGMlr1pyN1jdsRfCj5MW8XTHkhdo0Z7NSf6Fj4z/mzYcyXrgps1wTF4vtGDkgy50flvl1/htT9I9ngcHzRpZ2A6AyxdVipt4DL5dCmCpbgnfJFD8yHEU/1/EuBwsI1P0c5oQfdMpzafoIfiARYB4mtyTatxOL/BCm8VLTKHiGWrdgU1OQR9Ahbg92zYk5ISzmEsOIzcCdvR/CjwI1oSql3MQEQKh3EWuOELehyKdETy2ngLKh46SG5yNLwSrFhMbTyGodSJyeNoMm7PO7nwXD1hjzv5yvN7LDqSEcHyLai4Vv0o7/UNKiGTZBCENZdhtNtg0h87wGkU/s5V0WTJmJkJkuHJSGB+gnCx/hv/AJ0Nyn+oyfxXURvW9o37BOR8GXwrnNCMDmL/QeSW2CR7Ai+pGf1FXCe0swgxW5+aWbeJgU6A4RABDgGKsGJ1PvnMs8HVwMXaFSMF8pjDx+i7TWF/8VIr1JnCwb6lH047abf8/TV6sGBqIO2ApRT/tLePLflLWMxHoSuV7/u1obxsmvDS8Mazvg2VZtikkcAX00eDTJ/UwK2fULyFvP0kn/P3uRS1P14hM68Ff58RK+SI5SqboIUn0LS21BMBlKIOZZcjQW1sxvcK8dE39rkh1LTIsXLAIbQ1bj9fHCKXyCU0fNHu9figILgp5GX233GLiFuNQXDR2TxWmYnNNUrowHlwZRjZJm0VqSFNKYFKW1O6VUK8xsgMCjCc3wBVLeHOl4A6MAiT6Yb8nXysQmAaRYqQu0L/96NkiFTwPe2Axcj9mm/d+D9I+YbyDvmIDi32BbZcX3s0c83B7ezrUnnvxf9aTib+uXz3AjMBnHZqfpJ3ZU6E6B6+sx18EQyrpMZt2Og0dynO1m3T/UzkU7OXRmlyQugSrCkWDpy4XU4LhqR7SuokKpoVhKfvWMgi9ProK1aFxZLhcAdxhLbqkltc4Xg5kTFT9EmOgLmkdwltb8jRRADryU1HQekGkSeUjC1IM8o8JHKcsVuwkkMPmcVijSkcqeaXEJ/NXamzWFFX5l7CmhDNuyfBtNnmgmmHUkcDrrDhXl1vZf9fFIUxYfHQLDvXFYhFwDns8Rchl5UZpnPjYWQ2CLp8H7fIEE3v9j5mypmiHmtq2If8hAQ98M6b2qm8fJBNuKTz6uCCjmRfIpPyoQVxt9XQU2ON7QFVXzGGMWRrs9Q1z/BHYlagY/kSnbABIuDDygF8UoW8XdX2svmzFT821/lUt9kf9milUEA==", "X-OriginatorOrg": "corigine.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ca22bf30-8dbc-48e3-4728-08dbb8f6913a", "X-MS-Exchange-CrossTenant-AuthSource": "SJ0PR13MB5545.namprd13.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Sep 2023 09:55:34.3867 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fe128f2c-073b-4c20-818e-7246a585940c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n dFcbmJF3tBr6v7WOKDYL7JUFvA9IPnT055cKVFaRO8tQiVq6p3lCRSrELHktSM4zpee6UlsEyKYsVgbZD69pdbcigMXI2K4rTG/M06ADvJw=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR13MB5868", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Use space character to align instead of TAB character.\nThere should one blank line to split the block of logic, no more no less.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\n---\n drivers/net/nfp/nfpcore/nfp6000/nfp6000.h | 4 +-\n drivers/net/nfp/nfpcore/nfp_cpp.h | 18 +--\n drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 17 ++-\n drivers/net/nfp/nfpcore/nfp_cppcore.c | 2 -\n drivers/net/nfp/nfpcore/nfp_crc.c | 2 +\n drivers/net/nfp/nfpcore/nfp_hwinfo.c | 2 +\n drivers/net/nfp/nfpcore/nfp_hwinfo.h | 45 ++++---\n drivers/net/nfp/nfpcore/nfp_mip.c | 9 +-\n drivers/net/nfp/nfpcore/nfp_mip.h | 1 +\n drivers/net/nfp/nfpcore/nfp_mutex.c | 17 +--\n drivers/net/nfp/nfpcore/nfp_nffw.c | 8 +-\n drivers/net/nfp/nfpcore/nfp_nsp.c | 3 +\n drivers/net/nfp/nfpcore/nfp_nsp.h | 105 ++++++++--------\n drivers/net/nfp/nfpcore/nfp_nsp_cmds.c | 1 +\n drivers/net/nfp/nfpcore/nfp_nsp_eth.c | 132 ++++++++++-----------\n drivers/net/nfp/nfpcore/nfp_resource.c | 18 +--\n drivers/net/nfp/nfpcore/nfp_rtsym.c | 16 +--\n drivers/net/nfp/nfpcore/nfp_rtsym.h | 1 +\n 18 files changed, 206 insertions(+), 195 deletions(-)", "diff": "diff --git a/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h b/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h\nindex 7750a0218e..efaa87c0e5 100644\n--- a/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h\n+++ b/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h\n@@ -15,8 +15,8 @@\n #define NFP_CPP_TARGET_PCIE 9\n #define NFP_CPP_TARGET_ARM 10\n #define NFP_CPP_TARGET_CRYPTO 12\n-#define NFP_CPP_TARGET_ISLAND_XPB 14\t/* Shared with CAP */\n-#define NFP_CPP_TARGET_ISLAND_CAP 14\t/* Shared with XPB */\n+#define NFP_CPP_TARGET_ISLAND_XPB 14 /* Shared with CAP */\n+#define NFP_CPP_TARGET_ISLAND_CAP 14 /* Shared with XPB */\n #define NFP_CPP_TARGET_CT_XPB 14\n #define NFP_CPP_TARGET_LOCAL_SCRATCH 15\n #define NFP_CPP_TARGET_CLS NFP_CPP_TARGET_LOCAL_SCRATCH\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cpp.h b/drivers/net/nfp/nfpcore/nfp_cpp.h\nindex 82189e9910..92cae2557a 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cpp.h\n+++ b/drivers/net/nfp/nfpcore/nfp_cpp.h\n@@ -80,16 +80,17 @@ struct nfp_cpp_operations {\n \t * Serialized\n \t */\n \tint (*area_acquire)(struct nfp_cpp_area *area);\n+\n \t/*\n \t * Release resources for a NFP CPP area\n \t * Serialized\n \t */\n \tvoid (*area_release)(struct nfp_cpp_area *area);\n+\n \t/*\n \t * Return a void IO pointer to a NFP CPP area\n \t * NOTE: This is _not_ serialized\n \t */\n-\n \tvoid *(*area_iomem)(struct nfp_cpp_area *area);\n \n \t/*\n@@ -280,7 +281,7 @@ void nfp_cpp_free(struct nfp_cpp *cpp);\n * @return\n * true if model is in the NFP6000 family, false otherwise.\n */\n-#define NFP_CPP_MODEL_IS_6000(model)\t\t \\\n+#define NFP_CPP_MODEL_IS_6000(model) \\\n \t\t((NFP_CPP_MODEL_CHIP_of(model) >= 0x3800) && \\\n \t\t(NFP_CPP_MODEL_CHIP_of(model) < 0x7000))\n \n@@ -290,11 +291,11 @@ uint32_t nfp_cpp_model(struct nfp_cpp *cpp);\n * NFP Interface types - logical interface for this CPP connection 4 bits are\n * reserved for interface type.\n */\n-#define NFP_CPP_INTERFACE_TYPE_INVALID\t\t0x0\n-#define NFP_CPP_INTERFACE_TYPE_PCI\t\t0x1\n-#define NFP_CPP_INTERFACE_TYPE_ARM\t\t0x2\n-#define NFP_CPP_INTERFACE_TYPE_RPC\t\t0x3\n-#define NFP_CPP_INTERFACE_TYPE_ILA\t\t0x4\n+#define NFP_CPP_INTERFACE_TYPE_INVALID 0x0\n+#define NFP_CPP_INTERFACE_TYPE_PCI 0x1\n+#define NFP_CPP_INTERFACE_TYPE_ARM 0x2\n+#define NFP_CPP_INTERFACE_TYPE_RPC 0x3\n+#define NFP_CPP_INTERFACE_TYPE_ILA 0x4\n \n /**\n * Construct a 16-bit NFP Interface ID\n@@ -316,7 +317,7 @@ uint32_t nfp_cpp_model(struct nfp_cpp *cpp);\n * @return\n * Interface ID\n */\n-#define NFP_CPP_INTERFACE(type, unit, channel)\t\\\n+#define NFP_CPP_INTERFACE(type, unit, channel) \\\n \t((((type) & 0xf) << 12) | \\\n \t (((unit) & 0xf) << 8) | \\\n \t (((channel) & 0xff) << 0))\n@@ -354,7 +355,6 @@ uint32_t nfp_cpp_model(struct nfp_cpp *cpp);\n */\n #define NFP_CPP_INTERFACE_CHANNEL_of(interface)\t(((interface) >> 0) & 0xff)\n \n-\n uint16_t nfp_cpp_interface(struct nfp_cpp *cpp);\n \n int nfp_cpp_serial(struct nfp_cpp *cpp, const uint8_t **serial);\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\nindex 7e94bfb611..28a6278497 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n+++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n@@ -37,7 +37,7 @@\n #include \"nfp6000/nfp6000.h\"\n #include \"../nfp_logs.h\"\n \n-#define NFP_PCIE_BAR(_pf)\t(0x30000 + ((_pf) & 7) * 0xc0)\n+#define NFP_PCIE_BAR(_pf) (0x30000 + ((_pf) & 7) * 0xc0)\n \n #define NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS(_x) (((_x) & 0x1f) << 16)\n #define NFP_PCIE_BAR_PCIE2CPP_BASEADDRESS(_x) (((_x) & 0xffff) << 0)\n@@ -58,7 +58,7 @@\n * Minimal size of the PCIe cfg memory we depend on being mapped,\n * queue controller and DMA controller don't have to be covered.\n */\n-#define NFP_PCI_MIN_MAP_SIZE\t\t\t\t0x080000 /* 512K */\n+#define NFP_PCI_MIN_MAP_SIZE 0x080000 /* 512K */\n \n #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)\n #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)\n@@ -93,7 +93,7 @@ struct nfp_bar {\n \tchar *iomem; /**< mapped IO memory */\n };\n \n-#define BUSDEV_SZ\t13\n+#define BUSDEV_SZ 13\n struct nfp_pcie_user {\n \tstruct nfp_bar bar[NFP_BAR_MAX];\n \n@@ -163,7 +163,6 @@ nfp_compute_bar(const struct nfp_bar *bar,\n \t\t\treturn -EINVAL;\n \n \t\toffset &= mask;\n-\n \t\tbitsize = 40 - 16;\n \t} else {\n \t\tmask = ~(NFP_PCIE_P2C_BULK_SIZE(bar) - 1);\n@@ -171,7 +170,6 @@ nfp_compute_bar(const struct nfp_bar *bar,\n \t\t/* Bulk mapping */\n \t\tnewcfg |= NFP_PCIE_BAR_PCIE2CPP_MAPTYPE\n \t\t\t\t(NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK);\n-\n \t\tnewcfg |= NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(tgt);\n \t\tnewcfg |= NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(tok);\n \n@@ -179,7 +177,6 @@ nfp_compute_bar(const struct nfp_bar *bar,\n \t\t\treturn -EINVAL;\n \n \t\toffset &= mask;\n-\n \t\tbitsize = 40 - 21;\n \t}\n \n@@ -278,6 +275,7 @@ nfp_enable_bars(struct nfp_pcie_user *nfp)\n \t\tstart = NFP_BAR_MAX;\n \t\tend = NFP_BAR_MID;\n \t}\n+\n \tfor (x = start; x > end; x--) {\n \t\tbar = &nfp->bar[x - 1];\n \t\tbar->barcfg = 0;\n@@ -310,6 +308,7 @@ nfp_alloc_bar(struct nfp_pcie_user *nfp)\n \t\tstart = NFP_BAR_MAX;\n \t\tend = NFP_BAR_MID;\n \t}\n+\n \tfor (x = start; x > end; x--) {\n \t\tbar = &nfp->bar[x - 1];\n \t\tif (bar->lock == 0) {\n@@ -317,6 +316,7 @@ nfp_alloc_bar(struct nfp_pcie_user *nfp)\n \t\t\treturn bar;\n \t\t}\n \t}\n+\n \treturn NULL;\n }\n \n@@ -346,7 +346,6 @@ nfp_disable_bars(struct nfp_pcie_user *nfp)\n }\n \n /* Generic CPP bus access interface. */\n-\n struct nfp6000_area_priv {\n \tstruct nfp_bar *bar;\n \tuint32_t bar_offset;\n@@ -443,6 +442,7 @@ static void\n nfp6000_area_release(struct nfp_cpp_area *area)\n {\n \tstruct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);\n+\n \tpriv->bar->lock = 0;\n \tpriv->bar = NULL;\n \tpriv->iomem = NULL;\n@@ -478,7 +478,6 @@ nfp6000_area_read(struct nfp_cpp_area *area,\n \t\treturn -EFAULT;\n \n \twidth = priv->width.read;\n-\n \tif (width <= 0)\n \t\treturn -EINVAL;\n \n@@ -548,7 +547,6 @@ nfp6000_area_write(struct nfp_cpp_area *area,\n \t\treturn -EFAULT;\n \n \twidth = priv->width.write;\n-\n \tif (width <= 0)\n \t\treturn -EINVAL;\n \n@@ -718,6 +716,7 @@ nfp6000_set_barsz(struct rte_pci_device *dev,\n \t\ti++;\n \n \tdesc->barsz = i;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_cppcore.c b/drivers/net/nfp/nfpcore/nfp_cppcore.c\nindex 0e8372576e..c46fd62e32 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cppcore.c\n+++ b/drivers/net/nfp/nfpcore/nfp_cppcore.c\n@@ -433,7 +433,6 @@ nfp_cpp_area_acquire(struct nfp_cpp_area *area)\n {\n \tif (area->cpp->op->area_acquire != NULL) {\n \t\tint err = area->cpp->op->area_acquire(area);\n-\n \t\tif (err < 0) {\n \t\t\tPMD_DRV_LOG(ERR, \"Area acquire op failed\");\n \t\t\treturn -1;\n@@ -862,7 +861,6 @@ nfp_cpp_alloc(struct rte_pci_device *dev,\n \tconst struct nfp_cpp_operations *ops;\n \n \tops = nfp_cpp_transport_operations();\n-\n \tif (ops == NULL || ops->init == NULL)\n \t\treturn NULL;\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_crc.c b/drivers/net/nfp/nfpcore/nfp_crc.c\nindex 68f27f8c68..986c52711d 100644\n--- a/drivers/net/nfp/nfpcore/nfp_crc.c\n+++ b/drivers/net/nfp/nfpcore/nfp_crc.c\n@@ -15,11 +15,13 @@ nfp_crc32_be_generic(uint32_t crc,\n \t\tuint32_t polynomial)\n {\n \tuint32_t i;\n+\n \twhile (len--) {\n \t\tcrc ^= *p++ << 24;\n \t\tfor (i = 0; i < 8; i++)\n \t\t\tcrc = (crc << 1) ^ ((crc & 0x80000000) ? polynomial : 0);\n \t}\n+\n \treturn crc;\n }\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_hwinfo.c b/drivers/net/nfp/nfpcore/nfp_hwinfo.c\nindex f5579ab60f..e33e660ea9 100644\n--- a/drivers/net/nfp/nfpcore/nfp_hwinfo.c\n+++ b/drivers/net/nfp/nfpcore/nfp_hwinfo.c\n@@ -54,6 +54,7 @@ nfp_hwinfo_db_walk(struct nfp_hwinfo *hwinfo,\n \t\t\treturn -EINVAL;\n \t\t}\n \t}\n+\n \treturn 0;\n }\n \n@@ -178,6 +179,7 @@ nfp_hwinfo_read(struct nfp_cpp *cpp)\n \t\tfree(db);\n \t\treturn NULL;\n \t}\n+\n \treturn db;\n }\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_hwinfo.h b/drivers/net/nfp/nfpcore/nfp_hwinfo.h\nindex 424db8035d..37427bb6c8 100644\n--- a/drivers/net/nfp/nfpcore/nfp_hwinfo.h\n+++ b/drivers/net/nfp/nfpcore/nfp_hwinfo.h\n@@ -8,33 +8,31 @@\n \n #include <inttypes.h>\n \n-#define HWINFO_SIZE_MIN\t0x100\n+#define HWINFO_SIZE_MIN 0x100\n \n /*\n * The Hardware Info Table defines the properties of the system.\n *\n * HWInfo v1 Table (fixed size)\n *\n- * 0x0000: uint32_t version\t Hardware Info Table version (1.0)\n- * 0x0004: uint32_t size\t Total size of the table, including the\n- *\t\t\t\t\tCRC32 (IEEE 802.3)\n- * 0x0008: uint32_t jumptab\t Offset of key/value table\n- * 0x000c: uint32_t keys\t Total number of keys in the key/value\n- *\t\t\t\t\ttable\n- * NNNNNN:\t\t\t\tKey/value jump table and string data\n- * (size - 4): uint32_t crc32\tCRC32 (same as IEEE 802.3, POSIX csum, etc)\n- *\t\t\t\tCRC32(\"\",0) = ~0, CRC32(\"a\",1) = 0x48C279FE\n+ * 0x0000: uint32_t version Hardware Info Table version (1.0)\n+ * 0x0004: uint32_t size Total size of the table, including the\n+ * CRC32 (IEEE 802.3)\n+ * 0x0008: uint32_t jumptab Offset of key/value table\n+ * 0x000c: uint32_t keys Total number of keys in the key/value table\n+ * NNNNNN: Key/value jump table and string data\n+ * (size - 4): uint32_t crc32 CRC32 (same as IEEE 802.3, POSIX csum, etc)\n+ * CRC32(\"\",0) = ~0, CRC32(\"a\",1) = 0x48C279FE\n *\n * HWInfo v2 Table (variable size)\n *\n- * 0x0000: uint32_t version\t Hardware Info Table version (2.0)\n- * 0x0004: uint32_t size\t Current size of the data area, excluding\n- *\t\t\t\t\tCRC32\n- * 0x0008: uint32_t limit\t Maximum size of the table\n- * 0x000c: uint32_t reserved\t Unused, set to zero\n- * NNNNNN:\t\t\tKey/value data\n- * (size - 4): uint32_t crc32\tCRC32 (same as IEEE 802.3, POSIX csum, etc)\n- *\t\t\t\tCRC32(\"\",0) = ~0, CRC32(\"a\",1) = 0x48C279FE\n+ * 0x0000: uint32_t version Hardware Info Table version (2.0)\n+ * 0x0004: uint32_t size Current size of the data area, excluding CRC32\n+ * 0x0008: uint32_t limit Maximum size of the table\n+ * 0x000c: uint32_t reserved Unused, set to zero\n+ * NNNNNN: Key/value data\n+ * (size - 4): uint32_t crc32 CRC32 (same as IEEE 802.3, POSIX csum, etc)\n+ * CRC32(\"\",0) = ~0, CRC32(\"a\",1) = 0x48C279FE\n *\n * If the HWInfo table is in the process of being updated, the low bit of\n * version will be set.\n@@ -47,17 +45,16 @@\n *\n * All keys are guaranteed to be unique.\n *\n- * N+0:\tuint32_t key_1\t\tOffset to the first key\n- * N+4:\tuint32_t val_1\t\tOffset to the first value\n- * N+8: uint32_t key_2\t\tOffset to the second key\n- * N+c: uint32_t val_2\t\tOffset to the second value\n+ * N+0: uint32_t key_1 Offset to the first key\n+ * N+4: uint32_t val_1 Offset to the first value\n+ * N+8: uint32_t key_2 Offset to the second key\n+ * N+c: uint32_t val_2 Offset to the second value\n * ...\n *\n * HWInfo v2 Key/Value Table\n * -------------------------\n *\n * Packed UTF8Z strings, ie 'key1\\000value1\\000key2\\000value2\\000'\n- *\n * Unsorted.\n *\n * Note: Only the HwInfo v2 Table be supported now.\n@@ -65,7 +62,7 @@\n \n #define NFP_HWINFO_VERSION_1 ('H' << 24 | 'I' << 16 | 1 << 8 | 0 << 1 | 0)\n #define NFP_HWINFO_VERSION_2 ('H' << 24 | 'I' << 16 | 2 << 8 | 0 << 1 | 0)\n-#define NFP_HWINFO_VERSION_UPDATING\tRTE_BIT32(0)\n+#define NFP_HWINFO_VERSION_UPDATING RTE_BIT32(0)\n \n struct nfp_hwinfo {\n \tuint8_t start[0];\ndiff --git a/drivers/net/nfp/nfpcore/nfp_mip.c b/drivers/net/nfp/nfpcore/nfp_mip.c\nindex 0892c99e96..7f06c24927 100644\n--- a/drivers/net/nfp/nfpcore/nfp_mip.c\n+++ b/drivers/net/nfp/nfpcore/nfp_mip.c\n@@ -11,9 +11,9 @@\n #include \"nfp_mip.h\"\n #include \"nfp_nffw.h\"\n \n-#define NFP_MIP_SIGNATURE\trte_cpu_to_le_32(0x0050494d) /* \"MIP\\0\" */\n-#define NFP_MIP_VERSION\t\trte_cpu_to_le_32(1)\n-#define NFP_MIP_MAX_OFFSET\t(256 * 1024)\n+#define NFP_MIP_SIGNATURE rte_cpu_to_le_32(0x0050494d) /* \"MIP\\0\" */\n+#define NFP_MIP_VERSION rte_cpu_to_le_32(1)\n+#define NFP_MIP_MAX_OFFSET (256 * 1024)\n \n struct nfp_mip {\n \tuint32_t signature;\n@@ -49,11 +49,13 @@ nfp_mip_try_read(struct nfp_cpp *cpp,\n \t\tPMD_DRV_LOG(ERR, \"Failed to read MIP data\");\n \t\treturn -EIO;\n \t}\n+\n \tif (mip->signature != NFP_MIP_SIGNATURE) {\n \t\tPMD_DRV_LOG(ERR, \"Incorrect MIP signature %#08x\",\n \t\t\t\trte_le_to_cpu_32(mip->signature));\n \t\treturn -EINVAL;\n \t}\n+\n \tif (mip->mip_version != NFP_MIP_VERSION) {\n \t\tPMD_DRV_LOG(ERR, \"Unsupported MIP version %d\",\n \t\t\t\trte_le_to_cpu_32(mip->mip_version));\n@@ -82,6 +84,7 @@ nfp_mip_read_resource(struct nfp_cpp *cpp,\n \t\tgoto exit_close_nffw;\n \n \terr = nfp_mip_try_read(cpp, cpp_id, addr, mip);\n+\n exit_close_nffw:\n \tnfp_nffw_info_close(nffw_info);\n \treturn err;\ndiff --git a/drivers/net/nfp/nfpcore/nfp_mip.h b/drivers/net/nfp/nfpcore/nfp_mip.h\nindex 980abc2517..16824a6769 100644\n--- a/drivers/net/nfp/nfpcore/nfp_mip.h\n+++ b/drivers/net/nfp/nfpcore/nfp_mip.h\n@@ -18,4 +18,5 @@ void nfp_mip_symtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size);\n void nfp_mip_strtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size);\n int nfp_nffw_info_mip_first(struct nfp_nffw_info *state, uint32_t *cpp_id,\n \t\tuint64_t *off);\n+\n #endif\ndiff --git a/drivers/net/nfp/nfpcore/nfp_mutex.c b/drivers/net/nfp/nfpcore/nfp_mutex.c\nindex 404d4fa938..e97537b795 100644\n--- a/drivers/net/nfp/nfpcore/nfp_mutex.c\n+++ b/drivers/net/nfp/nfpcore/nfp_mutex.c\n@@ -85,7 +85,7 @@ nfp_cpp_mutex_init(struct nfp_cpp *cpp,\n {\n \tint err;\n \tuint32_t model = nfp_cpp_model(cpp);\n-\tuint32_t muw = NFP_CPP_ID(target, 4, 0);\t/* atomic_write */\n+\tuint32_t muw = NFP_CPP_ID(target, 4, 0); /* atomic_write */\n \n \terr = _nfp_cpp_mutex_validate(model, &target, address);\n \tif (err < 0)\n@@ -134,7 +134,7 @@ nfp_cpp_mutex_alloc(struct nfp_cpp *cpp,\n \tuint32_t tmp;\n \tstruct nfp_cpp_mutex *mutex;\n \tuint32_t model = nfp_cpp_model(cpp);\n-\tuint32_t mur = NFP_CPP_ID(target, 3, 0);\t/* atomic_read */\n+\tuint32_t mur = NFP_CPP_ID(target, 3, 0); /* atomic_read */\n \n \t/* Look for cached mutex */\n \tfor (mutex = cpp->mutex_cache; mutex; mutex = mutex->next) {\n@@ -231,12 +231,15 @@ nfp_cpp_mutex_lock(struct nfp_cpp_mutex *mutex)\n \t\t/* If err != -EBUSY, then the lock was damaged */\n \t\tif (err < 0 && err != -EBUSY)\n \t\t\treturn err;\n+\n \t\tif (time(NULL) >= warn_at) {\n \t\t\tPMD_DRV_LOG(WARNING, \"Waiting for NFP mutex...\");\n \t\t\twarn_at = time(NULL) + 60;\n \t\t}\n+\n \t\tsched_yield();\n \t}\n+\n \treturn 0;\n }\n \n@@ -257,8 +260,8 @@ nfp_cpp_mutex_unlock(struct nfp_cpp_mutex *mutex)\n \tuint32_t value;\n \tstruct nfp_cpp *cpp = mutex->cpp;\n \tuint16_t interface = nfp_cpp_interface(cpp);\n-\tuint32_t muw = NFP_CPP_ID(mutex->target, 4, 0);\t/* atomic_write */\n-\tuint32_t mur = NFP_CPP_ID(mutex->target, 3, 0);\t/* atomic_read */\n+\tuint32_t muw = NFP_CPP_ID(mutex->target, 4, 0); /* atomic_write */\n+\tuint32_t mur = NFP_CPP_ID(mutex->target, 3, 0); /* atomic_read */\n \n \tif (mutex->depth > 1) {\n \t\tmutex->depth--;\n@@ -314,9 +317,9 @@ nfp_cpp_mutex_trylock(struct nfp_cpp_mutex *mutex)\n \tuint32_t tmp;\n \tuint32_t value;\n \tstruct nfp_cpp *cpp = mutex->cpp;\n-\tuint32_t mur = NFP_CPP_ID(mutex->target, 3, 0);\t/* atomic_read */\n-\tuint32_t muw = NFP_CPP_ID(mutex->target, 4, 0);\t/* atomic_write */\n-\tuint32_t mus = NFP_CPP_ID(mutex->target, 5, 3);\t/* test_set_imm */\n+\tuint32_t mur = NFP_CPP_ID(mutex->target, 3, 0); /* atomic_read */\n+\tuint32_t muw = NFP_CPP_ID(mutex->target, 4, 0); /* atomic_write */\n+\tuint32_t mus = NFP_CPP_ID(mutex->target, 5, 3); /* test_set_imm */\n \n \tif (mutex->depth > 0) {\n \t\tif (mutex->depth == MUTEX_DEPTH_MAX)\ndiff --git a/drivers/net/nfp/nfpcore/nfp_nffw.c b/drivers/net/nfp/nfpcore/nfp_nffw.c\nindex 5f004e3b21..be80eeaa0e 100644\n--- a/drivers/net/nfp/nfpcore/nfp_nffw.c\n+++ b/drivers/net/nfp/nfpcore/nfp_nffw.c\n@@ -61,10 +61,10 @@ nffw_fwinfo_mip_offset_get(const struct nffw_fwinfo *fi)\n \treturn (mip_off_hi & 0xFF) << 32 | fi->mip_offset_lo;\n }\n \n-#define NFP_IMB_TGTADDRESSMODECFG_MODE_of(_x)\t\t(((_x) >> 13) & 0x7)\n-#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE\t\tRTE_BIT32(12)\n-#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_32_BIT\t0\n-#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_40_BIT\tRTE_BIT32(12)\n+#define NFP_IMB_TGTADDRESSMODECFG_MODE_of(_x) (((_x) >> 13) & 0x7)\n+#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE RTE_BIT32(12)\n+#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_32_BIT 0\n+#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_40_BIT RTE_BIT32(12)\n \n static int\n nfp_mip_mu_locality_lsb(struct nfp_cpp *cpp)\ndiff --git a/drivers/net/nfp/nfpcore/nfp_nsp.c b/drivers/net/nfp/nfpcore/nfp_nsp.c\nindex a96ccea38b..ca3fc2fa59 100644\n--- a/drivers/net/nfp/nfpcore/nfp_nsp.c\n+++ b/drivers/net/nfp/nfpcore/nfp_nsp.c\n@@ -290,6 +290,7 @@ nfp_nsp_command(struct nfp_nsp *state,\n \terr = nfp_cpp_readq(cpp, nsp_cpp, nsp_command, &ret_val);\n \tif (err < 0)\n \t\treturn err;\n+\n \tret_val = FIELD_GET(NSP_COMMAND_OPTION, ret_val);\n \n \terr = FIELD_GET(NSP_STATUS_RESULT, reg);\n@@ -354,6 +355,7 @@ nfp_nsp_command_buf(struct nfp_nsp *nsp,\n \t\tif (err < 0)\n \t\t\treturn err;\n \t}\n+\n \t/* Zero out remaining part of the buffer */\n \tif (out_buf != NULL && out_size > 0 && out_size > in_size) {\n \t\tmemset(out_buf, 0, out_size - in_size);\n@@ -400,6 +402,7 @@ nfp_nsp_wait(struct nfp_nsp *state)\n \t\t\tbreak;\n \t\t}\n \t}\n+\n \tif (err != 0)\n \t\tPMD_DRV_LOG(ERR, \"NSP failed to respond %d\", err);\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_nsp.h b/drivers/net/nfp/nfpcore/nfp_nsp.h\nindex 0fcb21e99c..ee58bf33b8 100644\n--- a/drivers/net/nfp/nfpcore/nfp_nsp.h\n+++ b/drivers/net/nfp/nfpcore/nfp_nsp.h\n@@ -10,73 +10,72 @@\n #include \"nfp_nsp.h\"\n \n #define GENMASK_ULL(h, l) \\\n-\t(((~0ULL) - (1ULL << (l)) + 1) & \\\n-\t (~0ULL >> (64 - 1 - (h))))\n+\t(((~0ULL) - (1ULL << (l)) + 1) & (~0ULL >> (64 - 1 - (h))))\n \n #define __bf_shf(x) (__builtin_ffsll(x) - 1)\n \n-#define FIELD_GET(_mask, _reg)\t\\\n+#define FIELD_GET(_mask, _reg) \\\n \t(__extension__ ({ \\\n \t\ttypeof(_mask) _x = (_mask); \\\n-\t\t(typeof(_x))(((_reg) & (_x)) >> __bf_shf(_x));\t\\\n+\t\t(typeof(_x))(((_reg) & (_x)) >> __bf_shf(_x)); \\\n \t}))\n \n-#define FIELD_FIT(_mask, _val)\t\t\t\t\t\t\\\n+#define FIELD_FIT(_mask, _val) \\\n \t(__extension__ ({ \\\n \t\ttypeof(_mask) _x = (_mask); \\\n \t\t!((((typeof(_x))_val) << __bf_shf(_x)) & ~(_x)); \\\n \t}))\n \n-#define FIELD_PREP(_mask, _val)\t\t\t\t\t\t\\\n+#define FIELD_PREP(_mask, _val) \\\n \t(__extension__ ({ \\\n \t\ttypeof(_mask) _x = (_mask); \\\n-\t\t((typeof(_x))(_val) << __bf_shf(_x)) & (_x);\t\\\n+\t\t((typeof(_x))(_val) << __bf_shf(_x)) & (_x); \\\n \t}))\n \n /* Offsets relative to the CSR base */\n-#define NSP_STATUS\t\t0x00\n-#define NSP_STATUS_MAGIC\tGENMASK_ULL(63, 48)\n-#define NSP_STATUS_MAJOR\tGENMASK_ULL(47, 44)\n-#define NSP_STATUS_MINOR\tGENMASK_ULL(43, 32)\n-#define NSP_STATUS_CODE\tGENMASK_ULL(31, 16)\n-#define NSP_STATUS_RESULT\tGENMASK_ULL(15, 8)\n-#define NSP_STATUS_BUSY\tRTE_BIT64(0)\n-\n-#define NSP_COMMAND\t\t0x08\n-#define NSP_COMMAND_OPTION\tGENMASK_ULL(63, 32)\n-#define NSP_COMMAND_CODE\tGENMASK_ULL(31, 16)\n-#define NSP_COMMAND_START\tRTE_BIT64(0)\n+#define NSP_STATUS 0x00\n+#define NSP_STATUS_MAGIC GENMASK_ULL(63, 48)\n+#define NSP_STATUS_MAJOR GENMASK_ULL(47, 44)\n+#define NSP_STATUS_MINOR GENMASK_ULL(43, 32)\n+#define NSP_STATUS_CODE GENMASK_ULL(31, 16)\n+#define NSP_STATUS_RESULT GENMASK_ULL(15, 8)\n+#define NSP_STATUS_BUSY RTE_BIT64(0)\n+\n+#define NSP_COMMAND 0x08\n+#define NSP_COMMAND_OPTION GENMASK_ULL(63, 32)\n+#define NSP_COMMAND_CODE GENMASK_ULL(31, 16)\n+#define NSP_COMMAND_START RTE_BIT64(0)\n \n /* CPP address to retrieve the data from */\n-#define NSP_BUFFER\t\t0x10\n-#define NSP_BUFFER_CPP\tGENMASK_ULL(63, 40)\n-#define NSP_BUFFER_PCIE\tGENMASK_ULL(39, 38)\n-#define NSP_BUFFER_ADDRESS\tGENMASK_ULL(37, 0)\n+#define NSP_BUFFER 0x10\n+#define NSP_BUFFER_CPP GENMASK_ULL(63, 40)\n+#define NSP_BUFFER_PCIE GENMASK_ULL(39, 38)\n+#define NSP_BUFFER_ADDRESS GENMASK_ULL(37, 0)\n \n-#define NSP_DFLT_BUFFER\t\t0x18\n+#define NSP_DFLT_BUFFER 0x18\n \n-#define NSP_DFLT_BUFFER_CONFIG\t0x20\n-#define NSP_DFLT_BUFFER_SIZE_MB\tGENMASK_ULL(7, 0)\n+#define NSP_DFLT_BUFFER_CONFIG 0x20\n+#define NSP_DFLT_BUFFER_SIZE_MB GENMASK_ULL(7, 0)\n \n-#define NSP_MAGIC\t\t0xab10\n-#define NSP_MAJOR\t\t0\n-#define NSP_MINOR\t\t8\n+#define NSP_MAGIC 0xab10\n+#define NSP_MAJOR 0\n+#define NSP_MINOR 8\n \n-#define NSP_CODE_MAJOR\t\tGENMASK(15, 12)\n-#define NSP_CODE_MINOR\t\tGENMASK(11, 0)\n+#define NSP_CODE_MAJOR GENMASK(15, 12)\n+#define NSP_CODE_MINOR GENMASK(11, 0)\n \n enum nfp_nsp_cmd {\n-\tSPCODE_NOOP\t\t= 0, /* No operation */\n-\tSPCODE_SOFT_RESET\t= 1, /* Soft reset the NFP */\n-\tSPCODE_FW_DEFAULT\t= 2, /* Load default (UNDI) FW */\n-\tSPCODE_PHY_INIT\t\t= 3, /* Initialize the PHY */\n-\tSPCODE_MAC_INIT\t\t= 4, /* Initialize the MAC */\n-\tSPCODE_PHY_RXADAPT\t= 5, /* Re-run PHY RX Adaptation */\n-\tSPCODE_FW_LOAD\t\t= 6, /* Load fw from buffer, len in option */\n-\tSPCODE_ETH_RESCAN\t= 7, /* Rescan ETHs, write ETH_TABLE to buf */\n-\tSPCODE_ETH_CONTROL\t= 8, /* Update media config from buffer */\n-\tSPCODE_NSP_SENSORS\t= 12, /* Read NSP sensor(s) */\n-\tSPCODE_NSP_IDENTIFY\t= 13, /* Read NSP version */\n+\tSPCODE_NOOP = 0, /* No operation */\n+\tSPCODE_SOFT_RESET = 1, /* Soft reset the NFP */\n+\tSPCODE_FW_DEFAULT = 2, /* Load default (UNDI) FW */\n+\tSPCODE_PHY_INIT = 3, /* Initialize the PHY */\n+\tSPCODE_MAC_INIT = 4, /* Initialize the MAC */\n+\tSPCODE_PHY_RXADAPT = 5, /* Re-run PHY RX Adaptation */\n+\tSPCODE_FW_LOAD = 6, /* Load fw from buffer, len in option */\n+\tSPCODE_ETH_RESCAN = 7, /* Rescan ETHs, write ETH_TABLE to buf */\n+\tSPCODE_ETH_CONTROL = 8, /* Update media config from buffer */\n+\tSPCODE_NSP_SENSORS = 12, /* Read NSP sensor(s) */\n+\tSPCODE_NSP_IDENTIFY = 13, /* Read NSP version */\n };\n \n static const struct {\n@@ -123,13 +122,13 @@ nfp_nsp_has_mac_reinit(struct nfp_nsp *state)\n }\n \n enum nfp_eth_interface {\n-\tNFP_INTERFACE_NONE\t= 0,\n-\tNFP_INTERFACE_SFP\t= 1,\n-\tNFP_INTERFACE_SFPP\t= 10,\n-\tNFP_INTERFACE_SFP28\t= 28,\n-\tNFP_INTERFACE_QSFP\t= 40,\n-\tNFP_INTERFACE_CXP\t= 100,\n-\tNFP_INTERFACE_QSFP28\t= 112,\n+\tNFP_INTERFACE_NONE = 0,\n+\tNFP_INTERFACE_SFP = 1,\n+\tNFP_INTERFACE_SFPP = 10,\n+\tNFP_INTERFACE_SFP28 = 28,\n+\tNFP_INTERFACE_QSFP = 40,\n+\tNFP_INTERFACE_CXP = 100,\n+\tNFP_INTERFACE_QSFP28 = 112,\n };\n \n enum nfp_eth_media {\n@@ -153,10 +152,10 @@ enum nfp_eth_fec {\n \tNFP_FEC_DISABLED_BIT,\n };\n \n-#define NFP_FEC_AUTO\t\tRTE_BIT32(NFP_FEC_AUTO_BIT)\n-#define NFP_FEC_BASER\t\tRTE_BIT32(NFP_FEC_BASER_BIT)\n-#define NFP_FEC_REED_SOLOMON\tRTE_BIT32(NFP_FEC_REED_SOLOMON_BIT)\n-#define NFP_FEC_DISABLED\tRTE_BIT32(NFP_FEC_DISABLED_BIT)\n+#define NFP_FEC_AUTO RTE_BIT32(NFP_FEC_AUTO_BIT)\n+#define NFP_FEC_BASER RTE_BIT32(NFP_FEC_BASER_BIT)\n+#define NFP_FEC_REED_SOLOMON RTE_BIT32(NFP_FEC_REED_SOLOMON_BIT)\n+#define NFP_FEC_DISABLED RTE_BIT32(NFP_FEC_DISABLED_BIT)\n \n /* ETH table information */\n struct nfp_eth_table {\ndiff --git a/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c b/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c\nindex 3081e22dad..769ed54957 100644\n--- a/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c\n+++ b/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c\n@@ -107,5 +107,6 @@ nfp_hwmon_read_sensor(struct nfp_cpp *cpp,\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n+\n \treturn 0;\n }\ndiff --git a/drivers/net/nfp/nfpcore/nfp_nsp_eth.c b/drivers/net/nfp/nfpcore/nfp_nsp_eth.c\nindex cb090d2a47..d291552d03 100644\n--- a/drivers/net/nfp/nfpcore/nfp_nsp_eth.c\n+++ b/drivers/net/nfp/nfpcore/nfp_nsp_eth.c\n@@ -11,70 +11,68 @@\n #include \"nfp_nsp.h\"\n #include \"nfp6000/nfp6000.h\"\n \n-#define NSP_ETH_NBI_PORT_COUNT\t\t24\n-#define NSP_ETH_MAX_COUNT\t\t(2 * NSP_ETH_NBI_PORT_COUNT)\n-#define NSP_ETH_TABLE_SIZE\t\t(NSP_ETH_MAX_COUNT *\t\t\\\n-\t\t\t\t\t sizeof(union eth_table_entry))\n-\n-#define NSP_ETH_PORT_LANES\t\tGENMASK_ULL(3, 0)\n-#define NSP_ETH_PORT_INDEX\t\tGENMASK_ULL(15, 8)\n-#define NSP_ETH_PORT_LABEL\t\tGENMASK_ULL(53, 48)\n-#define NSP_ETH_PORT_PHYLABEL\t\tGENMASK_ULL(59, 54)\n-#define NSP_ETH_PORT_FEC_SUPP_BASER\tRTE_BIT64(60)\n-#define NSP_ETH_PORT_FEC_SUPP_RS\tRTE_BIT64(61)\n-\n-#define NSP_ETH_PORT_LANES_MASK\t\trte_cpu_to_le_64(NSP_ETH_PORT_LANES)\n-\n-#define NSP_ETH_STATE_CONFIGURED\tRTE_BIT64(0)\n-#define NSP_ETH_STATE_ENABLED\t\tRTE_BIT64(1)\n-#define NSP_ETH_STATE_TX_ENABLED\tRTE_BIT64(2)\n-#define NSP_ETH_STATE_RX_ENABLED\tRTE_BIT64(3)\n-#define NSP_ETH_STATE_RATE\t\tGENMASK_ULL(11, 8)\n-#define NSP_ETH_STATE_INTERFACE\t\tGENMASK_ULL(19, 12)\n-#define NSP_ETH_STATE_MEDIA\t\tGENMASK_ULL(21, 20)\n-#define NSP_ETH_STATE_OVRD_CHNG\t\tRTE_BIT64(22)\n-#define NSP_ETH_STATE_ANEG\t\tGENMASK_ULL(25, 23)\n-#define NSP_ETH_STATE_FEC\t\tGENMASK_ULL(27, 26)\n-\n-#define NSP_ETH_CTRL_CONFIGURED\t\tRTE_BIT64(0)\n-#define NSP_ETH_CTRL_ENABLED\t\tRTE_BIT64(1)\n-#define NSP_ETH_CTRL_TX_ENABLED\t\tRTE_BIT64(2)\n-#define NSP_ETH_CTRL_RX_ENABLED\t\tRTE_BIT64(3)\n-#define NSP_ETH_CTRL_SET_RATE\t\tRTE_BIT64(4)\n-#define NSP_ETH_CTRL_SET_LANES\t\tRTE_BIT64(5)\n-#define NSP_ETH_CTRL_SET_ANEG\t\tRTE_BIT64(6)\n-#define NSP_ETH_CTRL_SET_FEC\t\tRTE_BIT64(7)\n+#define NSP_ETH_NBI_PORT_COUNT 24\n+#define NSP_ETH_MAX_COUNT (2 * NSP_ETH_NBI_PORT_COUNT)\n+#define NSP_ETH_TABLE_SIZE (NSP_ETH_MAX_COUNT * sizeof(union eth_table_entry))\n+\n+#define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0)\n+#define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8)\n+#define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48)\n+#define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54)\n+#define NSP_ETH_PORT_FEC_SUPP_BASER RTE_BIT64(60)\n+#define NSP_ETH_PORT_FEC_SUPP_RS RTE_BIT64(61)\n+\n+#define NSP_ETH_PORT_LANES_MASK rte_cpu_to_le_64(NSP_ETH_PORT_LANES)\n+\n+#define NSP_ETH_STATE_CONFIGURED RTE_BIT64(0)\n+#define NSP_ETH_STATE_ENABLED RTE_BIT64(1)\n+#define NSP_ETH_STATE_TX_ENABLED RTE_BIT64(2)\n+#define NSP_ETH_STATE_RX_ENABLED RTE_BIT64(3)\n+#define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8)\n+#define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12)\n+#define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20)\n+#define NSP_ETH_STATE_OVRD_CHNG RTE_BIT64(22)\n+#define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23)\n+#define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26)\n+\n+#define NSP_ETH_CTRL_CONFIGURED RTE_BIT64(0)\n+#define NSP_ETH_CTRL_ENABLED RTE_BIT64(1)\n+#define NSP_ETH_CTRL_TX_ENABLED RTE_BIT64(2)\n+#define NSP_ETH_CTRL_RX_ENABLED RTE_BIT64(3)\n+#define NSP_ETH_CTRL_SET_RATE RTE_BIT64(4)\n+#define NSP_ETH_CTRL_SET_LANES RTE_BIT64(5)\n+#define NSP_ETH_CTRL_SET_ANEG RTE_BIT64(6)\n+#define NSP_ETH_CTRL_SET_FEC RTE_BIT64(7)\n \n /* Which connector port. */\n-#define PORT_TP\t\t\t0x00\n-#define PORT_AUI\t\t0x01\n-#define PORT_MII\t\t0x02\n-#define PORT_FIBRE\t\t0x03\n-#define PORT_BNC\t\t0x04\n-#define PORT_DA\t\t\t0x05\n-#define PORT_NONE\t\t0xef\n-#define PORT_OTHER\t\t0xff\n-\n-#define SPEED_10\t\t10\n-#define SPEED_100\t\t100\n-#define SPEED_1000\t\t1000\n-#define SPEED_2500\t\t2500\n-#define SPEED_5000\t\t5000\n-#define SPEED_10000\t\t10000\n-#define SPEED_14000\t\t14000\n-#define SPEED_20000\t\t20000\n-#define SPEED_25000\t\t25000\n-#define SPEED_40000\t\t40000\n-#define SPEED_50000\t\t50000\n-#define SPEED_56000\t\t56000\n-#define SPEED_100000\t\t100000\n+#define PORT_TP 0x00\n+#define PORT_AUI 0x01\n+#define PORT_MII 0x02\n+#define PORT_FIBRE 0x03\n+#define PORT_BNC 0x04\n+#define PORT_DA 0x05\n+#define PORT_NONE 0xef\n+#define PORT_OTHER 0xff\n+\n+#define SPEED_10 10\n+#define SPEED_100 100\n+#define SPEED_1000 1000\n+#define SPEED_2500 2500\n+#define SPEED_5000 5000\n+#define SPEED_10000 10000\n+#define SPEED_14000 14000\n+#define SPEED_20000 20000\n+#define SPEED_25000 25000\n+#define SPEED_40000 40000\n+#define SPEED_50000 50000\n+#define SPEED_56000 56000\n+#define SPEED_100000 100000\n \n enum nfp_eth_raw {\n \tNSP_ETH_RAW_PORT = 0,\n \tNSP_ETH_RAW_STATE,\n \tNSP_ETH_RAW_MAC,\n \tNSP_ETH_RAW_CONTROL,\n-\n \tNSP_ETH_NUM_RAW\n };\n \n@@ -102,12 +100,12 @@ static const struct {\n \tenum nfp_eth_rate rate;\n \tuint32_t speed;\n } nsp_eth_rate_tbl[] = {\n-\t{ RATE_INVALID,\t0, },\n-\t{ RATE_10M,\tSPEED_10, },\n-\t{ RATE_100M,\tSPEED_100, },\n-\t{ RATE_1G,\tSPEED_1000, },\n-\t{ RATE_10G,\tSPEED_10000, },\n-\t{ RATE_25G,\tSPEED_25000, },\n+\t{ RATE_INVALID, 0, },\n+\t{ RATE_10M, SPEED_10, },\n+\t{ RATE_100M, SPEED_100, },\n+\t{ RATE_1G, SPEED_1000, },\n+\t{ RATE_10G, SPEED_10000, },\n+\t{ RATE_25G, SPEED_25000, },\n };\n \n static uint32_t\n@@ -212,10 +210,12 @@ nfp_eth_calc_port_geometry(struct nfp_eth_table *table)\n \t\t\tif (table->ports[i].label_port !=\n \t\t\t\t\ttable->ports[j].label_port)\n \t\t\t\tcontinue;\n+\n \t\t\ttable->ports[i].port_lanes += table->ports[j].lanes;\n \n \t\t\tif (i == j)\n \t\t\t\tcontinue;\n+\n \t\t\tif (table->ports[i].label_subport ==\n \t\t\t\t\ttable->ports[j].label_subport)\n \t\t\t\tPMD_DRV_LOG(DEBUG, \"Port %d subport %d is a duplicate\",\n@@ -556,11 +556,11 @@ nfp_eth_set_bit_config(struct nfp_nsp *nsp,\n \treturn 0;\n }\n \n-#define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit)\t\\\n-\t(__extension__ ({ \\\n-\t\ttypeof(mask) _x = (mask); \\\n+#define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \\\n+\t(__extension__ ({ \\\n+\t\ttypeof(mask) _x = (mask); \\\n \t\tnfp_eth_set_bit_config(nsp, raw_idx, _x, __bf_shf(_x), \\\n-\t\t\t\tval, ctrl_bit);\t\t\t\\\n+\t\t\t\tval, ctrl_bit); \\\n \t}))\n \n /**\ndiff --git a/drivers/net/nfp/nfpcore/nfp_resource.c b/drivers/net/nfp/nfpcore/nfp_resource.c\nindex bdebf5c3aa..54bcc5f234 100644\n--- a/drivers/net/nfp/nfpcore/nfp_resource.c\n+++ b/drivers/net/nfp/nfpcore/nfp_resource.c\n@@ -13,14 +13,14 @@\n #include \"nfp_resource.h\"\n #include \"nfp_crc.h\"\n \n-#define NFP_RESOURCE_TBL_TARGET\t\tNFP_CPP_TARGET_MU\n-#define NFP_RESOURCE_TBL_BASE\t\t0x8100000000ULL\n+#define NFP_RESOURCE_TBL_TARGET NFP_CPP_TARGET_MU\n+#define NFP_RESOURCE_TBL_BASE 0x8100000000ULL\n \n /* NFP Resource Table self-identifier */\n-#define NFP_RESOURCE_TBL_NAME\t\t\"nfp.res\"\n-#define NFP_RESOURCE_TBL_KEY\t\t0x00000000 /* Special key for entry 0 */\n+#define NFP_RESOURCE_TBL_NAME \"nfp.res\"\n+#define NFP_RESOURCE_TBL_KEY 0x00000000 /* Special key for entry 0 */\n \n-#define NFP_RESOURCE_ENTRY_NAME_SZ\t8\n+#define NFP_RESOURCE_ENTRY_NAME_SZ 8\n \n /* Resource table entry */\n struct nfp_resource_entry {\n@@ -42,9 +42,9 @@ struct nfp_resource_entry {\n \t} region;\n };\n \n-#define NFP_RESOURCE_TBL_SIZE\t\t4096\n-#define NFP_RESOURCE_TBL_ENTRIES\t(int)(NFP_RESOURCE_TBL_SIZE /\t\\\n-\t\t\t\t\t sizeof(struct nfp_resource_entry))\n+#define NFP_RESOURCE_TBL_SIZE 4096\n+#define NFP_RESOURCE_TBL_ENTRIES (int)(NFP_RESOURCE_TBL_SIZE / \\\n+\t\t\t\t\tsizeof(struct nfp_resource_entry))\n \n struct nfp_resource {\n \tchar name[NFP_RESOURCE_ENTRY_NAME_SZ + 1];\n@@ -75,6 +75,7 @@ nfp_cpp_resource_find(struct nfp_cpp *cpp,\n \t\tPMD_DRV_LOG(ERR, \"Grabbing device lock not supported\");\n \t\treturn -EOPNOTSUPP;\n \t}\n+\n \tkey = nfp_crc32_posix(name_pad, NFP_RESOURCE_ENTRY_NAME_SZ);\n \n \tfor (i = 0; i < NFP_RESOURCE_TBL_ENTRIES; i++) {\n@@ -96,6 +97,7 @@ nfp_cpp_resource_find(struct nfp_cpp *cpp,\n \t\t\t\tentry.region.cpp_token);\n \t\tres->addr = ((uint64_t)entry.region.page_offset) << 8;\n \t\tres->size = (uint64_t)entry.region.page_size << 8;\n+\n \t\treturn 0;\n \t}\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_rtsym.c b/drivers/net/nfp/nfpcore/nfp_rtsym.c\nindex 0e6c0f9fe1..37811ceaeb 100644\n--- a/drivers/net/nfp/nfpcore/nfp_rtsym.c\n+++ b/drivers/net/nfp/nfpcore/nfp_rtsym.c\n@@ -17,18 +17,18 @@\n #include \"nfp6000/nfp6000.h\"\n \n /* These need to match the linker */\n-#define SYM_TGT_LMEM\t\t0\n-#define SYM_TGT_EMU_CACHE\t0x17\n+#define SYM_TGT_LMEM 0\n+#define SYM_TGT_EMU_CACHE 0x17\n \n struct nfp_rtsym_entry {\n-\tuint8_t\ttype;\n-\tuint8_t\ttarget;\n-\tuint8_t\tisland;\n-\tuint8_t\taddr_hi;\n+\tuint8_t type;\n+\tuint8_t target;\n+\tuint8_t island;\n+\tuint8_t addr_hi;\n \tuint32_t addr_lo;\n \tuint16_t name;\n-\tuint8_t\tmenum;\n-\tuint8_t\tsize_hi;\n+\tuint8_t menum;\n+\tuint8_t size_hi;\n \tuint32_t size_lo;\n };\n \ndiff --git a/drivers/net/nfp/nfpcore/nfp_rtsym.h b/drivers/net/nfp/nfpcore/nfp_rtsym.h\nindex ff1facbd17..de1966f04b 100644\n--- a/drivers/net/nfp/nfpcore/nfp_rtsym.h\n+++ b/drivers/net/nfp/nfpcore/nfp_rtsym.h\n@@ -57,4 +57,5 @@ uint64_t nfp_rtsym_read_le(struct nfp_rtsym_table *rtbl, const char *name,\n \t\tint *error);\n uint8_t *nfp_rtsym_map(struct nfp_rtsym_table *rtbl, const char *name,\n \t\tuint32_t min_size, struct nfp_cpp_area **area);\n+\n #endif\n", "prefixes": [ "v5", "08/26" ] }