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GET /api/patches/131586/?format=api
{ "id": 131586, "url": "http://patches.dpdk.org/api/patches/131586/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230919012136.2818396-8-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230919012136.2818396-8-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230919012136.2818396-8-nicolas.chautru@intel.com", "date": "2023-09-19T01:21:36", "name": "[v1,7/7] baseband/acc: add configure helper for VRB2", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "18c4c6961a8e18b775a78c78b1d1e8dcb476de60", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230919012136.2818396-8-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29539, "url": "http://patches.dpdk.org/api/series/29539/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29539", "date": "2023-09-19T01:21:29", "name": "VRB2 BBDEV PMD introduction", "version": 1, "mbox": "http://patches.dpdk.org/series/29539/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131586/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/131586/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6BE87425F2;\n\tTue, 19 Sep 2023 03:25:38 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B834D402E1;\n\tTue, 19 Sep 2023 03:25:02 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 9CEBD40275\n for <dev@dpdk.org>; Tue, 19 Sep 2023 03:24:56 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Sep 2023 18:24:55 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by orsmga002.jf.intel.com with ESMTP; 18 Sep 2023 18:24:55 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695086696; x=1726622696;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=6dpXh6lsCysFTMwxuNDtZycsKLB9eXl/ceVlTMUdV+4=;\n b=hduoRyi5eo8/BEc3avL3Q42zePuFkdZ0GQ/5agIkwepFc0BHWXJyPAVV\n MgUzSjVDKJhD/f0bBmcJ9DLwfXtfB8tBZKUVThvYD/qFhqd5eD6FjiB0F\n jEU8MrAh14pBmW4icFoLd0ibrMO1jyZIgijmpdXVJh2WfhYP5nxxrfnQ9\n GyYE2/JWdW0mvMWvofJBpijZ+I35jDFxIX6/UvJCZ6nJoaUUcXyoEezb8\n Fd1FaIz5Knruyko47+qYWsF87lw+caEhq0LC7fTvGmw10eZleO83kNSTg\n RCUqWoh4YD5JF4ADdFPnPbKWhf44RvsZRiyzkkoyWlLd7MzJ1/muQ36JD w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10837\"; a=\"360078110\"", "E=Sophos;i=\"6.02,158,1688454000\"; d=\"scan'208\";a=\"360078110\"", "E=McAfee;i=\"6600,9927,10837\"; a=\"746039467\"", "E=Sophos;i=\"6.02,158,1688454000\"; d=\"scan'208\";a=\"746039467\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v1 7/7] baseband/acc: add configure helper for VRB2", "Date": "Tue, 19 Sep 2023 01:21:36 +0000", "Message-Id": "<20230919012136.2818396-8-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230919012136.2818396-1-nicolas.chautru@intel.com>", "References": "<20230919012136.2818396-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This allows to configure the VRB2 device using a\ncompanion configuration function within the DPDK\nbbdev-test environment.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/acc100_pmd.h | 2 +\n drivers/baseband/acc/acc_common.h | 7 +\n drivers/baseband/acc/rte_acc100_pmd.c | 6 +-\n drivers/baseband/acc/rte_vrb_pmd.c | 322 ++++++++++++++++++++++++++\n drivers/baseband/acc/vrb_cfg.h | 16 ++\n 5 files changed, 352 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h\nindex a48298650c..5a8965fa53 100644\n--- a/drivers/baseband/acc/acc100_pmd.h\n+++ b/drivers/baseband/acc/acc100_pmd.h\n@@ -34,6 +34,8 @@\n #define ACC100_VENDOR_ID (0x8086)\n #define ACC100_PF_DEVICE_ID (0x0d5c)\n #define ACC100_VF_DEVICE_ID (0x0d5d)\n+#define VRB1_PF_DEVICE_ID (0x57C0)\n+#define VRB2_PF_DEVICE_ID (0x57C2)\n \n /* Values used in writing to the registers */\n #define ACC100_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */\ndiff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h\nindex 56578c43ba..8c2f1db262 100644\n--- a/drivers/baseband/acc/acc_common.h\n+++ b/drivers/baseband/acc/acc_common.h\n@@ -1480,6 +1480,13 @@ get_num_cbs_in_tb_ldpc_enc(struct rte_bbdev_op_ldpc_enc *ldpc_enc)\n \treturn cbs_in_tb;\n }\n \n+static inline void\n+acc_reg_fast_write(struct acc_device *d, uint32_t offset, uint32_t value)\n+{\n+\tvoid *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);\n+\tmmio_write(reg_addr, value);\n+}\n+\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n static inline void\n acc_memdump(const char *string, void *buf, uint16_t bytes)\ndiff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex 7f8d05b5a9..699a227d13 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -5187,6 +5187,10 @@ rte_acc_configure(const char *dev_name, struct rte_acc_conf *conf)\n \t\treturn acc100_configure(dev_name, conf);\n \telse if (pci_dev->id.device_id == ACC101_PF_DEVICE_ID)\n \t\treturn acc101_configure(dev_name, conf);\n-\telse\n+\telse if (pci_dev->id.device_id == VRB1_PF_DEVICE_ID)\n \t\treturn vrb1_configure(dev_name, conf);\n+\telse if (pci_dev->id.device_id == VRB2_PF_DEVICE_ID)\n+\t\treturn vrb2_configure(dev_name, conf);\n+\n+\treturn -ENXIO;\n }\ndiff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex 36d2c8173d..76efc8faf1 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -5073,3 +5073,325 @@ vrb1_configure(const char *dev_name, struct rte_acc_conf *conf)\n \trte_bbdev_log_debug(\"PF Tip configuration complete for %s\", dev_name);\n \treturn 0;\n }\n+\n+\n+/* Initial configuration of a VRB2 device prior to running configure(). */\n+int\n+vrb2_configure(const char *dev_name, struct rte_acc_conf *conf)\n+{\n+\trte_bbdev_log(INFO, \"vrb2_configure\");\n+\tuint32_t value, address, status;\n+\tint qg_idx, template_idx, vf_idx, acc, i, aq_reg, static_allocation, numEngines;\n+\tint numQgs, numQqsAcc, totalQgs;\n+\tint qman_func_id[8] = {0, 2, 1, 3, 4, 5, 0, 0};\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\tint rlim, alen, timestamp;\n+\n+\t/* Compile time checks */\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_dma_req_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(union acc_dma_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_fcw_td) != 24);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_fcw_te) != 32);\n+\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\tstruct acc_device *d = bbdev->data->dev_private;\n+\n+\t/* Store configuration */\n+\trte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf));\n+\n+\t/* Explicitly releasing AXI as this may be stopped after PF FLR/BME */\n+\taddress = VRB2_PfDmaAxiControl;\n+\tvalue = 1;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Set the fabric mode */\n+\taddress = VRB2_PfFabricM2iBufferReg;\n+\tvalue = VRB2_FABRIC_MODE;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Set default descriptor signature */\n+\taddress = VRB2_PfDmaDescriptorSignature;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Enable the Error Detection in DMA */\n+\tvalue = VRB2_CFG_DMA_ERROR;\n+\taddress = VRB2_PfDmaErrorDetectionEn;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* AXI Cache configuration */\n+\tvalue = VRB2_CFG_AXI_CACHE;\n+\taddress = VRB2_PfDmaAxcacheReg;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* AXI Response configuration */\n+\tacc_reg_write(d, VRB2_PfDmaCfgRrespBresp, 0x0);\n+\n+\t/* Default DMA Configuration (Qmgr Enabled) */\n+\tacc_reg_write(d, VRB2_PfDmaConfig0Reg, 0);\n+\tacc_reg_write(d, VRB2_PfDmaQmanenSelect, 0xFFFFFFFF);\n+\tacc_reg_write(d, VRB2_PfDmaQmanen, 0);\n+\n+\t/* Default RLIM/ALEN configuration */\n+\trlim = 0;\n+\talen = 3;\n+\ttimestamp = 0;\n+\taddress = VRB2_PfDmaConfig1Reg;\n+\tvalue = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Default FFT configuration */\n+\tfor (template_idx = 0; template_idx < VRB2_FFT_NUM; template_idx++) {\n+\t\tacc_reg_write(d, VRB2_PfFftConfig0 + template_idx * 0x1000, VRB2_FFT_CFG_0);\n+\t\tacc_reg_write(d, VRB2_PfFftParityMask8 + template_idx * 0x1000, VRB2_FFT_ECC);\n+\t}\n+\n+\t/* Configure DMA Qmanager addresses */\n+\taddress = VRB2_PfDmaQmgrAddrReg;\n+\tvalue = VRB2_PfQmgrEgressQueuesTemplate;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* ===== Qmgr Configuration ===== */\n+\t/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */\n+\ttotalQgs = conf->q_ul_4g.num_qgroups + conf->q_ul_5g.num_qgroups +\n+\t\t\tconf->q_dl_4g.num_qgroups + conf->q_dl_5g.num_qgroups +\n+\t\t\tconf->q_fft.num_qgroups + conf->q_mld.num_qgroups;\n+\tfor (qg_idx = 0; qg_idx < VRB2_NUM_QGRPS; qg_idx++) {\n+\t\taddress = VRB2_PfQmgrDepthLog2Grp + ACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = aqDepth(qg_idx, conf);\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrTholdGrp + ACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\t/* Template Priority in incremental order */\n+\tfor (template_idx = 0; template_idx < ACC_NUM_TMPL; template_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_0;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_1;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg2Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_2;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_3;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_4;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg5Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_5;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg6Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_6;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = VRB2_PfQmgrGrpTmplateReg7Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_7;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\taddress = VRB2_PfQmgrGrpPriority;\n+\tvalue = VRB2_CFG_QMGR_HI_P;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Template Configuration */\n+\tfor (template_idx = 0; template_idx < ACC_NUM_TMPL; template_idx++) {\n+\t\tvalue = 0;\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 4GUL */\n+\tnumQgs = conf->q_ul_4g.num_qgroups;\n+\tnumQqsAcc = 0;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_UL_4G; template_idx <= VRB2_SIG_UL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 5GUL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs = conf->q_ul_5g.num_qgroups;\n+\tvalue = 0;\n+\tnumEngines = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_UL_5G; template_idx <= VRB2_SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\t/* Check engine power-on status */\n+\t\taddress = VRB2_PfFecUl5gIbDebug0Reg + ACC_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc_reg_read(d, address) >> 4) & 0x7;\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tif (status == 1) {\n+\t\t\tacc_reg_write(d, address, value);\n+\t\t\tnumEngines++;\n+\t\t} else\n+\t\t\tacc_reg_write(d, address, 0);\n+\t}\n+\trte_bbdev_log(INFO, \"Number of 5GUL engines %d\", numEngines);\n+\t/* 4GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_4g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_DL_4G; template_idx <= VRB2_SIG_DL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 5GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_5g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_DL_5G; template_idx <= VRB2_SIG_DL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* FFT */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_fft.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_FFT; template_idx <= VRB2_SIG_FFT_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* MLD */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_mld.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = VRB2_SIG_MLD; template_idx <= VRB2_SIG_MLD_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = VRB2_PfQmgrGrpTmplateEnRegIndx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\t/* Queue Group Function mapping */\n+\tfor (i = 0; i < 4; i++) {\n+\t\tvalue = 0;\n+\t\tfor (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {\n+\t\t\tacc = accFromQgid(qg_idx + i * ACC_NUM_QGRPS_PER_WORD, conf);\n+\t\t\tvalue |= qman_func_id[acc] << (qg_idx * 4);\n+\t\t}\n+\t\tacc_reg_write(d, VRB2_PfQmgrGrpFunction0 + i * ACC_BYTES_IN_WORD, value);\n+\t}\n+\n+\t/* Configuration of the Arbitration QGroup depth to 1 */\n+\tfor (qg_idx = 0; qg_idx < VRB2_NUM_QGRPS; qg_idx++) {\n+\t\taddress = VRB2_PfQmgrArbQDepthGrp + ACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = 0;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\tstatic_allocation = 1;\n+\tif (static_allocation == 1) {\n+\t\t/* This pointer to ARAM (512kB) is shifted by 2 (4B per register) */\n+\t\tuint32_t aram_address = 0;\n+\t\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\t\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\t\t\taddress = VRB2_PfQmgrVfBaseAddr + vf_idx\n+\t\t\t\t\t\t* ACC_BYTES_IN_WORD + qg_idx\n+\t\t\t\t\t\t* ACC_BYTES_IN_WORD * 64;\n+\t\t\t\tvalue = aram_address;\n+\t\t\t\tacc_reg_fast_write(d, address, value);\n+\t\t\t\t/* Offset ARAM Address for next memory bank - increment of 4B. */\n+\t\t\t\taram_address += aqNum(qg_idx, conf) *\n+\t\t\t\t\t\t(1 << aqDepth(qg_idx, conf));\n+\t\t\t}\n+\t\t}\n+\t\tif (aram_address > VRB2_WORDS_IN_ARAM_SIZE) {\n+\t\t\trte_bbdev_log(ERR, \"ARAM Configuration not fitting %d %d\\n\",\n+\t\t\t\t\taram_address, VRB2_WORDS_IN_ARAM_SIZE);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\t/* Dynamic Qmgr allocation */\n+\t\tacc_reg_write(d, VRB2_PfQmgrAramAllocEn, 1);\n+\t\tacc_reg_write(d, VRB2_PfQmgrAramAllocSetupN0, 0x1000);\n+\t\tacc_reg_write(d, VRB2_PfQmgrAramAllocSetupN1, 0);\n+\t\tacc_reg_write(d, VRB2_PfQmgrAramAllocSetupN2, 0);\n+\t\tacc_reg_write(d, VRB2_PfQmgrAramAllocSetupN3, 0);\n+\t\tacc_reg_write(d, VRB2_PfQmgrSoftReset, 1);\n+\t\tacc_reg_write(d, VRB2_PfQmgrSoftReset, 0);\n+\t}\n+\n+\t/* ==== HI Configuration ==== */\n+\n+\t/* No Info Ring/MSI by default */\n+\taddress = VRB2_PfHiInfoRingIntWrEnRegPf;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\taddress = VRB2_PfHiCfgMsiIntWrEnRegPf;\n+\tvalue = 0xFFFFFFFF;\n+\tacc_reg_write(d, address, value);\n+\t/* Prevent Block on Transmit Error */\n+\taddress = VRB2_PfHiBlockTransmitOnErrorEn;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\t/* Prevents to drop MSI */\n+\taddress = VRB2_PfHiMsiDropEnableReg;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\t/* Set the PF Mode register */\n+\taddress = VRB2_PfHiPfMode;\n+\tvalue = ((conf->pf_mode_en) ? ACC_PF_VAL : 0) | 0x1F07F0;\n+\tacc_reg_write(d, address, value);\n+\t/* Explicitly releasing AXI after PF Mode */\n+\tacc_reg_write(d, VRB2_PfDmaAxiControl, 1);\n+\n+\t/* QoS overflow init */\n+\tvalue = 1;\n+\taddress = VRB2_PfQosmonAEvalOverflow0;\n+\tacc_reg_write(d, address, value);\n+\taddress = VRB2_PfQosmonBEvalOverflow0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Enabling AQueues through the Queue hierarchy*/\n+\tunsigned int en_bitmask[VRB2_AQ_REG_NUM];\n+\tfor (vf_idx = 0; vf_idx < VRB2_NUM_VFS; vf_idx++) {\n+\t\tfor (qg_idx = 0; qg_idx < VRB2_NUM_QGRPS; qg_idx++) {\n+\t\t\tfor (aq_reg = 0; aq_reg < VRB2_AQ_REG_NUM; aq_reg++)\n+\t\t\t\ten_bitmask[aq_reg] = 0;\n+\t\t\tif (vf_idx < conf->num_vf_bundles && qg_idx < totalQgs) {\n+\t\t\t\tfor (aq_reg = 0; aq_reg < VRB2_AQ_REG_NUM; aq_reg++) {\n+\t\t\t\t\tif (aqNum(qg_idx, conf) >= 16 * (aq_reg + 1))\n+\t\t\t\t\t\ten_bitmask[aq_reg] = 0xFFFF;\n+\t\t\t\t\telse if (aqNum(qg_idx, conf) <= 16 * aq_reg)\n+\t\t\t\t\t\ten_bitmask[aq_reg] = 0x0;\n+\t\t\t\t\telse\n+\t\t\t\t\t\ten_bitmask[aq_reg] = (1 << (aqNum(qg_idx,\n+\t\t\t\t\t\t\t\tconf) - aq_reg * 16)) - 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tfor (aq_reg = 0; aq_reg < VRB2_AQ_REG_NUM; aq_reg++) {\n+\t\t\t\taddress = VRB2_PfQmgrAqEnableVf + vf_idx * 16 + aq_reg * 4;\n+\t\t\t\tvalue = (qg_idx << 16) + en_bitmask[aq_reg];\n+\t\t\t\tacc_reg_fast_write(d, address, value);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\trte_bbdev_log(INFO,\n+\t\t\t\"VRB2 basic config complete for %s - pf_bb_config should ideally be used instead\",\n+\t\t\tdev_name);\n+\treturn 0;\n+}\ndiff --git a/drivers/baseband/acc/vrb_cfg.h b/drivers/baseband/acc/vrb_cfg.h\nindex e3c8902b46..79487c4e04 100644\n--- a/drivers/baseband/acc/vrb_cfg.h\n+++ b/drivers/baseband/acc/vrb_cfg.h\n@@ -29,4 +29,20 @@\n int\n vrb1_configure(const char *dev_name, struct rte_acc_conf *conf);\n \n+/**\n+ * Configure a VRB2 device.\n+ *\n+ * @param dev_name\n+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n+ * It can also be retrieved for a bbdev device from the dev_name field in the\n+ * rte_bbdev_info structure returned by rte_bbdev_info_get().\n+ * @param conf\n+ * Configuration to apply to VRB2 HW.\n+ *\n+ * @return\n+ * Zero on success, negative value on failure.\n+ */\n+int\n+vrb2_configure(const char *dev_name, struct rte_acc_conf *conf);\n+\n #endif /* _VRB_CFG_H_ */\n", "prefixes": [ "v1", "7/7" ] }