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{
    "id": 131575,
    "url": "http://patches.dpdk.org/api/patches/131575/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230918163114.276722-2-hernan.vargas@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230918163114.276722-2-hernan.vargas@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230918163114.276722-2-hernan.vargas@intel.com",
    "date": "2023-09-18T16:31:11",
    "name": "[v3,1/4] baseband/fpga_5gnr_fec: renaming for consistency",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "53c0d3ad9263fca7e5c04585e9df08a8887f3a7a",
    "submitter": {
        "id": 2659,
        "url": "http://patches.dpdk.org/api/people/2659/?format=api",
        "name": "Hernan Vargas",
        "email": "hernan.vargas@intel.com"
    },
    "delegate": {
        "id": 2642,
        "url": "http://patches.dpdk.org/api/users/2642/?format=api",
        "username": "mcoquelin",
        "first_name": "Maxime",
        "last_name": "Coquelin",
        "email": "maxime.coquelin@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230918163114.276722-2-hernan.vargas@intel.com/mbox/",
    "series": [
        {
            "id": 29537,
            "url": "http://patches.dpdk.org/api/series/29537/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29537",
            "date": "2023-09-18T16:31:10",
            "name": "changes for 23.11",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/29537/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/131575/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/131575/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695054721; x=1726590721;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=bxy0Zojs2twtA/0FId3LLpG41OgtIoe4O/GnTFgwB6U=;\n b=G5mHEGIljM7j7tdhNtNdzi4zPD1p7Ts6D8QhJQzsTmLw88MoQDY1FwVO\n v5GKkyazoCj728AO4RR68k22SZgeM0P2j9n1APt0OOzf+/DbNbQeOgV4z\n FtVqe0E4gaWn4u1jAD3R2CJ661kuB++Havx5deKgB3Q/SoU+GjzP3fpwO\n XnkSXly4zZ7r6ZMbgoIA3icDEWR/OdqeeGsv9FQ8EcDAP6n2mjhmW9Ora\n yaPHraYxNQQXxO2aK/S2MP3FDkJPbQdNIDY2JsBOXt4Ciz5tGIaBH2Nc2\n G9FPE7k167bEx7lnABtN3dZOVIBaLGLhJ1rPliDyyVYe5m8JQmfnFYXAs Q==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10837\"; a=\"382451785\"",
            "E=Sophos;i=\"6.02,156,1688454000\"; d=\"scan'208\";a=\"382451785\"",
            "E=McAfee;i=\"6600,9927,10837\"; a=\"1076645883\"",
            "E=Sophos;i=\"6.02,156,1688454000\"; d=\"scan'208\";a=\"1076645883\""
        ],
        "X-ExtLoop1": "1",
        "From": "Hernan Vargas <hernan.vargas@intel.com>",
        "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com",
        "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>",
        "Subject": "[PATCH v3 1/4] baseband/fpga_5gnr_fec: renaming for consistency",
        "Date": "Mon, 18 Sep 2023 09:31:11 -0700",
        "Message-Id": "<20230918163114.276722-2-hernan.vargas@intel.com>",
        "X-Mailer": "git-send-email 2.37.1",
        "In-Reply-To": "<20230918163114.276722-1-hernan.vargas@intel.com>",
        "References": "<20230918163114.276722-1-hernan.vargas@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Rename generic functions and constants using the FPGA 5GNR prefix naming\nto prepare for code reuse for new FPGA implementation variant.\nNo functional impact.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h    | 117 +++--\n .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c         | 455 ++++++++----------\n .../fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h     |  17 +-\n 3 files changed, 269 insertions(+), 320 deletions(-)",
    "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex e3038112fabb..9300349a731b 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -31,26 +31,26 @@\n #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)\n \n /* Align DMA descriptors to 256 bytes - cache-aligned */\n-#define FPGA_RING_DESC_ENTRY_LENGTH (8)\n+#define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8)\n /* Ring size is in 256 bits (32 bytes) units */\n #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)\n /* Maximum size of queue */\n-#define FPGA_RING_MAX_SIZE (1024)\n+#define FPGA_5GNR_RING_MAX_SIZE (1024)\n \n #define FPGA_NUM_UL_QUEUES (32)\n #define FPGA_NUM_DL_QUEUES (32)\n #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)\n #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)\n \n-#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)\n+#define FPGA_5GNR_INVALID_HW_QUEUE_ID (0xFFFFFFFF)\n \n-#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)\n-#define FPGA_HARQ_RDY_TIMEOUT (10)\n-#define FPGA_TIMEOUT_CHECK_INTERVAL (5)\n-#define FPGA_DDR_OVERFLOW (0x10)\n+#define FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US (1000)\n+#define FPGA_5GNR_HARQ_RDY_TIMEOUT (10)\n+#define FPGA_5GNR_TIMEOUT_CHECK_INTERVAL (5)\n+#define FPGA_5GNR_DDR_OVERFLOW (0x10)\n \n-#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8\n-#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8\n+#define FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES 8\n+#define FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES 8\n \n /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */\n #define N_ZC_1 66 /* N = 66 Zc for BG 1 */\n@@ -152,7 +152,7 @@ struct __rte_packed fpga_dma_enc_desc {\n \t\t};\n \n \t\tuint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *\n-\t\t\t\t\t(FPGA_RING_DESC_ENTRY_LENGTH - 1)];\n+\t\t\t\t\t(FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n \t};\n };\n \n@@ -197,7 +197,7 @@ struct __rte_packed fpga_dma_dec_desc {\n \t\t\tuint8_t cbs_in_op;\n \t\t};\n \n-\t\tuint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];\n+\t\tuint32_t sw_ctxt[8 * (FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n \t};\n };\n \n@@ -207,8 +207,8 @@ union fpga_dma_desc {\n \tstruct fpga_dma_dec_desc dec_req;\n };\n \n-/* FPGA 5GNR FEC Ring Control Register */\n-struct __rte_packed fpga_ring_ctrl_reg {\n+/* FPGA 5GNR Ring Control Register. */\n+struct __rte_packed fpga_5gnr_ring_ctrl_reg {\n \tuint64_t ring_base_addr;\n \tuint64_t ring_head_addr;\n \tuint16_t ring_size:11;\n@@ -226,38 +226,37 @@ struct __rte_packed fpga_ring_ctrl_reg {\n \tuint16_t rsrvd3;\n \tuint16_t head_point;\n \tuint16_t rsrvd4;\n-\n };\n \n-/* Private data structure for each FPGA FEC device */\n+/* Private data structure for each FPGA 5GNR device. */\n struct fpga_5gnr_fec_device {\n-\t/** Base address of MMIO registers (BAR0) */\n+\t/** Base address of MMIO registers (BAR0). */\n \tvoid *mmio_base;\n-\t/** Base address of memory for sw rings */\n+\t/** Base address of memory for sw rings. */\n \tvoid *sw_rings;\n-\t/** Physical address of sw_rings */\n+\t/** Physical address of sw_rings. */\n \trte_iova_t sw_rings_phys;\n \t/** Number of bytes available for each queue in device. */\n \tuint32_t sw_ring_size;\n-\t/** Max number of entries available for each queue in device */\n+\t/** Max number of entries available for each queue in device. */\n \tuint32_t sw_ring_max_depth;\n-\t/** Base address of response tail pointer buffer */\n+\t/** Base address of response tail pointer buffer. */\n \tuint32_t *tail_ptrs;\n-\t/** Physical address of tail pointers */\n+\t/** Physical address of tail pointers. */\n \trte_iova_t tail_ptr_phys;\n-\t/** Queues flush completion flag */\n+\t/** Queues flush completion flag. */\n \tuint64_t *flush_queue_status;\n-\t/* Bitmap capturing which Queues are bound to the PF/VF */\n+\t/** Bitmap capturing which Queues are bound to the PF/VF. */\n \tuint64_t q_bound_bit_map;\n-\t/* Bitmap capturing which Queues have already been assigned */\n+\t/** Bitmap capturing which Queues have already been assigned. */\n \tuint64_t q_assigned_bit_map;\n-\t/** True if this is a PF FPGA FEC device */\n+\t/** True if this is a PF FPGA 5GNR device. */\n \tbool pf_device;\n };\n \n-/* Structure associated with each queue. */\n-struct __rte_cache_aligned fpga_queue {\n-\tstruct fpga_ring_ctrl_reg ring_ctrl_reg;  /* Ring Control Register */\n+/** Structure associated with each queue. */\n+struct __rte_cache_aligned fpga_5gnr_queue {\n+\tstruct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg;  /**< Ring Control Register */\n \tunion fpga_dma_desc *ring_addr;  /* Virtual address of software ring */\n \tuint64_t *ring_head_addr;  /* Virtual address of completion_head */\n \tuint64_t shadow_completion_head; /* Shadow completion head value */\n@@ -274,84 +273,80 @@ struct __rte_cache_aligned fpga_queue {\n \tvoid *shadow_tail_addr;\n };\n \n-/* Write to 16 bit MMIO register address */\n+/* Write to 16 bit MMIO register address. */\n static inline void\n mmio_write_16(void *addr, uint16_t value)\n {\n \t*((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);\n }\n \n-/* Write to 32 bit MMIO register address */\n+/* Write to 32 bit MMIO register address. */\n static inline void\n mmio_write_32(void *addr, uint32_t value)\n {\n \t*((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);\n }\n \n-/* Write to 64 bit MMIO register address */\n+/* Write to 64 bit MMIO register address. */\n static inline void\n mmio_write_64(void *addr, uint64_t value)\n {\n \t*((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);\n }\n \n-/* Write a 8 bit register of a FPGA 5GNR FEC device */\n+/* Write a 8 bit register of a FPGA 5GNR device. */\n static inline void\n-fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)\n+fpga_5gnr_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \t*((volatile uint8_t *)(reg_addr)) = payload;\n }\n \n-/* Write a 16 bit register of a FPGA 5GNR FEC device */\n+/* Write a 16 bit register of a FPGA 5GNR device. */\n static inline void\n-fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)\n+fpga_5gnr_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tmmio_write_16(reg_addr, payload);\n }\n \n-/* Write a 32 bit register of a FPGA 5GNR FEC device */\n+/* Write a 32 bit register of a FPGA 5GNR device. */\n static inline void\n-fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)\n+fpga_5gnr_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tmmio_write_32(reg_addr, payload);\n }\n \n-/* Write a 64 bit register of a FPGA 5GNR FEC device */\n+/* Write a 64 bit register of a FPGA 5GNR device. */\n static inline void\n-fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)\n+fpga_5gnr_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tmmio_write_64(reg_addr, payload);\n }\n \n-/* Write a ring control register of a FPGA 5GNR FEC device */\n+/* Write a ring control register of a FPGA 5GNR device. */\n static inline void\n-fpga_ring_reg_write(void *mmio_base, uint32_t offset,\n-\t\tstruct fpga_ring_ctrl_reg payload)\n+fpga_ring_reg_write(void *mmio_base, uint32_t offset, struct fpga_5gnr_ring_ctrl_reg payload)\n {\n-\tfpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);\n-\tfpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,\n+\tfpga_5gnr_reg_write_64(mmio_base, offset, payload.ring_base_addr);\n+\tfpga_5gnr_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,\n \t\t\tpayload.ring_head_addr);\n-\tfpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE,\n-\t\t\tpayload.ring_size);\n-\tfpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,\n+\tfpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE, payload.ring_size);\n+\tfpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,\n \t\t\tpayload.head_point);\n-\tfpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,\n+\tfpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,\n \t\t\tpayload.flush_queue_en);\n-\tfpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,\n+\tfpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,\n \t\t\tpayload.shadow_tail);\n-\tfpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC,\n-\t\t\tpayload.misc);\n-\tfpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,\n-\t\t\tpayload.enable);\n+\tfpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC, payload.misc);\n+\tfpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload.enable);\n }\n \n-/* Read a register of FPGA 5GNR FEC device */\n+/* Read a register of FPGA 5GNR device. */\n static inline uint32_t\n-fpga_reg_read_32(void *mmio_base, uint32_t offset)\n+fpga_5gnr_reg_read_32(void *mmio_base, uint32_t offset)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tuint32_t ret = *((volatile uint32_t *)(reg_addr));\n@@ -360,9 +355,9 @@ fpga_reg_read_32(void *mmio_base, uint32_t offset)\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \n-/* Read a register of FPGA 5GNR FEC device */\n+/* Read a register of FPGA 5GNR device. */\n static inline uint16_t\n-fpga_reg_read_16(void *mmio_base, uint32_t offset)\n+fpga_5gnr_reg_read_16(void *mmio_base, uint32_t offset)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tuint16_t ret = *((volatile uint16_t *)(reg_addr));\n@@ -371,17 +366,17 @@ fpga_reg_read_16(void *mmio_base, uint32_t offset)\n \n #endif\n \n-/* Read a register of FPGA 5GNR FEC device */\n+/* Read a register of FPGA 5GNR device. */\n static inline uint8_t\n-fpga_reg_read_8(void *mmio_base, uint32_t offset)\n+fpga_5gnr_reg_read_8(void *mmio_base, uint32_t offset)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \treturn *((volatile uint8_t *)(reg_addr));\n }\n \n-/* Read a register of FPGA 5GNR FEC device */\n+/* Read a register of FPGA 5GNR device. */\n static inline uint64_t\n-fpga_reg_read_64(void *mmio_base, uint32_t offset)\n+fpga_5gnr_reg_read_64(void *mmio_base, uint32_t offset)\n {\n \tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n \tuint64_t ret = *((volatile uint64_t *)(reg_addr));\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 6b0644ffc5d6..5fbe913ddbe2 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -34,38 +34,38 @@ static inline void\n print_ring_reg_debug_info(void *mmio_base, uint32_t offset)\n {\n \trte_bbdev_log_debug(\n-\t\t\"FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08\"\n+\t\t\"FPGA 5GNR MMIO base address @ %p | Ring Control Register @ offset = 0x%08\"\n \t\tPRIx32, mmio_base, offset);\n \trte_bbdev_log_debug(\n \t\t\"RING_BASE_ADDR = 0x%016\"PRIx64,\n-\t\tfpga_reg_read_64(mmio_base, offset));\n+\t\tfpga_5gnr_reg_read_64(mmio_base, offset));\n \trte_bbdev_log_debug(\n \t\t\"RING_HEAD_ADDR = 0x%016\"PRIx64,\n-\t\tfpga_reg_read_64(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_64(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_HEAD_ADDR));\n \trte_bbdev_log_debug(\n \t\t\"RING_SIZE = 0x%04\"PRIx16,\n-\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_16(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_SIZE));\n \trte_bbdev_log_debug(\n \t\t\"RING_MISC = 0x%02\"PRIx8,\n-\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_8(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_MISC));\n \trte_bbdev_log_debug(\n \t\t\"RING_ENABLE = 0x%02\"PRIx8,\n-\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_8(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_ENABLE));\n \trte_bbdev_log_debug(\n \t\t\"RING_FLUSH_QUEUE_EN = 0x%02\"PRIx8,\n-\t\tfpga_reg_read_8(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_8(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));\n \trte_bbdev_log_debug(\n \t\t\"RING_SHADOW_TAIL = 0x%04\"PRIx16,\n-\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_16(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_SHADOW_TAIL));\n \trte_bbdev_log_debug(\n \t\t\"RING_HEAD_POINT = 0x%04\"PRIx16,\n-\t\tfpga_reg_read_16(mmio_base, offset +\n+\t\tfpga_5gnr_reg_read_16(mmio_base, offset +\n \t\t\t\tFPGA_5GNR_FEC_RING_HEAD_POINT));\n }\n \n@@ -73,13 +73,13 @@ print_ring_reg_debug_info(void *mmio_base, uint32_t offset)\n static inline void\n print_static_reg_debug_info(void *mmio_base)\n {\n-\tuint16_t config = fpga_reg_read_16(mmio_base,\n+\tuint16_t config = fpga_5gnr_reg_read_16(mmio_base,\n \t\t\tFPGA_5GNR_FEC_CONFIGURATION);\n-\tuint8_t qmap_done = fpga_reg_read_8(mmio_base,\n+\tuint8_t qmap_done = fpga_5gnr_reg_read_8(mmio_base,\n \t\t\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);\n-\tuint16_t lb_factor = fpga_reg_read_16(mmio_base,\n+\tuint16_t lb_factor = fpga_5gnr_reg_read_16(mmio_base,\n \t\t\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);\n-\tuint16_t ring_desc_len = fpga_reg_read_16(mmio_base,\n+\tuint16_t ring_desc_len = fpga_5gnr_reg_read_16(mmio_base,\n \t\t\tFPGA_5GNR_FEC_RING_DESC_LEN);\n \n \trte_bbdev_log_debug(\"UL.DL Weights = %u.%u\",\n@@ -179,17 +179,17 @@ print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)\n #endif\n \n static int\n-fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n+fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n {\n \t/* Number of queues bound to a PF/VF */\n \tuint32_t hw_q_num = 0;\n \tuint32_t ring_size, payload, address, q_id, offset;\n \trte_iova_t phys_addr;\n-\tstruct fpga_ring_ctrl_reg ring_reg;\n-\tstruct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;\n+\tstruct fpga_5gnr_ring_ctrl_reg ring_reg;\n+\tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n \n \taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n-\tif (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {\n+\tif (!(fpga_5gnr_reg_read_32(d->mmio_base, address) & 0x1)) {\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?\",\n \t\t\t\tdev->data->name);\n@@ -197,26 +197,26 @@ fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \t}\n \n \t/* Clear queue registers structure */\n-\tmemset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));\n+\tmemset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg));\n \n \t/* Scan queue map.\n \t * If a queue is valid and mapped to a calling PF/VF the read value is\n \t * replaced with a queue ID and if it's not then\n-\t * FPGA_INVALID_HW_QUEUE_ID is returned.\n+\t * FPGA_5GNR_INVALID_HW_QUEUE_ID is returned.\n \t */\n \tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n-\t\tuint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,\n+\t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));\n \n \t\trte_bbdev_log_debug(\"%s: queue ID: %u, registry queue ID: %u\",\n \t\t\t\tdev->device->name, q_id, hw_q_id);\n \n-\t\tif (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {\n-\t\t\tfpga_dev->q_bound_bit_map |= (1ULL << q_id);\n+\t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) {\n+\t\t\td->q_bound_bit_map |= (1ULL << q_id);\n \t\t\t/* Clear queue register of found queue */\n \t\t\toffset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n-\t\t\t\t(sizeof(struct fpga_ring_ctrl_reg) * q_id);\n-\t\t\tfpga_ring_reg_write(fpga_dev->mmio_base,\n+\t\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_id);\n+\t\t\tfpga_ring_reg_write(d->mmio_base,\n \t\t\t\t\toffset, ring_reg);\n \t\t\t++hw_q_num;\n \t\t}\n@@ -234,30 +234,30 @@ fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \t\treturn -EINVAL;\n \t}\n \n-\tring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);\n+\tring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);\n \n \t/* Enforce 32 byte alignment */\n \tRTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);\n \n \t/* Allocate memory for SW descriptor rings */\n-\tfpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,\n+\td->sw_rings = rte_zmalloc_socket(dev->device->driver->name,\n \t\t\tnum_queues * ring_size, RTE_CACHE_LINE_SIZE,\n \t\t\tsocket_id);\n-\tif (fpga_dev->sw_rings == NULL) {\n+\tif (d->sw_rings == NULL) {\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Failed to allocate memory for %s:%u sw_rings\",\n \t\t\t\tdev->device->driver->name, dev->data->dev_id);\n \t\treturn -ENOMEM;\n \t}\n \n-\tfpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);\n-\tfpga_dev->sw_ring_size = ring_size;\n-\tfpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;\n+\td->sw_rings_phys = rte_malloc_virt2iova(d->sw_rings);\n+\td->sw_ring_size = ring_size;\n+\td->sw_ring_max_depth = FPGA_5GNR_RING_MAX_SIZE;\n \n \t/* Allocate memory for ring flush status */\n-\tfpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,\n+\td->flush_queue_status = rte_zmalloc_socket(NULL,\n \t\t\tsizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);\n-\tif (fpga_dev->flush_queue_status == NULL) {\n+\tif (d->flush_queue_status == NULL) {\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Failed to allocate memory for %s:%u flush_queue_status\",\n \t\t\t\tdev->device->driver->name, dev->data->dev_id);\n@@ -265,33 +265,32 @@ fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \t}\n \n \t/* Set the flush status address registers */\n-\tphys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);\n+\tphys_addr = rte_malloc_virt2iova(d->flush_queue_status);\n \n \taddress = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW;\n \tpayload = (uint32_t)(phys_addr);\n-\tfpga_reg_write_32(fpga_dev->mmio_base, address, payload);\n+\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload);\n \n \taddress = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI;\n \tpayload = (uint32_t)(phys_addr >> 32);\n-\tfpga_reg_write_32(fpga_dev->mmio_base, address, payload);\n+\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload);\n \n \treturn 0;\n }\n \n static int\n-fpga_dev_close(struct rte_bbdev *dev)\n+fpga_5gnr_dev_close(struct rte_bbdev *dev)\n {\n-\tstruct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;\n+\tstruct fpga_5gnr_fec_device *fpga_5gnr_dev = dev->data->dev_private;\n \n-\trte_free(fpga_dev->sw_rings);\n-\trte_free(fpga_dev->flush_queue_status);\n+\trte_free(fpga_5gnr_dev->sw_rings);\n+\trte_free(fpga_5gnr_dev->flush_queue_status);\n \n \treturn 0;\n }\n \n static void\n-fpga_dev_info_get(struct rte_bbdev *dev,\n-\t\tstruct rte_bbdev_driver_info *dev_info)\n+fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n {\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n \tuint32_t q_id = 0;\n@@ -338,28 +337,27 @@ fpga_dev_info_get(struct rte_bbdev *dev,\n \n \t/* Check the HARQ DDR size available */\n \tuint8_t timeout_counter = 0;\n-\tuint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base,\n+\tuint32_t harq_buf_ready = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);\n \twhile (harq_buf_ready != 1) {\n-\t\tusleep(FPGA_TIMEOUT_CHECK_INTERVAL);\n+\t\tusleep(FPGA_5GNR_TIMEOUT_CHECK_INTERVAL);\n \t\ttimeout_counter++;\n-\t\tharq_buf_ready = fpga_reg_read_32(d->mmio_base,\n+\t\tharq_buf_ready = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);\n-\t\tif (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) {\n-\t\t\trte_bbdev_log(ERR, \"HARQ Buffer not ready %d\",\n-\t\t\t\t\tharq_buf_ready);\n+\t\tif (timeout_counter > FPGA_5GNR_HARQ_RDY_TIMEOUT) {\n+\t\t\trte_bbdev_log(ERR, \"HARQ Buffer not ready %d\", harq_buf_ready);\n \t\t\tharq_buf_ready = 1;\n \t\t}\n \t}\n-\tuint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base,\n+\tuint32_t harq_buf_size = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n \n \tstatic struct rte_bbdev_queue_conf default_queue_conf;\n \tdefault_queue_conf.socket = dev->data->socket_id;\n-\tdefault_queue_conf.queue_size = FPGA_RING_MAX_SIZE;\n+\tdefault_queue_conf.queue_size = FPGA_5GNR_RING_MAX_SIZE;\n \n \tdev_info->driver_name = dev->device->driver->name;\n-\tdev_info->queue_size_lim = FPGA_RING_MAX_SIZE;\n+\tdev_info->queue_size_lim = FPGA_5GNR_RING_MAX_SIZE;\n \tdev_info->hardware_accelerated = true;\n \tdev_info->min_alignment = 64;\n \tdev_info->harq_buffer_size = (harq_buf_size >> 10) + 1;\n@@ -372,9 +370,9 @@ fpga_dev_info_get(struct rte_bbdev *dev,\n \t/* Calculates number of queues assigned to device */\n \tdev_info->max_num_queues = 0;\n \tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n-\t\tuint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,\n+\t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));\n-\t\tif (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)\n+\t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID)\n \t\t\tdev_info->max_num_queues++;\n \t}\n \t/* Expose number of queue per operation type */\n@@ -392,7 +390,7 @@ fpga_dev_info_get(struct rte_bbdev *dev,\n  * when there is no available queue\n  */\n static inline int\n-fpga_find_free_queue_idx(struct rte_bbdev *dev,\n+fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev,\n \t\tconst struct rte_bbdev_queue_conf *conf)\n {\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n@@ -422,16 +420,16 @@ fpga_find_free_queue_idx(struct rte_bbdev *dev,\n }\n \n static int\n-fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n+fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t\tconst struct rte_bbdev_queue_conf *conf)\n {\n \tuint32_t address, ring_offset;\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n-\tstruct fpga_queue *q;\n+\tstruct fpga_5gnr_queue *q;\n \tint8_t q_idx;\n \n \t/* Check if there is a free queue to assign */\n-\tq_idx = fpga_find_free_queue_idx(dev, conf);\n+\tq_idx = fpga_5gnr_find_free_queue_idx(dev, conf);\n \tif (q_idx == -1)\n \t\treturn -1;\n \n@@ -450,8 +448,7 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \n \t/* Set ring_base_addr */\n \tq->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));\n-\tq->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +\n-\t\t\t(d->sw_ring_size * queue_id);\n+\tq->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + (d->sw_ring_size * queue_id);\n \n \t/* Allocate memory for Completion Head variable*/\n \tq->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,\n@@ -466,27 +463,26 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t\treturn -ENOMEM;\n \t}\n \t/* Set ring_head_addr */\n-\tq->ring_ctrl_reg.ring_head_addr =\n-\t\t\trte_malloc_virt2iova(q->ring_head_addr);\n+\tq->ring_ctrl_reg.ring_head_addr = rte_malloc_virt2iova(q->ring_head_addr);\n \n \t/* Clear shadow_completion_head */\n \tq->shadow_completion_head = 0;\n \n \t/* Set ring_size */\n-\tif (conf->queue_size > FPGA_RING_MAX_SIZE) {\n+\tif (conf->queue_size > FPGA_5GNR_RING_MAX_SIZE) {\n \t\t/* Mark queue as un-assigned */\n \t\td->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));\n \t\trte_free(q->ring_head_addr);\n \t\trte_free(q);\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Size of queue is too big %d (MAX: %d ) for %s:%u\",\n-\t\t\t\tconf->queue_size, FPGA_RING_MAX_SIZE,\n+\t\t\t\tconf->queue_size, FPGA_5GNR_RING_MAX_SIZE,\n \t\t\t\tdev->device->driver->name, dev->data->dev_id);\n \t\treturn -EINVAL;\n \t}\n \tq->ring_ctrl_reg.ring_size = conf->queue_size;\n \n-\t/* Set Miscellaneous FPGA register*/\n+\t/* Set Miscellaneous FPGA 5GNR register. */\n \t/* Max iteration number for TTI mitigation - todo */\n \tq->ring_ctrl_reg.max_ul_dec = 0;\n \t/* Enable max iteration number for TTI - todo */\n@@ -495,17 +491,17 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t/* Enable the ring */\n \tq->ring_ctrl_reg.enable = 1;\n \n-\t/* Set FPGA head_point and tail registers */\n+\t/* Set FPGA 5GNR head_point and tail registers */\n \tq->ring_ctrl_reg.head_point = q->tail = 0;\n \n-\t/* Set FPGA shadow_tail register */\n+\t/* Set FPGA 5GNR shadow_tail register */\n \tq->ring_ctrl_reg.shadow_tail = q->tail;\n \n \t/* Calculates the ring offset for found queue */\n \tring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n-\t\t\t(sizeof(struct fpga_ring_ctrl_reg) * q_idx);\n+\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_idx);\n \n-\t/* Set FPGA Ring Control Registers */\n+\t/* Set FPGA 5GNR Ring Control Registers */\n \tfpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);\n \n \t/* Store MMIO register of shadow_tail */\n@@ -522,8 +518,7 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \n \tdev->data->queues[queue_id].queue_private = q;\n \n-\trte_bbdev_log_debug(\"BBDEV queue[%d] set up for FPGA queue[%d]\",\n-\t\t\tqueue_id, q_idx);\n+\trte_bbdev_log_debug(\"BBDEV queue[%d] set up for FPGA 5GNR queue[%d]\", queue_id, q_idx);\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \t/* Read FPGA Ring Control Registers after configuration*/\n@@ -533,21 +528,21 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n }\n \n static int\n-fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)\n+fpga_5gnr_queue_release(struct rte_bbdev *dev, uint16_t queue_id)\n {\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n-\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n-\tstruct fpga_ring_ctrl_reg ring_reg;\n+\tstruct fpga_5gnr_queue *q = dev->data->queues[queue_id].queue_private;\n+\tstruct fpga_5gnr_ring_ctrl_reg ring_reg;\n \tuint32_t offset;\n \n-\trte_bbdev_log_debug(\"FPGA Queue[%d] released\", queue_id);\n+\trte_bbdev_log_debug(\"FPGA 5GNR Queue[%d] released\", queue_id);\n \n \tif (q != NULL) {\n-\t\tmemset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));\n+\t\tmemset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg));\n \t\toffset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n-\t\t\t(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);\n+\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q->q_idx);\n \t\t/* Disable queue */\n-\t\tfpga_reg_write_8(d->mmio_base,\n+\t\tfpga_5gnr_reg_write_8(d->mmio_base,\n \t\t\t\toffset + FPGA_5GNR_FEC_RING_ENABLE, 0x00);\n \t\t/* Clear queue registers */\n \t\tfpga_ring_reg_write(d->mmio_base, offset, ring_reg);\n@@ -564,12 +559,12 @@ fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)\n \n /* Function starts a device queue. */\n static int\n-fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)\n+fpga_5gnr_queue_start(struct rte_bbdev *dev, uint16_t queue_id)\n {\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n-\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\tstruct fpga_5gnr_queue *q = dev->data->queues[queue_id].queue_private;\n \tuint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n-\t\t\t(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);\n+\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q->q_idx);\n \tuint8_t enable = 0x01;\n \tuint16_t zero = 0x0000;\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n@@ -586,23 +581,20 @@ fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)\n \t/* Clear queue head and tail variables */\n \tq->tail = q->head_free_desc = 0;\n \n-\t/* Clear FPGA head_point and tail registers */\n-\tfpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,\n-\t\t\tzero);\n-\tfpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,\n-\t\t\tzero);\n+\t/* Clear FPGA 5GNR head_point and tail registers */\n+\tfpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, zero);\n+\tfpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, zero);\n \n \t/* Enable queue */\n-\tfpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,\n-\t\t\tenable);\n+\tfpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, enable);\n \n-\trte_bbdev_log_debug(\"FPGA Queue[%d] started\", queue_id);\n+\trte_bbdev_log_debug(\"FPGA 5GNR Queue[%d] started\", queue_id);\n \treturn 0;\n }\n \n /* Function stops a device queue. */\n static int\n-fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n+fpga_5gnr_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n {\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n@@ -611,40 +603,36 @@ fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n \t\treturn -1;\n \t}\n #endif\n-\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\tstruct fpga_5gnr_queue *q = dev->data->queues[queue_id].queue_private;\n \tuint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n-\t\t\t(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);\n+\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q->q_idx);\n \tuint8_t payload = 0x01;\n \tuint8_t counter = 0;\n-\tuint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /\n-\t\t\tFPGA_TIMEOUT_CHECK_INTERVAL;\n+\tuint8_t timeout = FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US / FPGA_5GNR_TIMEOUT_CHECK_INTERVAL;\n \n \t/* Set flush_queue_en bit to trigger queue flushing */\n-\tfpga_reg_write_8(d->mmio_base,\n+\tfpga_5gnr_reg_write_8(d->mmio_base,\n \t\t\toffset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload);\n \n \t/** Check if queue flush is completed.\n-\t * FPGA will update the completion flag after queue flushing is\n+\t * FPGA 5GNR will update the completion flag after queue flushing is\n \t * completed. If completion flag is not updated within 1ms it is\n \t * considered as a failure.\n \t */\n-\twhile (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx)\n-\t\t\t& payload)) {\n+\twhile (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {\n \t\tif (counter > timeout) {\n-\t\t\trte_bbdev_log(ERR, \"FPGA Queue Flush failed for queue %d\",\n-\t\t\t\t\tqueue_id);\n+\t\t\trte_bbdev_log(ERR, \"FPGA 5GNR Queue Flush failed for queue %d\", queue_id);\n \t\t\treturn -1;\n \t\t}\n-\t\tusleep(FPGA_TIMEOUT_CHECK_INTERVAL);\n+\t\tusleep(FPGA_5GNR_TIMEOUT_CHECK_INTERVAL);\n \t\tcounter++;\n \t}\n \n \t/* Disable queue */\n \tpayload = 0x00;\n-\tfpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,\n-\t\t\tpayload);\n+\tfpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload);\n \n-\trte_bbdev_log_debug(\"FPGA Queue[%d] stopped\", queue_id);\n+\trte_bbdev_log_debug(\"FPGA 5GNR Queue[%d] stopped\", queue_id);\n \treturn 0;\n }\n \n@@ -654,7 +642,7 @@ get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)\n \tuint16_t queue_id;\n \n \tfor (queue_id = 0; queue_id < data->num_queues; ++queue_id) {\n-\t\tstruct fpga_queue *q = data->queues[queue_id].queue_private;\n+\t\tstruct fpga_5gnr_queue *q = data->queues[queue_id].queue_private;\n \t\tif (q != NULL && q->q_idx == q_idx)\n \t\t\treturn queue_id;\n \t}\n@@ -662,13 +650,13 @@ get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)\n \treturn -1;\n }\n \n-/* Interrupt handler triggered by FPGA dev for handling specific interrupt */\n+/* Interrupt handler triggered by FPGA 5GNR dev for handling specific interrupt. */\n static void\n-fpga_dev_interrupt_handler(void *cb_arg)\n+fpga_5gnr_dev_interrupt_handler(void *cb_arg)\n {\n \tstruct rte_bbdev *dev = cb_arg;\n-\tstruct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;\n-\tstruct fpga_queue *q;\n+\tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n+\tstruct fpga_5gnr_queue *q;\n \tuint64_t ring_head;\n \tuint64_t q_idx;\n \tuint16_t queue_id;\n@@ -677,7 +665,7 @@ fpga_dev_interrupt_handler(void *cb_arg)\n \t/* Scan queue assigned to this device */\n \tfor (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {\n \t\tq_idx = 1ULL << i;\n-\t\tif (fpga_dev->q_bound_bit_map & q_idx) {\n+\t\tif (d->q_bound_bit_map & q_idx) {\n \t\t\tqueue_id = get_queue_id(dev->data, i);\n \t\t\tif (queue_id == (uint16_t) -1)\n \t\t\t\tcontinue;\n@@ -698,9 +686,9 @@ fpga_dev_interrupt_handler(void *cb_arg)\n }\n \n static int\n-fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)\n+fpga_5gnr_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)\n {\n-\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\tstruct fpga_5gnr_queue *q = dev->data->queues[queue_id].queue_private;\n \n \tif (!rte_intr_cap_multiple(dev->intr_handle))\n \t\treturn -ENOTSUP;\n@@ -711,16 +699,16 @@ fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)\n }\n \n static int\n-fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)\n+fpga_5gnr_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)\n {\n-\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\tstruct fpga_5gnr_queue *q = dev->data->queues[queue_id].queue_private;\n \tq->irq_enable = 0;\n \n \treturn 0;\n }\n \n static int\n-fpga_intr_enable(struct rte_bbdev *dev)\n+fpga_5gnr_intr_enable(struct rte_bbdev *dev)\n {\n \tint ret;\n \tuint8_t i;\n@@ -771,8 +759,7 @@ fpga_intr_enable(struct rte_bbdev *dev)\n \t\treturn ret;\n \t}\n \n-\tret = rte_intr_callback_register(dev->intr_handle,\n-\t\t\tfpga_dev_interrupt_handler, dev);\n+\tret = rte_intr_callback_register(dev->intr_handle, fpga_5gnr_dev_interrupt_handler, dev);\n \tif (ret < 0) {\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Couldn't register interrupt callback for device: %s\",\n@@ -783,21 +770,21 @@ fpga_intr_enable(struct rte_bbdev *dev)\n \treturn 0;\n }\n \n-static const struct rte_bbdev_ops fpga_ops = {\n-\t.setup_queues = fpga_setup_queues,\n-\t.intr_enable = fpga_intr_enable,\n-\t.close = fpga_dev_close,\n-\t.info_get = fpga_dev_info_get,\n-\t.queue_setup = fpga_queue_setup,\n-\t.queue_stop = fpga_queue_stop,\n-\t.queue_start = fpga_queue_start,\n-\t.queue_release = fpga_queue_release,\n-\t.queue_intr_enable = fpga_queue_intr_enable,\n-\t.queue_intr_disable = fpga_queue_intr_disable\n+static const struct rte_bbdev_ops fpga_5gnr_ops = {\n+\t.setup_queues = fpga_5gnr_setup_queues,\n+\t.intr_enable = fpga_5gnr_intr_enable,\n+\t.close = fpga_5gnr_dev_close,\n+\t.info_get = fpga_5gnr_dev_info_get,\n+\t.queue_setup = fpga_5gnr_queue_setup,\n+\t.queue_stop = fpga_5gnr_queue_stop,\n+\t.queue_start = fpga_5gnr_queue_start,\n+\t.queue_release = fpga_5gnr_queue_release,\n+\t.queue_intr_enable = fpga_5gnr_queue_intr_enable,\n+\t.queue_intr_disable = fpga_5gnr_queue_intr_disable\n };\n \n static inline void\n-fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,\n+fpga_5gnr_dma_enqueue(struct fpga_5gnr_queue *q, uint16_t num_desc,\n \t\tstruct rte_bbdev_stats *queue_stats)\n {\n \tuint64_t start_time = 0;\n@@ -1488,7 +1475,7 @@ mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)\n }\n \n static inline void\n-fpga_mutex_acquisition(struct fpga_queue *q)\n+fpga_5gnr_mutex_acquisition(struct fpga_5gnr_queue *q)\n {\n \tuint32_t mutex_ctrl, mutex_read, cnt = 0;\n \t/* Assign a unique id for the duration of the DDR access */\n@@ -1497,14 +1484,10 @@ fpga_mutex_acquisition(struct fpga_queue *q)\n \tmutex_ctrl = (q->ddr_mutex_uuid << 16) + 1;\n \tdo {\n \t\tif (cnt > 0)\n-\t\t\tusleep(FPGA_TIMEOUT_CHECK_INTERVAL);\n-\t\trte_bbdev_log_debug(\"Acquiring Mutex for %x\\n\",\n-\t\t\t\tq->ddr_mutex_uuid);\n-\t\tfpga_reg_write_32(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_MUTEX,\n-\t\t\t\tmutex_ctrl);\n-\t\tmutex_read = fpga_reg_read_32(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_MUTEX);\n+\t\t\tusleep(FPGA_5GNR_TIMEOUT_CHECK_INTERVAL);\n+\t\trte_bbdev_log_debug(\"Acquiring Mutex for %x\\n\", q->ddr_mutex_uuid);\n+\t\tfpga_5gnr_reg_write_32(q->d->mmio_base, FPGA_5GNR_FEC_MUTEX, mutex_ctrl);\n+\t\tmutex_read = fpga_5gnr_reg_read_32(q->d->mmio_base, FPGA_5GNR_FEC_MUTEX);\n \t\trte_bbdev_log_debug(\"Mutex %x cnt %d owner %x\\n\",\n \t\t\t\tmutex_read, cnt, q->ddr_mutex_uuid);\n \t\tcnt++;\n@@ -1512,27 +1495,24 @@ fpga_mutex_acquisition(struct fpga_queue *q)\n }\n \n static inline void\n-fpga_mutex_free(struct fpga_queue *q)\n+fpga_5gnr_mutex_free(struct fpga_5gnr_queue *q)\n {\n \tuint32_t mutex_ctrl = q->ddr_mutex_uuid << 16;\n-\tfpga_reg_write_32(q->d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_MUTEX,\n-\t\t\tmutex_ctrl);\n+\tfpga_5gnr_reg_write_32(q->d->mmio_base, FPGA_5GNR_FEC_MUTEX, mutex_ctrl);\n }\n \n static inline int\n-fpga_harq_write_loopback(struct fpga_queue *q,\n+fpga_5gnr_harq_write_loopback(struct fpga_5gnr_queue *q,\n \t\tstruct rte_mbuf *harq_input, uint16_t harq_in_length,\n \t\tuint32_t harq_in_offset, uint32_t harq_out_offset)\n {\n-\tfpga_mutex_acquisition(q);\n+\tfpga_5gnr_mutex_acquisition(q);\n \tuint32_t out_offset = harq_out_offset;\n \tuint32_t in_offset = harq_in_offset;\n \tuint32_t left_length = harq_in_length;\n \tuint32_t reg_32, increment = 0;\n \tuint64_t *input = NULL;\n-\tuint32_t last_transaction = left_length\n-\t\t\t% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\tuint32_t last_transaction = left_length % FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES;\n \tuint64_t last_word;\n \n \tif (last_transaction > 0)\n@@ -1542,71 +1522,63 @@ fpga_harq_write_loopback(struct fpga_queue *q,\n \t * Get HARQ buffer size for each VF/PF: When 0x00, there is no\n \t * available DDR space for the corresponding VF/PF.\n \t */\n-\treg_32 = fpga_reg_read_32(q->d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n+\treg_32 = fpga_5gnr_reg_read_32(q->d->mmio_base, FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n \tif (reg_32 < harq_in_length) {\n \t\tleft_length = reg_32;\n \t\trte_bbdev_log(ERR, \"HARQ in length > HARQ buffer size\\n\");\n \t}\n \n-\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,\n-\t\t\tuint8_t *, in_offset);\n+\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input, uint8_t *, in_offset);\n \n \twhile (left_length > 0) {\n-\t\tif (fpga_reg_read_8(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {\n-\t\t\tfpga_reg_write_32(q->d->mmio_base,\n+\t\tif (fpga_5gnr_reg_read_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {\n+\t\t\tfpga_5gnr_reg_write_32(q->d->mmio_base,\n \t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,\n \t\t\t\t\tout_offset);\n-\t\t\tfpga_reg_write_64(q->d->mmio_base,\n+\t\t\tfpga_5gnr_reg_write_64(q->d->mmio_base,\n \t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS,\n \t\t\t\t\tinput[increment]);\n-\t\t\tleft_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n-\t\t\tout_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\t\tleft_length -= FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\t\tout_offset += FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES;\n \t\t\tincrement++;\n-\t\t\tfpga_reg_write_8(q->d->mmio_base,\n-\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n+\t\t\tfpga_5gnr_reg_write_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n \t\t}\n \t}\n \twhile (last_transaction > 0) {\n-\t\tif (fpga_reg_read_8(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {\n-\t\t\tfpga_reg_write_32(q->d->mmio_base,\n+\t\tif (fpga_5gnr_reg_read_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {\n+\t\t\tfpga_5gnr_reg_write_32(q->d->mmio_base,\n \t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,\n \t\t\t\t\tout_offset);\n \t\t\tlast_word = input[increment];\n \t\t\tlast_word &= (uint64_t)(1 << (last_transaction * 4))\n \t\t\t\t\t- 1;\n-\t\t\tfpga_reg_write_64(q->d->mmio_base,\n+\t\t\tfpga_5gnr_reg_write_64(q->d->mmio_base,\n \t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS,\n \t\t\t\t\tlast_word);\n-\t\t\tfpga_reg_write_8(q->d->mmio_base,\n-\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n+\t\t\tfpga_5gnr_reg_write_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n \t\t\tlast_transaction = 0;\n \t\t}\n \t}\n-\tfpga_mutex_free(q);\n+\tfpga_5gnr_mutex_free(q);\n \treturn 1;\n }\n \n static inline int\n-fpga_harq_read_loopback(struct fpga_queue *q,\n+fpga_5gnr_harq_read_loopback(struct fpga_5gnr_queue *q,\n \t\tstruct rte_mbuf *harq_output, uint16_t harq_in_length,\n \t\tuint32_t harq_in_offset, uint32_t harq_out_offset)\n {\n-\tfpga_mutex_acquisition(q);\n+\tfpga_5gnr_mutex_acquisition(q);\n \tuint32_t left_length, in_offset = harq_in_offset;\n \tuint64_t reg;\n \tuint32_t increment = 0;\n \tuint64_t *input = NULL;\n-\tuint32_t last_transaction = harq_in_length\n-\t\t\t% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\tuint32_t last_transaction = harq_in_length % FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES;\n \n \tif (last_transaction > 0)\n \t\tharq_in_length += (8 - last_transaction);\n \n-\treg = fpga_reg_read_32(q->d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n+\treg = fpga_5gnr_reg_read_32(q->d->mmio_base, FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n \tif (reg < harq_in_length) {\n \t\tharq_in_length = reg;\n \t\trte_bbdev_log(ERR, \"HARQ in length > HARQ buffer size\\n\");\n@@ -1614,11 +1586,9 @@ fpga_harq_read_loopback(struct fpga_queue *q,\n \n \tif (!mbuf_append(harq_output, harq_output, harq_in_length)) {\n \t\trte_bbdev_log(ERR, \"HARQ output buffer warning %d %d\\n\",\n-\t\t\t\tharq_output->buf_len -\n-\t\t\t\trte_pktmbuf_headroom(harq_output),\n+\t\t\t\tharq_output->buf_len - rte_pktmbuf_headroom(harq_output),\n \t\t\t\tharq_in_length);\n-\t\tharq_in_length = harq_output->buf_len -\n-\t\t\t\trte_pktmbuf_headroom(harq_output);\n+\t\tharq_in_length = harq_output->buf_len - rte_pktmbuf_headroom(harq_output);\n \t\tif (!mbuf_append(harq_output, harq_output, harq_in_length)) {\n \t\t\trte_bbdev_log(ERR, \"HARQ output buffer issue %d %d\\n\",\n \t\t\t\t\tharq_output->buf_len, harq_in_length);\n@@ -1627,39 +1597,34 @@ fpga_harq_read_loopback(struct fpga_queue *q,\n \t}\n \tleft_length = harq_in_length;\n \n-\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output,\n-\t\t\tuint8_t *, harq_out_offset);\n+\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output, uint8_t *, harq_out_offset);\n \n \twhile (left_length > 0) {\n-\t\tfpga_reg_write_32(q->d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset);\n-\t\tfpga_reg_write_8(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);\n-\t\treg = fpga_reg_read_8(q->d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n+\t\tfpga_5gnr_reg_write_32(q->d->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS,\n+\t\t\t\tin_offset);\n+\t\tfpga_5gnr_reg_write_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);\n+\t\treg = fpga_5gnr_reg_read_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n \t\twhile (reg != 1) {\n-\t\t\treg = fpga_reg_read_8(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n-\t\t\tif (reg == FPGA_DDR_OVERFLOW) {\n-\t\t\t\trte_bbdev_log(ERR,\n-\t\t\t\t\t\t\"Read address is overflow!\\n\");\n+\t\t\treg = fpga_5gnr_reg_read_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n+\t\t\tif (reg == FPGA_5GNR_DDR_OVERFLOW) {\n+\t\t\t\trte_bbdev_log(ERR, \"Read address is overflow!\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n \t\t}\n-\t\tinput[increment] = fpga_reg_read_64(q->d->mmio_base,\n+\t\tinput[increment] = fpga_5gnr_reg_read_64(q->d->mmio_base,\n \t\t\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS);\n-\t\tleft_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES;\n-\t\tin_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\tleft_length -= FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES;\n+\t\tin_offset += FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES;\n \t\tincrement++;\n-\t\tfpga_reg_write_8(q->d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);\n+\t\tfpga_5gnr_reg_write_8(q->d->mmio_base, FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);\n \t}\n-\tfpga_mutex_free(q);\n+\tfpga_5gnr_mutex_free(q);\n \treturn 1;\n }\n \n static inline int\n-enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,\n+enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *op,\n \t\tuint16_t desc_offset)\n {\n \tunion fpga_dma_desc *desc;\n@@ -1750,7 +1715,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,\n }\n \n static inline int\n-enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,\n+enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *op,\n \t\tuint16_t desc_offset)\n {\n \tunion fpga_dma_desc *desc;\n@@ -1780,24 +1745,21 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \tdesc = q->ring_addr + ring_offset;\n \n-\tif (check_bit(dec->op_flags,\n-\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {\n+\tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {\n \t\tstruct rte_mbuf *harq_in = dec->harq_combined_input.data;\n \t\tstruct rte_mbuf *harq_out = dec->harq_combined_output.data;\n \t\tharq_in_length = dec->harq_combined_input.length;\n \t\tuint32_t harq_in_offset = dec->harq_combined_input.offset;\n \t\tuint32_t harq_out_offset = dec->harq_combined_output.offset;\n \n-\t\tif (check_bit(dec->op_flags,\n-\t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE\n-\t\t\t\t)) {\n-\t\t\tret = fpga_harq_write_loopback(q, harq_in,\n+\t\tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE)) {\n+\t\t\tret = fpga_5gnr_harq_write_loopback(q, harq_in,\n \t\t\t\t\tharq_in_length, harq_in_offset,\n \t\t\t\t\tharq_out_offset);\n \t\t} else if (check_bit(dec->op_flags,\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE\n \t\t\t\t)) {\n-\t\t\tret = fpga_harq_read_loopback(q, harq_out,\n+\t\t\tret = fpga_5gnr_harq_read_loopback(q, harq_out,\n \t\t\t\tharq_in_length, harq_in_offset,\n \t\t\t\tharq_out_offset);\n \t\t\tdec->harq_combined_output.length = harq_in_length;\n@@ -1805,14 +1767,15 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,\n \t\t\trte_bbdev_log(ERR, \"OP flag Err!\");\n \t\t\tret = -1;\n \t\t}\n+\n \t\t/* Set descriptor for dequeue */\n \t\tdesc->dec_req.done = 1;\n \t\tdesc->dec_req.error = 0;\n \t\tdesc->dec_req.op_addr = op;\n \t\tdesc->dec_req.cbs_in_op = 1;\n+\n \t\t/* Mark this dummy descriptor to be dropped by HW */\n-\t\tdesc->dec_req.desc_idx = (ring_offset + 1)\n-\t\t\t\t& q->sw_ring_wrap_mask;\n+\t\tdesc->dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask;\n \t\treturn ret; /* Error or number of CB */\n \t}\n \n@@ -1888,13 +1851,13 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,\n }\n \n static uint16_t\n-fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n+fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n \tuint16_t i, total_enqueued_cbs = 0;\n \tint32_t avail;\n \tint enqueued_cbs;\n-\tstruct fpga_queue *q = q_data->queue_private;\n+\tstruct fpga_5gnr_queue *q = q_data->queue_private;\n \tunion fpga_dma_desc *desc;\n \n \t/* Check if queue is not full */\n@@ -1915,8 +1878,7 @@ fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\tif (unlikely(avail - 1 < 0))\n \t\t\tbreak;\n \t\tavail -= 1;\n-\t\tenqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i],\n-\t\t\t\ttotal_enqueued_cbs);\n+\t\tenqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i], total_enqueued_cbs);\n \n \t\tif (enqueued_cbs < 0)\n \t\t\tbreak;\n@@ -1935,7 +1897,7 @@ fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\t\t& q->sw_ring_wrap_mask);\n \tdesc->enc_req.irq_en = q->irq_enable;\n \n-\tfpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n+\tfpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n \n \t/* Update stats */\n \tq_data->queue_stats.enqueued_count += i;\n@@ -1945,18 +1907,17 @@ fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n }\n \n static uint16_t\n-fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n+fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n \tuint16_t i, total_enqueued_cbs = 0;\n \tint32_t avail;\n \tint enqueued_cbs;\n-\tstruct fpga_queue *q = q_data->queue_private;\n+\tstruct fpga_5gnr_queue *q = q_data->queue_private;\n \tunion fpga_dma_desc *desc;\n \n \t/* Check if queue is not full */\n-\tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==\n-\t\t\tq->head_free_desc))\n+\tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc))\n \t\treturn 0;\n \n \t/* Calculates available space */\n@@ -1995,20 +1956,19 @@ fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \tdesc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)\n \t\t\t& q->sw_ring_wrap_mask);\n \tdesc->enc_req.irq_en = q->irq_enable;\n-\tfpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n+\tfpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n \treturn i;\n }\n \n \n static inline int\n-dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,\n+dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **op,\n \t\tuint16_t desc_offset)\n {\n \tunion fpga_dma_desc *desc;\n \tint desc_error;\n \t/* Set current desc */\n-\tdesc = q->ring_addr + ((q->head_free_desc + desc_offset)\n-\t\t\t& q->sw_ring_wrap_mask);\n+\tdesc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n \n \t/*check if done */\n \tif (desc->enc_req.done == 0)\n@@ -2033,7 +1993,7 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,\n \n \n static inline int\n-dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,\n+dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **op,\n \t\tuint16_t desc_offset)\n {\n \tunion fpga_dma_desc *desc;\n@@ -2075,10 +2035,10 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,\n }\n \n static uint16_t\n-fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n+fpga_5gnr_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n-\tstruct fpga_queue *q = q_data->queue_private;\n+\tstruct fpga_5gnr_queue *q = q_data->queue_private;\n \tuint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;\n \tuint16_t i;\n \tuint16_t dequeued_cbs = 0;\n@@ -2107,10 +2067,10 @@ fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n }\n \n static uint16_t\n-fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n+fpga_5gnr_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n-\tstruct fpga_queue *q = q_data->queue_private;\n+\tstruct fpga_5gnr_queue *q = q_data->queue_private;\n \tuint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;\n \tuint16_t i;\n \tuint16_t dequeued_cbs = 0;\n@@ -2129,8 +2089,7 @@ fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t}\n \n \t/* Update head */\n-\tq->head_free_desc = (q->head_free_desc + dequeued_cbs) &\n-\t\t\tq->sw_ring_wrap_mask;\n+\tq->head_free_desc = (q->head_free_desc + dequeued_cbs) & q->sw_ring_wrap_mask;\n \n \t/* Update stats */\n \tq_data->queue_stats.dequeued_count += i;\n@@ -2145,15 +2104,14 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n {\n \tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n \n-\tdev->dev_ops = &fpga_ops;\n-\tdev->enqueue_ldpc_enc_ops = fpga_enqueue_ldpc_enc;\n-\tdev->enqueue_ldpc_dec_ops = fpga_enqueue_ldpc_dec;\n-\tdev->dequeue_ldpc_enc_ops = fpga_dequeue_ldpc_enc;\n-\tdev->dequeue_ldpc_dec_ops = fpga_dequeue_ldpc_dec;\n+\tdev->dev_ops = &fpga_5gnr_ops;\n+\tdev->enqueue_ldpc_enc_ops = fpga_5gnr_enqueue_ldpc_enc;\n+\tdev->enqueue_ldpc_dec_ops = fpga_5gnr_enqueue_ldpc_dec;\n+\tdev->dequeue_ldpc_enc_ops = fpga_5gnr_dequeue_ldpc_enc;\n+\tdev->dequeue_ldpc_dec_ops = fpga_5gnr_dequeue_ldpc_dec;\n \n \t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =\n-\t\t\t!strcmp(drv->driver.name,\n-\t\t\t\t\tRTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));\n+\t\t\t!strcmp(drv->driver.name, RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));\n \t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =\n \t\t\tpci_dev->mem_resource[0].addr;\n \n@@ -2202,14 +2160,14 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,\n \tbbdev->intr_handle = pci_dev->intr_handle;\n \tbbdev->data->socket_id = pci_dev->device.numa_node;\n \n-\t/* Invoke FEC FPGA device initialization function */\n+\t/* Invoke FPGA 5GNR FEC device initialization function */\n \tfpga_5gnr_fec_init(bbdev, pci_drv);\n \n \trte_bbdev_log_debug(\"bbdev id = %u [%s]\",\n \t\t\tbbdev->data->dev_id, dev_name);\n \n \tstruct fpga_5gnr_fec_device *d = bbdev->data->dev_private;\n-\tuint32_t version_id = fpga_reg_read_32(d->mmio_base,\n+\tuint32_t version_id = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\tFPGA_5GNR_FEC_VERSION_ID);\n \trte_bbdev_log(INFO, \"FEC FPGA RTL v%u.%u\",\n \t\t((uint16_t)(version_id >> 16)), ((uint16_t)version_id));\n@@ -2255,8 +2213,7 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n \t/* release bbdev from library */\n \tret = rte_bbdev_release(bbdev);\n \tif (ret)\n-\t\trte_bbdev_log(ERR, \"Device %i failed to uninit: %i\", dev_id,\n-\t\t\t\tret);\n+\t\trte_bbdev_log(ERR, \"Device %i failed to uninit: %i\", dev_id, ret);\n \n \trte_bbdev_log_debug(\"Destroyed bbdev = %u\", dev_id);\n \n@@ -2264,7 +2221,7 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n }\n \n static inline void\n-set_default_fpga_conf(struct rte_fpga_5gnr_fec_conf *def_conf)\n+fpga_5gnr_set_default_conf(struct rte_fpga_5gnr_fec_conf *def_conf)\n {\n \t/* clear default configuration before initialization */\n \tmemset(def_conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));\n@@ -2304,7 +2261,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \tif (conf == NULL) {\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"FPGA Configuration was not provided. Default configuration will be loaded.\");\n-\t\tset_default_fpga_conf(&def_conf);\n+\t\tfpga_5gnr_set_default_conf(&def_conf);\n \t\tconf = &def_conf;\n \t}\n \n@@ -2315,13 +2272,13 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t */\n \tpayload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;\n \taddress = FPGA_5GNR_FEC_CONFIGURATION;\n-\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n \t/* Clear all queues registers */\n-\tpayload_32 = FPGA_INVALID_HW_QUEUE_ID;\n+\tpayload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID;\n \tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n \t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n-\t\tfpga_reg_write_32(d->mmio_base, address, payload_32);\n+\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t}\n \n \t/*\n@@ -2382,7 +2339,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t\tpayload_32 = 0x1;\n \t\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n \t\t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n-\t\t\tfpga_reg_write_32(d->mmio_base, address, payload_32);\n+\t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t\t}\n \t} else {\n \t\t/* Calculate total number of UL and DL queues to configure */\n@@ -2412,7 +2369,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t\t\t\taddress = (total_ul_q_id << 2) +\n \t\t\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP;\n \t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n-\t\t\t\tfpga_reg_write_32(d->mmio_base, address,\n+\t\t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address,\n \t\t\t\t\t\tpayload_32);\n \t\t\t}\n \t\t}\n@@ -2423,7 +2380,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t\t\t\taddress = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)\n \t\t\t\t\t\t<< 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n \t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n-\t\t\t\tfpga_reg_write_32(d->mmio_base, address,\n+\t\t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address,\n \t\t\t\t\t\tpayload_32);\n \t\t\t}\n \t\t}\n@@ -2432,17 +2389,17 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t/* Setting Load Balance Factor */\n \tpayload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);\n \taddress = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;\n-\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n \t/* Setting length of ring descriptor entry */\n-\tpayload_16 = FPGA_RING_DESC_ENTRY_LENGTH;\n+\tpayload_16 = FPGA_5GNR_RING_DESC_ENTRY_LENGTH;\n \taddress = FPGA_5GNR_FEC_RING_DESC_LEN;\n-\tfpga_reg_write_16(d->mmio_base, address, payload_16);\n+\tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n \t/* Queue PF/VF mapping table is ready */\n \tpayload_8 = 0x1;\n \taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n-\tfpga_reg_write_8(d->mmio_base, address, payload_8);\n+\tfpga_5gnr_reg_write_8(d->mmio_base, address, payload_8);\n \n \trte_bbdev_log_debug(\"PF FPGA 5GNR FEC configuration complete for %s\",\n \t\t\tdev_name);\n@@ -2487,8 +2444,6 @@ static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {\n \n \n RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);\n-RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,\n-\t\tpci_id_fpga_5gnr_fec_pf_map);\n+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME, pci_id_fpga_5gnr_fec_pf_map);\n RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);\n-RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,\n-\t\tpci_id_fpga_5gnr_fec_vf_map);\n+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME, pci_id_fpga_5gnr_fec_vf_map);\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\nindex f042d5dea586..894c218a5f7d 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\n@@ -13,9 +13,8 @@\n /**\n  * @file rte_pmd_fpga_5gnr_fec.h\n  *\n- * Interface for Intel(R) FGPA 5GNR FEC device configuration at the host level,\n- * directly accessible by the application.\n- * Configuration related to 5GNR functionality is done through\n+ * Functions for configuring VC 5GNR and AGX100 HW, exposed directly to applications.\n+ * Configuration related to encoding/decoding is done through the\n  * librte_bbdev library.\n  *\n  * @warning\n@@ -26,11 +25,11 @@\n extern \"C\" {\n #endif\n \n-/** Number of Virtual Functions FGPA 4G FEC supports */\n+/** Number of Virtual Functions FPGA 5GNR FEC supports */\n #define FPGA_5GNR_FEC_NUM_VFS 8\n \n /**\n- * Structure to pass FPGA 4G FEC configuration.\n+ * Structure to pass FPGA 5GNR FEC configuration.\n  */\n struct rte_fpga_5gnr_fec_conf {\n \t/** 1 if PF is used for dataplane, 0 for VFs */\n@@ -39,9 +38,9 @@ struct rte_fpga_5gnr_fec_conf {\n \tuint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n \t/** Number of DL queues per VF */\n \tuint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n-\t/** UL bandwidth. Needed for schedule algorithm */\n+\t/** UL bandwidth. Needed only for VC schedule algorithm */\n \tuint8_t ul_bandwidth;\n-\t/** DL bandwidth. Needed for schedule algorithm */\n+\t/** DL bandwidth. Needed only for VC schedule algorithm */\n \tuint8_t dl_bandwidth;\n \t/** UL Load Balance */\n \tuint8_t ul_load_balance;\n@@ -50,14 +49,14 @@ struct rte_fpga_5gnr_fec_conf {\n };\n \n /**\n- * Configure Intel(R) FPGA 5GNR FEC device\n+ * Configure a FPGA 5GNR device in PF mode notably for bbdev-test\n  *\n  * @param dev_name\n  *   The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n  *   It can also be retrieved for a bbdev device from the dev_name field in the\n  *   rte_bbdev_info structure returned by rte_bbdev_info_get().\n  * @param conf\n- *   Configuration to apply to FPGA 4G FEC.\n+ *   Configuration to apply to FPGA 5GNR FEC.\n  *\n  * @return\n  *   Zero on success, negative value on failure.\n",
    "prefixes": [
        "v3",
        "1/4"
    ]
}