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Update a patch.
GET /api/patches/131530/?format=api
{ "id": 131530, "url": "http://patches.dpdk.org/api/patches/131530/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230918021130.192982-15-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230918021130.192982-15-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230918021130.192982-15-simei.su@intel.com", "date": "2023-09-18T02:11:26", "name": "[v4,14/18] common/idpf/base: use GENMASK macro", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dac6ada7aa35fec9101a5235595af87924c1f384", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230918021130.192982-15-simei.su@intel.com/mbox/", "series": [ { "id": 29530, "url": "http://patches.dpdk.org/api/series/29530/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29530", "date": "2023-09-18T02:11:12", "name": "update idpf base code", "version": 4, "mbox": "http://patches.dpdk.org/series/29530/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131530/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131530/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7CF77425C9;\n\tMon, 18 Sep 2023 04:13:17 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EE2E040DCB;\n\tMon, 18 Sep 2023 04:12:45 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 81E5640A81\n for <dev@dpdk.org>; Mon, 18 Sep 2023 04:12:38 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Sep 2023 19:11:41 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2023 19:11:38 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695003159; x=1726539159;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=t1YwhA6ODp7Rx/kepctuEro/dp+EeLR0ibMpoGVGNDQ=;\n b=ZKwb78kc9LnQ1mpjLyV7915bh35rw/9xli+98yjz7UvWSRULNu21MN74\n 9Ad/CMR1HEI1USPFJq2ogxeJSN/SimMM+0DftViPQHx4aYGjQyP6RYAje\n HyDw9tKlTwbEeBJy4tSmF6rZ8jay3T3JijiPnmrepnoaT1R6KozV0KRAy\n cVpIqQnnWVRRzp6p9ShrSfkgoylNOLhTm8ENN7NuOrUjTE0dJbaIQGgL9\n 3r+J/HqPymGm7lUYxbqO7Wimn74frTaeZUouHVOsAKt8+t60bUNzfOpFJ\n l11crnCGnN9o44Uh5S7IFuf6aQX/hWV+aRvTH8mU/xM7N6cvrK0j7rd2p g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10836\"; a=\"359801764\"", "E=Sophos;i=\"6.02,155,1688454000\"; d=\"scan'208\";a=\"359801764\"", "E=McAfee;i=\"6600,9927,10836\"; a=\"815847024\"", "E=Sophos;i=\"6.02,155,1688454000\"; d=\"scan'208\";a=\"815847024\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com,\n wenjing.qiao@intel.com, Simei Su <simei.su@intel.com>,\n Pavan Kumar Linga <pavan.kumar.linga@intel.com>", "Subject": "[PATCH v4 14/18] common/idpf/base: use GENMASK macro", "Date": "Mon, 18 Sep 2023 10:11:26 +0800", "Message-Id": "<20230918021130.192982-15-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230918021130.192982-1-simei.su@intel.com>", "References": "<20230915021730.2681882-1-simei.su@intel.com>\n <20230918021130.192982-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Instead of using a custom defined macro for generating a mask,\nuse the standard GENMASK macro.\n\nSigned-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\nAcked-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 ++---\n drivers/common/idpf/base/idpf_lan_txrx.h | 116 +++++++++-----------\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +--\n drivers/common/idpf/base/idpf_osdep.h | 7 ++\n 4 files changed, 80 insertions(+), 85 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex e47afad6e9..b9d82592c0 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -24,7 +24,7 @@\n #define PF_FW_ARQBAH\t\t\t(PF_FW_BASE + 0x4)\n #define PF_FW_ARQLEN\t\t\t(PF_FW_BASE + 0x8)\n #define PF_FW_ARQLEN_ARQLEN_S\t\t0\n-#define PF_FW_ARQLEN_ARQLEN_M\t\tIDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)\n+#define PF_FW_ARQLEN_ARQLEN_M\t\tGENMASK(12, 0)\n #define PF_FW_ARQLEN_ARQVFE_S\t\t28\n #define PF_FW_ARQLEN_ARQVFE_M\t\tBIT(PF_FW_ARQLEN_ARQVFE_S)\n #define PF_FW_ARQLEN_ARQOVFL_S\t\t29\n@@ -35,14 +35,14 @@\n #define PF_FW_ARQLEN_ARQENABLE_M\tBIT(PF_FW_ARQLEN_ARQENABLE_S)\n #define PF_FW_ARQH\t\t\t(PF_FW_BASE + 0xC)\n #define PF_FW_ARQH_ARQH_S\t\t0\n-#define PF_FW_ARQH_ARQH_M\t\tIDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S)\n+#define PF_FW_ARQH_ARQH_M\t\tGENMASK(12, 0)\n #define PF_FW_ARQT\t\t\t(PF_FW_BASE + 0x10)\n \n #define PF_FW_ATQBAL\t\t\t(PF_FW_BASE + 0x14)\n #define PF_FW_ATQBAH\t\t\t(PF_FW_BASE + 0x18)\n #define PF_FW_ATQLEN\t\t\t(PF_FW_BASE + 0x1C)\n #define PF_FW_ATQLEN_ATQLEN_S\t\t0\n-#define PF_FW_ATQLEN_ATQLEN_M\t\tIDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)\n+#define PF_FW_ATQLEN_ATQLEN_M\t\tGENMASK(9, 0)\n #define PF_FW_ATQLEN_ATQVFE_S\t\t28\n #define PF_FW_ATQLEN_ATQVFE_M\t\tBIT(PF_FW_ATQLEN_ATQVFE_S)\n #define PF_FW_ATQLEN_ATQOVFL_S\t\t29\n@@ -53,7 +53,7 @@\n #define PF_FW_ATQLEN_ATQENABLE_M\tBIT(PF_FW_ATQLEN_ATQENABLE_S)\n #define PF_FW_ATQH\t\t\t(PF_FW_BASE + 0x20)\n #define PF_FW_ATQH_ATQH_S\t\t0\n-#define PF_FW_ATQH_ATQH_M\t\tIDPF_M(0x3FF, PF_FW_ATQH_ATQH_S)\n+#define PF_FW_ATQH_ATQH_M\t\tGENMASK(9, 0)\n #define PF_FW_ATQT\t\t\t(PF_FW_BASE + 0x24)\n \n /* Interrupts */\n@@ -66,7 +66,7 @@\n #define PF_GLINT_DYN_CTL_SWINT_TRIG_S\t2\n #define PF_GLINT_DYN_CTL_SWINT_TRIG_M\tBIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)\n #define PF_GLINT_DYN_CTL_ITR_INDX_S\t3\n-#define PF_GLINT_DYN_CTL_ITR_INDX_M\tIDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)\n+#define PF_GLINT_DYN_CTL_ITR_INDX_M\tGENMASK(4, 3)\n #define PF_GLINT_DYN_CTL_INTERVAL_S\t5\n #define PF_GLINT_DYN_CTL_INTERVAL_M\tBIT(PF_GLINT_DYN_CTL_INTERVAL_S)\n #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S\t24\n@@ -87,13 +87,13 @@\n \t(PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n-#define PF_GLINT_ITR_INTERVAL_M\t\tIDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S)\n+#define PF_GLINT_ITR_INTERVAL_M\t\tGENMASK(11, 0)\n \n /* Timesync registers */\n #define PF_TIMESYNC_BASE\t\t0x08404000\n #define PF_GLTSYN_CMD_SYNC\t\t(PF_TIMESYNC_BASE)\n #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S\t0\n-#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M\tIDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)\n+#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M\tGENMASK(1, 0)\n #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S\t2\n #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M\tBIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S)\n #define PF_GLTSYN_SHTIME_0\t\t(PF_TIMESYNC_BASE + 0x4)\n@@ -105,23 +105,23 @@\n /* Generic registers */\n #define PF_INT_DIR_OICR_ENA\t\t0x08406000\n #define PF_INT_DIR_OICR_ENA_S\t\t0\n-#define PF_INT_DIR_OICR_ENA_M\tIDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S)\n+#define PF_INT_DIR_OICR_ENA_M\t\tGENMASK(31, 0)\n #define PF_INT_DIR_OICR\t\t\t0x08406004\n #define PF_INT_DIR_OICR_TSYN_EVNT\t0\n #define PF_INT_DIR_OICR_PHY_TS_0\tBIT(1)\n #define PF_INT_DIR_OICR_PHY_TS_1\tBIT(2)\n #define PF_INT_DIR_OICR_CAUSE\t\t0x08406008\n #define PF_INT_DIR_OICR_CAUSE_CAUSE_S\t0\n-#define PF_INT_DIR_OICR_CAUSE_CAUSE_M\tIDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S)\n+#define PF_INT_DIR_OICR_CAUSE_CAUSE_M\tGENMASK(31, 0)\n #define PF_INT_PBA_CLEAR\t\t0x0840600C\n \n #define PF_FUNC_RID\t\t\t0x08406010\n #define PF_FUNC_RID_FUNCTION_NUMBER_S\t0\n-#define PF_FUNC_RID_FUNCTION_NUMBER_M\tIDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S)\n+#define PF_FUNC_RID_FUNCTION_NUMBER_M\tGENMASK(2, 0)\n #define PF_FUNC_RID_DEVICE_NUMBER_S\t3\n-#define PF_FUNC_RID_DEVICE_NUMBER_M\tIDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S)\n+#define PF_FUNC_RID_DEVICE_NUMBER_M\tGENMASK(7, 3)\n #define PF_FUNC_RID_BUS_NUMBER_S\t8\n-#define PF_FUNC_RID_BUS_NUMBER_M\tIDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S)\n+#define PF_FUNC_RID_BUS_NUMBER_M\tGENMASK(15, 8)\n \n /* Reset registers */\n #define PFGEN_RTRIG\t\t\t0x08407000\n@@ -133,7 +133,7 @@\n #define PFGEN_RTRIG_IMCR_M\t\tBIT(2)\n #define PFGEN_RSTAT\t\t\t0x08407008 /* PFR Status */\n #define PFGEN_RSTAT_PFR_STATE_S\t\t0\n-#define PFGEN_RSTAT_PFR_STATE_M\t\tIDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S)\n+#define PFGEN_RSTAT_PFR_STATE_M\t\tGENMASK(1, 0)\n #define PFGEN_CTRL\t\t\t0x0840700C\n #define PFGEN_CTRL_PFSWR\t\tBIT(0)\n \ndiff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h\nindex 4951e266f0..f213c49e47 100644\n--- a/drivers/common/idpf/base/idpf_lan_txrx.h\n+++ b/drivers/common/idpf/base/idpf_lan_txrx.h\n@@ -60,65 +60,54 @@ enum idpf_rss_hash {\n \tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))\n \n /* For idpf_splitq_base_tx_compl_desc */\n-#define IDPF_TXD_COMPLQ_GEN_S\t15\n+#define IDPF_TXD_COMPLQ_GEN_S\t\t15\n #define IDPF_TXD_COMPLQ_GEN_M\t\tBIT_ULL(IDPF_TXD_COMPLQ_GEN_S)\n #define IDPF_TXD_COMPLQ_COMPL_TYPE_S\t11\n-#define IDPF_TXD_COMPLQ_COMPL_TYPE_M\t\\\n-\tIDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)\n-#define IDPF_TXD_COMPLQ_QID_S\t0\n-#define IDPF_TXD_COMPLQ_QID_M\t\tIDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)\n+#define IDPF_TXD_COMPLQ_COMPL_TYPE_M\tGENMASK_ULL(13, 11)\n+#define IDPF_TXD_COMPLQ_QID_S\t\t0\n+#define IDPF_TXD_COMPLQ_QID_M\t\tGENMASK_ULL(9, 0)\n \n /* For base mode TX descriptors */\n \n-#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S\t23\n-#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M\tBIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)\n-#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S\t19\n-#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M\t\\\n-\t(0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)\n-#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S\t12\n-#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M\t\\\n-\t(0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)\n+#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S\t\t23\n+#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M\t\t\\\n+\tBIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)\n+#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S\t\t19\n+#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M\t\tGENMASK_ULL(22, 19)\n+#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S\t\t12\n+#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M\t\tGENMASK_ULL(18, 12)\n #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S\t11\n-#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \\\n+#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M\t\\\n \tBIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)\n #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST\t\\\n \tIDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M\n-#define IDPF_TXD_CTX_QW0_TUNN_NATT_S\t 9\n-#define IDPF_TXD_CTX_QW0_TUNN_NATT_M\t(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)\n-#define IDPF_TXD_CTX_UDP_TUNNELING\tBIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)\n-#define IDPF_TXD_CTX_GRE_TUNNELING\t(0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)\n+#define IDPF_TXD_CTX_QW0_TUNN_NATT_S\t\t9\n+#define IDPF_TXD_CTX_QW0_TUNN_NATT_M\t\tGENMASK_ULL(10, 9)\n+#define IDPF_TXD_CTX_UDP_TUNNELING\t\tBIT_ULL(9)\n+#define IDPF_TXD_CTX_GRE_TUNNELING\t\tBIT_ULL(10)\n #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S\t2\n-#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M\t\\\n-\t(0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)\n-#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S\t0\n-#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M\t\\\n-\t(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)\n-\n-#define IDPF_TXD_CTX_QW1_MSS_S\t\t50\n-#define IDPF_TXD_CTX_QW1_MSS_M\t\t\\\n-\tIDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)\n-#define IDPF_TXD_CTX_QW1_TSO_LEN_S\t30\n-#define IDPF_TXD_CTX_QW1_TSO_LEN_M\t\\\n-\tIDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)\n-#define IDPF_TXD_CTX_QW1_CMD_S\t\t4\n-#define IDPF_TXD_CTX_QW1_CMD_M\t\t\\\n-\tIDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)\n-#define IDPF_TXD_CTX_QW1_DTYPE_S\t0\n-#define IDPF_TXD_CTX_QW1_DTYPE_M\t\\\n-\tIDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)\n-#define IDPF_TXD_QW1_L2TAG1_S\t\t48\n-#define IDPF_TXD_QW1_L2TAG1_M\t\t\\\n-\tIDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)\n-#define IDPF_TXD_QW1_TX_BUF_SZ_S\t34\n-#define IDPF_TXD_QW1_TX_BUF_SZ_M\t\\\n-\tIDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)\n-#define IDPF_TXD_QW1_OFFSET_S\t\t16\n-#define IDPF_TXD_QW1_OFFSET_M\t\t\\\n-\tIDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)\n-#define IDPF_TXD_QW1_CMD_S\t\t4\n-#define IDPF_TXD_QW1_CMD_M\t\tIDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S)\n-#define IDPF_TXD_QW1_DTYPE_S\t\t0\n-#define IDPF_TXD_QW1_DTYPE_M\t\tIDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S)\n+#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M\tGENMASK_ULL(7, 2)\n+#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S\t\t0\n+#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M\t\tGENMASK_ULL(1, 0)\n+\n+#define IDPF_TXD_CTX_QW1_MSS_S\t\t\t50\n+#define IDPF_TXD_CTX_QW1_MSS_M\t\t\tGENMASK_ULL(63, 50)\n+#define IDPF_TXD_CTX_QW1_TSO_LEN_S\t\t30\n+#define IDPF_TXD_CTX_QW1_TSO_LEN_M\t\tGENMASK_ULL(47, 30)\n+#define IDPF_TXD_CTX_QW1_CMD_S\t\t\t4\n+#define IDPF_TXD_CTX_QW1_CMD_M\t\t\tGENMASK_ULL(15, 4)\n+#define IDPF_TXD_CTX_QW1_DTYPE_S\t\t0\n+#define IDPF_TXD_CTX_QW1_DTYPE_M\t\tGENMASK_ULL(3, 0)\n+#define IDPF_TXD_QW1_L2TAG1_S\t\t\t48\n+#define IDPF_TXD_QW1_L2TAG1_M\t\t\tGENMASK_ULL(63, 48)\n+#define IDPF_TXD_QW1_TX_BUF_SZ_S\t\t34\n+#define IDPF_TXD_QW1_TX_BUF_SZ_M\t\tGENMASK_ULL(47, 34)\n+#define IDPF_TXD_QW1_OFFSET_S\t\t\t16\n+#define IDPF_TXD_QW1_OFFSET_M\t\t\tGENMASK_ULL(33, 16)\n+#define IDPF_TXD_QW1_CMD_S\t\t\t4\n+#define IDPF_TXD_QW1_CMD_M\t\t\tGENMASK_ULL(15, 4)\n+#define IDPF_TXD_QW1_DTYPE_S\t\t\t0\n+#define IDPF_TXD_QW1_DTYPE_M\t\t\tGENMASK_ULL(3, 0)\n \n /* TX Completion Descriptor Completion Types */\n #define IDPF_TXD_COMPLT_ITR_FLUSH\t0\n@@ -169,10 +158,10 @@ enum idpf_tx_desc_len_fields {\n \tIDPF_TX_DESC_LEN_L4_LEN_S\t= 14 /* 4 BITS */\n };\n \n-#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)\n-#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)\n-#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n-#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n+#define IDPF_TXD_QW1_MACLEN_M\t\tGENMASK_ULL(6, 0)\n+#define IDPF_TXD_QW1_IPLEN_M\t\tGENMASK_ULL(13, 7)\n+#define IDPF_TXD_QW1_L4LEN_M\t\tGENMASK_ULL(17, 14)\n+#define IDPF_TXD_QW1_FCLEN_M\t\tGENMASK_ULL(17, 14)\n \n enum idpf_tx_base_desc_cmd_bits {\n \tIDPF_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n@@ -238,11 +227,10 @@ struct idpf_flex_tx_desc {\n \t__le64 buf_addr;\t/* Packet buffer address */\n \tstruct {\n \t\t__le16 cmd_dtype;\n-#define IDPF_FLEX_TXD_QW1_DTYPE_S\t\t0\n-#define IDPF_FLEX_TXD_QW1_DTYPE_M\t\t\\\n-\t\tIDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)\n+#define IDPF_FLEX_TXD_QW1_DTYPE_S\t0\n+#define IDPF_FLEX_TXD_QW1_DTYPE_M\tGENMASK(4, 0)\n #define IDPF_FLEX_TXD_QW1_CMD_S\t\t5\n-#define IDPF_FLEX_TXD_QW1_CMD_M\t\tIDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S)\n+#define IDPF_FLEX_TXD_QW1_CMD_M\t\tGENMASK(15, 5)\n \t\tunion {\n \t\t\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */\n \t\t\tu8 raw[4];\n@@ -384,9 +372,9 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_MSS_RT_0\t0\n #define IDPF_TXD_FLEX_CTX_MSS_RT_M\t0x3FFF\n #define IDPF_TXD_FLEX_CTX_FTYPE_S\t14\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VF\tIDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)\n-#define IDPF_TXD_FLEX_CTX_FTYPE_PF\tIDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)\n+#define IDPF_TXD_FLEX_CTX_FTYPE_VF\t0\n+#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV\tBIT(14)\n+#define IDPF_TXD_FLEX_CTX_FTYPE_PF\tBIT(15)\n \t\t\tu8 hdr_len;\n \t\t\tu8 ptag;\n \t\t} tso;\n@@ -403,10 +391,10 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_M\t\t0xFFFFF\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S\t36\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID\t\\\n-\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)\n+\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S)\n #define IDPF_TXD_FLEX_CTX_QW1_TPH_S\t\t37\n-#define IDPF_TXD_FLEX_CTX_QW1_TPH \\\n-\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S)\n+#define IDPF_TXD_FLEX_CTX_QW1_TPH\t\t\\\n+\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S)\n #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S\t\t38\n #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M\t\t0xF\n /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */\n@@ -414,7 +402,7 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M\t\t0x1FFFFF\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S\t63\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID\t\\\n-\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)\n+\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)\n /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */\n #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S\t\t48\n #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M\t\t0xFF\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex 4c5249129e..f394a0d67a 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -9,7 +9,7 @@\n /* Reset */\n #define VFGEN_RSTAT\t\t\t0x00008800\n #define VFGEN_RSTAT_VFR_STATE_S\t\t0\n-#define VFGEN_RSTAT_VFR_STATE_M\t\tIDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S)\n+#define VFGEN_RSTAT_VFR_STATE_M\t\tGENMASK(1, 0)\n \n /* Control(VF Mailbox) Queue */\n #define VF_BASE\t\t\t\t0x00006000\n@@ -18,7 +18,7 @@\n #define VF_ATQBAH\t\t\t(VF_BASE + 0x1800)\n #define VF_ATQLEN\t\t\t(VF_BASE + 0x0800)\n #define VF_ATQLEN_ATQLEN_S\t\t0\n-#define VF_ATQLEN_ATQLEN_M\t\tIDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S)\n+#define VF_ATQLEN_ATQLEN_M\t\tGENMASK(9, 0)\n #define VF_ATQLEN_ATQVFE_S\t\t28\n #define VF_ATQLEN_ATQVFE_M\t\tBIT(VF_ATQLEN_ATQVFE_S)\n #define VF_ATQLEN_ATQOVFL_S\t\t29\n@@ -29,14 +29,14 @@\n #define VF_ATQLEN_ATQENABLE_M\t\tBIT(VF_ATQLEN_ATQENABLE_S)\n #define VF_ATQH\t\t\t\t(VF_BASE + 0x0400)\n #define VF_ATQH_ATQH_S\t\t\t0\n-#define VF_ATQH_ATQH_M\t\t\tIDPF_M(0x3FF, VF_ATQH_ATQH_S)\n+#define VF_ATQH_ATQH_M\t\t\tGENMASK(9, 0)\n #define VF_ATQT\t\t\t\t(VF_BASE + 0x2400)\n \n #define VF_ARQBAL\t\t\t(VF_BASE + 0x0C00)\n #define VF_ARQBAH\t\t\t(VF_BASE)\n #define VF_ARQLEN\t\t\t(VF_BASE + 0x2000)\n #define VF_ARQLEN_ARQLEN_S\t\t0\n-#define VF_ARQLEN_ARQLEN_M\t\tIDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S)\n+#define VF_ARQLEN_ARQLEN_M\t\tGENMASK(9, 0)\n #define VF_ARQLEN_ARQVFE_S\t\t28\n #define VF_ARQLEN_ARQVFE_M\t\tBIT(VF_ARQLEN_ARQVFE_S)\n #define VF_ARQLEN_ARQOVFL_S\t\t29\n@@ -47,7 +47,7 @@\n #define VF_ARQLEN_ARQENABLE_M\t\tBIT(VF_ARQLEN_ARQENABLE_S)\n #define VF_ARQH\t\t\t\t(VF_BASE + 0x1400)\n #define VF_ARQH_ARQH_S\t\t\t0\n-#define VF_ARQH_ARQH_M\t\t\tIDPF_M(0x1FFF, VF_ARQH_ARQH_S)\n+#define VF_ARQH_ARQH_M\t\t\tGENMASK(12, 0)\n #define VF_ARQT\t\t\t\t(VF_BASE + 0x1000)\n \n /* Transmit queues */\n@@ -69,7 +69,7 @@\n #define VF_INT_DYN_CTL0_INTENA_S\t0\n #define VF_INT_DYN_CTL0_INTENA_M\tBIT(VF_INT_DYN_CTL0_INTENA_S)\n #define VF_INT_DYN_CTL0_ITR_INDX_S\t3\n-#define VF_INT_DYN_CTL0_ITR_INDX_M\tIDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)\n+#define VF_INT_DYN_CTL0_ITR_INDX_M\tGENMASK(4, 3)\n #define VF_INT_DYN_CTLN(_INT)\t\t(0x00003800 + ((_INT) * 4))\n #define VF_INT_DYN_CTLN_EXT(_INT)\t(0x00070000 + ((_INT) * 4))\n #define VF_INT_DYN_CTLN_INTENA_S\t0\n@@ -79,7 +79,7 @@\n #define VF_INT_DYN_CTLN_SWINT_TRIG_S\t2\n #define VF_INT_DYN_CTLN_SWINT_TRIG_M\tBIT(VF_INT_DYN_CTLN_SWINT_TRIG_S)\n #define VF_INT_DYN_CTLN_ITR_INDX_S\t3\n-#define VF_INT_DYN_CTLN_ITR_INDX_M\tIDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)\n+#define VF_INT_DYN_CTLN_ITR_INDX_M\tGENMASK(4, 3)\n #define VF_INT_DYN_CTLN_INTERVAL_S\t5\n #define VF_INT_DYN_CTLN_INTERVAL_M\tBIT(VF_INT_DYN_CTLN_INTERVAL_S)\n #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S\t24\n@@ -113,7 +113,7 @@\n \t(0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n-#define VF_INT_ITRN_INTERVAL_M\t\tIDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)\n+#define VF_INT_ITRN_INTERVAL_M\t\tGENMASK(11, 0)\n #define VF_INT_PBA_CLEAR\t\t0x00008900\n \n #define VF_INT_ICR0_ENA1\t\t0x00005000\ndiff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h\nindex 2a817a9807..74a376cb13 100644\n--- a/drivers/common/idpf/base/idpf_osdep.h\n+++ b/drivers/common/idpf/base/idpf_osdep.h\n@@ -48,6 +48,13 @@ typedef struct idpf_lock idpf_lock;\n \n #define IDPF_M(m, s)\t\t((m) << (s))\n \n+#define BITS_PER_LONG (8 * sizeof(long))\n+#define BITS_PER_LONG_LONG (8 * sizeof(long long))\n+#define GENMASK(h, l) \\\n+\t(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n+#define GENMASK_ULL(h, l) \\\n+\t(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n+\n #ifndef ETH_ADDR_LEN\n #define ETH_ADDR_LEN\t\t6\n #endif\n", "prefixes": [ "v4", "14/18" ] }