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GET /api/patches/131452/?format=api
{ "id": 131452, "url": "http://patches.dpdk.org/api/patches/131452/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230915021730.2681882-17-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230915021730.2681882-17-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230915021730.2681882-17-simei.su@intel.com", "date": "2023-09-15T02:17:29", "name": "[v3,16/17] common/idpf/base: remove unused Tx descriptor types", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ba26a0d28896fe533082178c206f576f0135453f", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230915021730.2681882-17-simei.su@intel.com/mbox/", "series": [ { "id": 29513, "url": "http://patches.dpdk.org/api/series/29513/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29513", "date": "2023-09-15T02:17:13", "name": "update idpf base code", "version": 3, "mbox": "http://patches.dpdk.org/series/29513/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131452/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131452/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0D70C4259D;\n\tFri, 15 Sep 2023 04:18:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9D58040DFB;\n\tFri, 15 Sep 2023 04:17:21 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 57D2240DFB\n for <dev@dpdk.org>; Fri, 15 Sep 2023 04:17:20 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Sep 2023 19:17:19 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by fmsmga005.fm.intel.com with ESMTP; 14 Sep 2023 19:17:17 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1694744240; x=1726280240;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=lk4Li/DkWyzCodv6w2XCCPNJ0agiY1dg9oHRa2nuGCQ=;\n b=X/J4f66sbhNhlAtWrd7Z9I5nP2uCXZf0Ifwc7dnSFTVO6fKpm0q7SD6M\n zgn4lombsaRO9TNqdy3h0E2FpUhwh8MpGeBEm/nJtAgo8LnrivS5Wy/Kp\n IRybyLu4F55DS8SBtoUF2pYUI7+4yMkeFyLFkBaFZiuUEEh0djIYC6B78\n 0lm3H/lpoFmvKI3Z3OLRMLfcg9RbSvhZKdSOA/Q1/fdpa98I7hfyX1jPQ\n CrTiisaf6ON0H7zCp+nstm/NKyuvApwzF5FH5zX6wcjSyh4vXPGuQK6MV\n QV6H36jEXMRcli0PoUZny9uva/rwUpzFDDyIKvGqJOywQuZ50oYK4Z4r3 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10833\"; a=\"410078011\"", "E=Sophos;i=\"6.02,147,1688454000\"; d=\"scan'208\";a=\"410078011\"", "E=McAfee;i=\"6600,9927,10833\"; a=\"1075622850\"", "E=Sophos;i=\"6.02,147,1688454000\"; d=\"scan'208\";a=\"1075622850\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com,\n Simei Su <simei.su@intel.com>,\n Pavan Kumar Linga <pavan.kumar.linga@intel.com>", "Subject": "[PATCH v3 16/17] common/idpf/base: remove unused Tx descriptor types", "Date": "Fri, 15 Sep 2023 10:17:29 +0800", "Message-Id": "<20230915021730.2681882-17-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230915021730.2681882-1-simei.su@intel.com>", "References": "<20230825101344.1828774-1-simei.su@intel.com>\n <20230915021730.2681882-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Remove the unused TX descriptor types and mark them as reserved.\n\nSigned-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/common/idpf/base/idpf_lan_txrx.h | 132 ++---------------------\n 1 file changed, 10 insertions(+), 122 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h\nindex 1e19aeafac..5bc4271584 100644\n--- a/drivers/common/idpf/base/idpf_lan_txrx.h\n+++ b/drivers/common/idpf/base/idpf_lan_txrx.h\n@@ -120,19 +120,19 @@ enum idpf_rss_hash {\n enum idpf_tx_desc_dtype_value {\n \tIDPF_TX_DESC_DTYPE_DATA\t\t\t\t= 0,\n \tIDPF_TX_DESC_DTYPE_CTX\t\t\t\t= 1,\n-\tIDPF_TX_DESC_DTYPE_REINJECT_CTX\t\t\t= 2,\n-\tIDPF_TX_DESC_DTYPE_FLEX_DATA\t\t\t= 3,\n-\tIDPF_TX_DESC_DTYPE_FLEX_CTX\t\t\t= 4,\n+\t/* DTYPE 2 is reserved\n+\t * DTYPE 3 is free for future use\n+\t * DTYPE 4 is reserved\n+\t */\n \tIDPF_TX_DESC_DTYPE_FLEX_TSO_CTX\t\t\t= 5,\n-\tIDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1\t\t= 6,\n+\t/* DTYPE 6 is reserved */\n \tIDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2\t\t= 7,\n-\tIDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX\t= 8,\n-\tIDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_TSO_CTX\t= 9,\n-\tIDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_CTX\t= 10,\n-\tIDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX\t\t= 11,\n+\t/* DTYPE 8, 9 are free for future use\n+\t * DTYPE 10 is reserved\n+\t * DTYPE 11 is free for future use\n+\t */\n \tIDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE\t\t= 12,\n-\tIDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_TSO_CTX\t= 13,\n-\tIDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_CTX\t\t= 14,\n+\t/* DTYPE 13, 14 are free for future use */\n \t/* DESC_DONE - HW has completed write-back of descriptor */\n \tIDPF_TX_DESC_DTYPE_DESC_DONE\t\t\t= 15,\n };\n@@ -232,16 +232,6 @@ struct idpf_flex_tx_desc {\n #define IDPF_FLEX_TXD_QW1_CMD_M\t\tGENMASK(15, 5)\n \t\t__le16 cmd_dtype;\n \t\tunion {\n-\t\t\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */\n-\t\t\tu8 raw[4];\n-\n-\t\t\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1 (0x06) */\n-\t\t\tstruct {\n-\t\t\t\t__le16 l2tag1;\n-\t\t\t\tu8 flex;\n-\t\t\t\tu8 tsync;\n-\t\t\t} tsync;\n-\n \t\t\t/* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */\n \t\t\tstruct {\n \t\t\t\t__le16 l2tag1;\n@@ -297,16 +287,6 @@ struct idpf_flex_tx_tso_ctx_qw {\n };\n \n union idpf_flex_tx_ctx_desc {\n-\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_CTX (0x04) */\n-\tstruct {\n-\t\tu8 qw0_flex[8];\n-\t\tstruct {\n-\t\t\t__le16 cmd_dtype;\n-\t\t\t__le16 l2tag1;\n-\t\t\tu8 qw1_flex[4];\n-\t\t} qw1;\n-\t} gen;\n-\n \t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */\n \tstruct {\n \t\tstruct idpf_flex_tx_tso_ctx_qw qw0;\n@@ -315,98 +295,6 @@ union idpf_flex_tx_ctx_desc {\n \t\t\tu8 flex[6];\n \t\t} qw1;\n \t} tso;\n-\n-\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX (0x08) */\n-\tstruct {\n-\t\tstruct idpf_flex_tx_tso_ctx_qw qw0;\n-\t\tstruct {\n-\t\t\t__le16 cmd_dtype;\n-\t\t\t__le16 l2tag2;\n-\t\t\tu8 flex0;\n-\t\t\tu8 ptag;\n-\t\t\tu8 flex1[2];\n-\t\t} qw1;\n-\t} tso_l2tag2_ptag;\n-\n-\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX (0x0B) */\n-\tstruct {\n-\t\tu8 qw0_flex[8];\n-\t\tstruct {\n-\t\t\t__le16 cmd_dtype;\n-\t\t\t__le16 l2tag2;\n-\t\t\tu8 flex[4];\n-\t\t} qw1;\n-\t} l2tag2;\n-\n-\t/* DTYPE = IDPF_TX_DESC_DTYPE_REINJECT_CTX (0x02) */\n-\tstruct {\n-\t\tstruct {\n-\t\t\t__le32 sa_domain;\n-#define IDPF_TXD_FLEX_CTX_SA_DOM_M\t0xFFFF\n-#define IDPF_TXD_FLEX_CTX_SA_DOM_VAL\t0x10000\n-\t\t\t__le32 sa_idx;\n-#define IDPF_TXD_FLEX_CTX_SAIDX_M\t0x1FFFFF\n-\t\t} qw0;\n-\t\tstruct {\n-\t\t\t__le16 cmd_dtype;\n-\t\t\t__le16 txr2comp;\n-#define IDPF_TXD_FLEX_CTX_TXR2COMP\t0x1\n-\t\t\t__le16 miss_txq_comp_tag;\n-\t\t\t__le16 miss_txq_id;\n-\t\t} qw1;\n-\t} reinjection_pkt;\n };\n \n-/* Host Split Context Descriptors */\n-struct idpf_flex_tx_hs_ctx_desc {\n-\tunion {\n-\t\tstruct {\n-\t\t\t__le32 host_fnum_tlen;\n-#define IDPF_TXD_FLEX_CTX_TLEN_S\t0\n-/* see IDPF_TXD_FLEX_CTX_TLEN_M for mask definition */\n-#define IDPF_TXD_FLEX_CTX_FNUM_S\t18\n-#define IDPF_TXD_FLEX_CTX_FNUM_M\t0x7FF\n-#define IDPF_TXD_FLEX_CTX_HOST_S\t29\n-#define IDPF_TXD_FLEX_CTX_HOST_M\t0x7\n-\t\t\t__le16 ftype_mss_rt;\n-#define IDPF_TXD_FLEX_CTX_MSS_RT_0\t0\n-#define IDPF_TXD_FLEX_CTX_MSS_RT_M\t0x3FFF\n-#define IDPF_TXD_FLEX_CTX_FTYPE_S\t14\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VF\t0\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV\tBIT(14)\n-#define IDPF_TXD_FLEX_CTX_FTYPE_PF\tBIT(15)\n-\t\t\tu8 hdr_len;\n-\t\t\tu8 ptag;\n-\t\t} tso;\n-\t\tstruct {\n-\t\t\tu8 flex0[2];\n-\t\t\t__le16 host_fnum_ftype;\n-\t\t\tu8 flex1[3];\n-\t\t\tu8 ptag;\n-\t\t} no_tso;\n-\t} qw0;\n-\n-\t__le64 qw1_cmd_dtype;\n-#define IDPF_TXD_FLEX_CTX_QW1_PASID_S\t\t16\n-#define IDPF_TXD_FLEX_CTX_QW1_PASID_M\t\t0xFFFFF\n-#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S\t36\n-#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID\t\\\n-\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S)\n-#define IDPF_TXD_FLEX_CTX_QW1_TPH_S\t\t37\n-#define IDPF_TXD_FLEX_CTX_QW1_TPH\t\t\\\n-\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S)\n-#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S\t\t38\n-#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M\t\t0xF\n-/* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */\n-#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_S\t\t42\n-#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M\t\t0x1FFFFF\n-#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S\t63\n-#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID\t\\\n-\tBIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)\n-/* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */\n-#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S\t\t48\n-#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M\t\t0xFF\n-#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_S\t\t56\n-#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_M\t\t0xFF\n-};\n #endif /* _IDPF_LAN_TXRX_H_ */\n", "prefixes": [ "v3", "16/17" ] }