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GET /api/patches/131352/?format=api
{ "id": 131352, "url": "http://patches.dpdk.org/api/patches/131352/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230912162640.1439383-5-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230912162640.1439383-5-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230912162640.1439383-5-beilei.xing@intel.com", "date": "2023-09-12T16:26:34", "name": "[v5,04/10] net/cpfl: introduce CP channel API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "09195d2a3e30b3f074cd3dbe2c65b7109a1a4491", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230912162640.1439383-5-beilei.xing@intel.com/mbox/", "series": [ { "id": 29484, "url": "http://patches.dpdk.org/api/series/29484/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29484", "date": "2023-09-12T16:26:30", "name": "net/cpfl: support port representor", "version": 5, "mbox": "http://patches.dpdk.org/series/29484/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131352/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/131352/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4AAAE4257B;\n\tTue, 12 Sep 2023 10:08:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CFAFF4068A;\n\tTue, 12 Sep 2023 10:08:12 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id D5333402EF\n for <dev@dpdk.org>; Tue, 12 Sep 2023 10:08:10 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Sep 2023 01:08:10 -0700", "from dpdk-beileix-icelake.sh.intel.com ([10.67.116.248])\n by fmsmga002.fm.intel.com with ESMTP; 12 Sep 2023 01:08:08 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1694506091; x=1726042091;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=S5/WvtXWXZH/xh+ewEwC3knyw1KE33oBNQsKyT3KzV0=;\n b=Zdc2Si1YtvzW3aQXFOqRSoxvnqz4+UtF31d0HXIN+J/CaMYKqhqUL5WR\n 7oJtq03+SDJhgF5+jGGnRlbgiQLSQXd+dmAsx0a8/t1zEspoMmUv5GIkp\n Js2I46VGcjAYhGqMEat5oWa8G9NA3UZT71R3/YMYNOnk0ND72s34aJNbO\n WwlnFApDdqaeQxYgNOE3qj+kLDFWtNPu2klDDp7VtLkJIW5CP3nKXHgQg\n HwU2GBJeoQDpXrrFGO0FjA26tum7yToRqIPm26dHLgkSroWC4s7nGdD9H\n a3XdgTcErAQQ95iMO4F9PENqrBaM+1pxYDFJz/GVBFc8Nx0ynZXxCRfqj Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10830\"; a=\"375639563\"", "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"375639563\"", "E=McAfee;i=\"6600,9927,10830\"; a=\"858702569\"", "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"858702569\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH v5 04/10] net/cpfl: introduce CP channel API", "Date": "Tue, 12 Sep 2023 16:26:34 +0000", "Message-Id": "<20230912162640.1439383-5-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230912162640.1439383-1-beilei.xing@intel.com>", "References": "<20230908111701.1022724-1-beilei.xing@intel.com>\n <20230912162640.1439383-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThe CPCHNL2 defines the API (v2) used for communication between the\nCPF driver and its on-chip management software. The CPFL PMD is a\nspecific CPF driver to utilize CPCHNL2 for device configuration and\nevent probing.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_cpchnl.h | 340 +++++++++++++++++++++++++++++++++\n 1 file changed, 340 insertions(+)\n create mode 100644 drivers/net/cpfl/cpfl_cpchnl.h", "diff": "diff --git a/drivers/net/cpfl/cpfl_cpchnl.h b/drivers/net/cpfl/cpfl_cpchnl.h\nnew file mode 100644\nindex 0000000000..2eefcbcc10\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_cpchnl.h\n@@ -0,0 +1,340 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_CPCHNL_H_\n+#define _CPFL_CPCHNL_H_\n+\n+/** @brief Command Opcodes\n+ * Values are to be different from virtchnl.h opcodes\n+ */\n+enum cpchnl2_ops {\n+\t/* vport info */\n+\tCPCHNL2_OP_GET_VPORT_LIST\t\t= 0x8025,\n+\tCPCHNL2_OP_GET_VPORT_INFO\t\t= 0x8026,\n+\n+\t/* DPHMA Event notifications */\n+\tCPCHNL2_OP_EVENT\t\t\t= 0x8050,\n+};\n+\n+/* Note! This affects the size of structs below */\n+#define CPCHNL2_MAX_TC_AMOUNT\t\t8\n+\n+#define CPCHNL2_ETH_LENGTH_OF_ADDRESS\t6\n+\n+#define CPCHNL2_FUNC_TYPE_PF\t\t0\n+#define CPCHNL2_FUNC_TYPE_SRIOV\t\t1\n+\n+/* vport statuses - must match the DB ones - see enum cp_vport_status*/\n+#define CPCHNL2_VPORT_STATUS_CREATED\t0\n+#define CPCHNL2_VPORT_STATUS_ENABLED\t1\n+#define CPCHNL2_VPORT_STATUS_DISABLED\t2\n+#define CPCHNL2_VPORT_STATUS_DESTROYED\t3\n+\n+/* Queue Groups Extension */\n+/**************************************************/\n+\n+#define MAX_Q_REGIONS 16\n+/* TBD - with current structure sizes, in order not to exceed 4KB ICQH buffer\n+ * no more than 11 queue groups are allowed per a single vport..\n+ * More will be possible only with future msg fragmentation.\n+ */\n+#define MAX_Q_VPORT_GROUPS 11\n+\n+#define CPCHNL2_CHECK_STRUCT_LEN(n, X) enum static_assert_enum_##X\t\\\n+\t{ static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }\n+\n+struct cpchnl2_queue_chunk {\n+\tu32 type;\t /* 0:QUEUE_TYPE_TX, 1:QUEUE_TYPE_RX */ /* enum nsl_lan_queue_type */\n+\tu32 start_queue_id;\n+\tu32 num_queues;\n+\tu8 pad[4];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(16, cpchnl2_queue_chunk);\n+\n+/* structure to specify several chunks of contiguous queues */\n+struct cpchnl2_queue_grp_chunks {\n+\tu16 num_chunks;\n+\tu8 reserved[6];\n+\tstruct cpchnl2_queue_chunk chunks[MAX_Q_REGIONS];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(264, cpchnl2_queue_grp_chunks);\n+\n+struct cpchnl2_rx_queue_group_info {\n+\t/* User can ask to update rss_lut size originally allocated\n+\t * by CreateVport command. New size will be returned if allocation succeeded,\n+\t * otherwise original rss_size from CreateVport will be returned.\n+\t */\n+\tu16 rss_lut_size;\n+\tu8 pad[6]; /*Future extension purpose*/\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_rx_queue_group_info);\n+\n+struct cpchnl2_tx_queue_group_info {\n+\tu8 tx_tc; /*TX TC queue group will be connected to*/\n+\t/* Each group can have its own priority, value 0-7, while each group with unique\n+\t * priority is strict priority. It can be single set of queue groups which configured with\n+\t * same priority, then they are assumed part of WFQ arbitration group and are expected to be\n+\t * assigned with weight.\n+\t */\n+\tu8 priority;\n+\t/* Determines if queue group is expected to be Strict Priority according to its priority */\n+\tu8 is_sp;\n+\tu8 pad;\n+\t/* Peak Info Rate Weight in case Queue Group is part of WFQ arbitration set.\n+\t * The weights of the groups are independent of each other. Possible values: 1-200.\n+\t */\n+\tu16 pir_weight;\n+\t/* Future extension purpose for CIR only */\n+\tu8 cir_pad[2];\n+\tu8 pad2[8]; /* Future extension purpose*/\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(16, cpchnl2_tx_queue_group_info);\n+\n+struct cpchnl2_queue_group_id {\n+\t/* Queue group ID - depended on it's type:\n+\t * Data & p2p - is an index which is relative to Vport.\n+\t * Config & Mailbox - is an ID which is relative to func.\n+\t * This ID is used in future calls, i.e. delete.\n+\t * Requested by host and assigned by Control plane.\n+\t */\n+\tu16 queue_group_id;\n+\t/* Functional type: see CPCHNL2_QUEUE_GROUP_TYPE definitions */\n+\tu16 queue_group_type;\n+\tu8 pad[4];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_queue_group_id);\n+\n+struct cpchnl2_queue_group_info {\n+\t/* IN */\n+\tstruct cpchnl2_queue_group_id qg_id;\n+\n+\t/* IN, Number of queues of different types in the group. */\n+\tu16 num_tx_q;\n+\tu16 num_tx_complq;\n+\tu16 num_rx_q;\n+\tu16 num_rx_bufq;\n+\n+\tstruct cpchnl2_tx_queue_group_info tx_q_grp_info;\n+\tstruct cpchnl2_rx_queue_group_info rx_q_grp_info;\n+\n+\tu8 egress_port;\n+\tu8 pad[39]; /*Future extension purpose*/\n+\tstruct cpchnl2_queue_grp_chunks chunks;\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(344, cpchnl2_queue_group_info);\n+\n+struct cpchnl2_queue_groups {\n+\tu16 num_queue_groups; /* Number of queue groups in struct below */\n+\tu8 pad[6];\n+\t/* group information , number is determined by param above */\n+\tstruct cpchnl2_queue_group_info groups[MAX_Q_VPORT_GROUPS];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(3792, cpchnl2_queue_groups);\n+\n+/**\n+ * @brief function types\n+ */\n+enum cpchnl2_func_type {\n+\tCPCHNL2_FTYPE_LAN_PF = 0,\n+\tCPCHNL2_FTYPE_LAN_VF = 1,\n+\tCPCHNL2_FTYPE_LAN_MAX\n+};\n+\n+/**\n+ * @brief containing vport id & type\n+ */\n+struct cpchnl2_vport_id {\n+\tu32 vport_id;\n+\tu16 vport_type;\n+\tu8 pad[2];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_vport_id);\n+\n+struct cpchnl2_func_id {\n+\t/* Function type: 0 - LAN PF, 1 - LAN VF, Rest - \"reserved\" */\n+\tu8 func_type;\n+\t/* Always relevant, indexing is according to LAN PE 0-15, while only 0-4 APFs\n+\t * and 8-12 CPFs are valid\n+\t */\n+\tu8 pf_id;\n+\t/* Valid only if \"type\" above is VF, indexing is relative to PF specified above. */\n+\tu16 vf_id;\n+\tu8 pad[4];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_func_id);\n+\n+/* Note! Do not change the fields and especially their order as should eventually\n+ * be aligned to 32bit. Must match the virtchnl structure definition.\n+ * If should change, change also the relevant FAS and virtchnl code, under permission.\n+ */\n+struct cpchnl2_vport_info {\n+\tu16 vport_index;\n+\t/* VSI index, global indexing aligned to HW.\n+\t * Index of HW VSI is allocated by HMA during \"CreateVport\" virtChnl command.\n+\t * Relevant for VSI backed Vports only, not relevant for vport_type = \"Qdev\".\n+\t */\n+\tu16 vsi_id;\n+\tu8 vport_status;\t/* enum cpchnl2_vport_status */\n+\t/* 0 - LAN PF, 1 - LAN VF. Rest - reserved. Can be later expanded to other PEs */\n+\tu8 func_type;\n+\t/* Valid only if \"type\" above is VF, indexing is relative to PF specified above. */\n+\tu16 vf_id;\n+\t/* Always relevant, indexing is according to LAN PE 0-15,\n+\t * while only 0-4 APFs and 8-12 CPFs are valid.\n+\t */\n+\tu8 pf_id;\n+\tu8 rss_enabled; /* if RSS is enabled for Vport. Driven by Node Policy. Currently '0' */\n+\t/* MAC Address assigned for this vport, all 0s for \"Qdev\" Vport type */\n+\tu8 mac_addr[CPCHNL2_ETH_LENGTH_OF_ADDRESS];\n+\tu16 vmrl_id;\n+\t/* Indicates if IMC created SEM MAC rule for this Vport.\n+\t * Currently this is done by IMC for all Vport of type \"Default\" only,\n+\t * but can be different in the future.\n+\t */\n+\tu8 sem_mac_rule_exist;\n+\t/* Bitmask to inform which TC is valid.\n+\t * 0x1 << TCnum. 1b: valid else 0.\n+\t * Driven by Node Policy on system level, then Sysetm level TCs are\n+\t * reported to IDPF and it can enable Vport level TCs on TX according\n+\t * to Syetm enabled ones.\n+\t * If TC aware mode - bit set for valid TC.\n+\t * otherwise =1 (only bit 0 is set. represents the VSI\n+\t */\n+\tu8 tx_tc_bitmask;\n+\t/* For each valid TC, TEID of VPORT node over TC in TX LAN WS.\n+\t * If TC aware mode - up to 8 TC TEIDs. Otherwise vport_tc_teid[0] shall hold VSI TEID\n+\t */\n+\tu32 vport_tc_teid[CPCHNL2_MAX_TC_AMOUNT];\n+\t/* For each valid TC, bandwidth in mbps.\n+\t * Default BW per Vport is from Node policy\n+\t * If TC aware mode -per TC. Otherwise, bandwidth[0] holds VSI bandwidth\n+\t */\n+\tu32 bandwidth[CPCHNL2_MAX_TC_AMOUNT];\n+\t/* From Node Policy. */\n+\tu16 max_mtu;\n+\tu16 default_rx_qid;\t/* Default LAN RX Queue ID */\n+\tu16 vport_flags; /* see: VPORT_FLAGS */\n+\tu8 egress_port;\n+\tu8 pad_reserved[5];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(96, cpchnl2_vport_info);\n+\n+/*\n+ * CPCHNL2_OP_GET_VPORT_LIST\n+ */\n+\n+/**\n+ * @brief Used for CPCHNL2_OP_GET_VPORT_LIST opcode request\n+ * @param func_type Func type: 0 - LAN_PF, 1 - LAN_VF. Rest - reserved (see enum cpchnl2_func_type)\n+ * @param pf_id Always relevant, indexing is according to LAN PE 0-15, while only 0-4 APFs and 8-12\n+ * CPFs are valid\n+ * @param vf_id Valid only if \"type\" above is VF, indexing is relative to PF specified above\n+ */\n+struct cpchnl2_get_vport_list_request {\n+\tu8 func_type;\n+\tu8 pf_id;\n+\tu16 vf_id;\n+\tu8 pad[4];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_get_vport_list_request);\n+\n+/**\n+ * @brief Used for CPCHNL2_OP_GET_VPORT_LIST opcode response\n+ * @param func_type Func type: 0 - LAN_PF, 1 - LAN_VF. Rest - reserved. Can be later extended to\n+ * other PE types\n+ * @param pf_id Always relevant, indexing is according to LAN PE 0-15, while only 0-4 APFs and 8-12\n+ * CPFs are valid\n+ * @param vf_id Valid only if \"type\" above is VF, indexing is relative to PF specified above\n+ * @param nof_vports Number of vports created on the function\n+ * @param vports array of the IDs and types. vport ID is elative to its func (PF/VF). same as in\n+ * Create Vport\n+ * vport_type: Aligned to VirtChnl types: Default, SIOV, etc.\n+ */\n+struct cpchnl2_get_vport_list_response {\n+\tu8 func_type;\n+\tu8 pf_id;\n+\tu16 vf_id;\n+\tu16 nof_vports;\n+\tu8 pad[2];\n+\tstruct cpchnl2_vport_id vports[];\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(8, cpchnl2_get_vport_list_response);\n+\n+/*\n+ * CPCHNL2_OP_GET_VPORT_INFO\n+ */\n+/**\n+ * @brief Used for CPCHNL2_OP_GET_VPORT_INFO opcode request\n+ * @param vport a structure containing vport_id (relative to function) and type\n+ * @param func a structure containing function type, pf_id, vf_id\n+ */\n+struct cpchnl2_get_vport_info_request {\n+\tstruct cpchnl2_vport_id vport;\n+\tstruct cpchnl2_func_id func;\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(16, cpchnl2_get_vport_info_request);\n+\n+/**\n+ * @brief Used for CPCHNL2_OP_GET_VPORT_INFO opcode response\n+ * @param vport a structure containing vport_id (relative to function) and type to get info for\n+ * @param info a structure all the information for a given vport\n+ * @param queue_groups a structure containing all the queue groups of the given vport\n+ */\n+struct cpchnl2_get_vport_info_response {\n+\tstruct cpchnl2_vport_id vport;\n+\tstruct cpchnl2_vport_info info;\n+\tstruct cpchnl2_queue_groups queue_groups;\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(3896, cpchnl2_get_vport_info_response);\n+\n+ /* Cpchnl events\n+ * Sends event message to inform the peer of notification that may affect it.\n+ * No direct response is expected from the peer, though it may generate other\n+ * messages in response to this one.\n+ */\n+enum cpchnl2_event {\n+\tCPCHNL2_EVENT_UNKNOWN = 0,\n+\tCPCHNL2_EVENT_VPORT_CREATED,\n+\tCPCHNL2_EVENT_VPORT_DESTROYED,\n+\tCPCHNL2_EVENT_VPORT_ENABLED,\n+\tCPCHNL2_EVENT_VPORT_DISABLED,\n+\tCPCHNL2_PKG_EVENT,\n+\tCPCHNL2_EVENT_ADD_QUEUE_GROUPS,\n+\tCPCHNL2_EVENT_DEL_QUEUE_GROUPS,\n+\tCPCHNL2_EVENT_ADD_QUEUES,\n+\tCPCHNL2_EVENT_DEL_QUEUES\n+};\n+\n+/*\n+ * This is for CPCHNL2_EVENT_VPORT_CREATED\n+ */\n+struct cpchnl2_event_vport_created {\n+\tstruct cpchnl2_vport_id vport; /* Vport identifier to point to specific Vport */\n+\tstruct cpchnl2_vport_info info; /* Vport configuration info */\n+\tstruct cpchnl2_queue_groups queue_groups; /* Vport assign queue groups configuration info */\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(3896, cpchnl2_event_vport_created);\n+\n+/*\n+ * This is for CPCHNL2_EVENT_VPORT_DESTROYED\n+ */\n+struct cpchnl2_event_vport_destroyed {\n+\t/* Vport identifier to point to specific Vport */\n+\tstruct cpchnl2_vport_id vport;\n+\tstruct cpchnl2_func_id func;\n+};\n+CPCHNL2_CHECK_STRUCT_LEN(16, cpchnl2_event_vport_destroyed);\n+\n+struct cpchnl2_event_info {\n+\tstruct {\n+\t\ts32 type;\t\t/* See enum cpchnl2_event */\n+\t\tuint8_t reserved[4];\t/* Reserved */\n+\t} header;\n+\tunion {\n+\t\tstruct cpchnl2_event_vport_created vport_created;\n+\t\tstruct cpchnl2_event_vport_destroyed vport_destroyed;\n+\t} data;\n+};\n+\n+#endif /* _CPFL_CPCHNL_H_ */\n", "prefixes": [ "v5", "04/10" ] }