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GET /api/patches/131188/?format=api
{ "id": 131188, "url": "http://patches.dpdk.org/api/patches/131188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230906093407.3635038-5-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230906093407.3635038-5-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230906093407.3635038-5-wenjing.qiao@intel.com", "date": "2023-09-06T09:34:02", "name": "[v3,4/9] net/cpfl: setup ctrl path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "81a8e5b6e71ec2f539ebbd47b8063acbd62476ee", "submitter": { "id": 2680, "url": "http://patches.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230906093407.3635038-5-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 29433, "url": "http://patches.dpdk.org/api/series/29433/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29433", "date": "2023-09-06T09:33:58", "name": "add rte flow support for cpfl", "version": 3, "mbox": "http://patches.dpdk.org/series/29433/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131188/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C11E942528;\n\tWed, 6 Sep 2023 11:34:57 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 903A3402E3;\n\tWed, 6 Sep 2023 11:34:34 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 54DD44027C\n for <dev@dpdk.org>; Wed, 6 Sep 2023 11:34:32 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Sep 2023 02:34:32 -0700", "from dpdk-wenjing-02.sh.intel.com ([10.67.119.75])\n by fmsmga001.fm.intel.com with ESMTP; 06 Sep 2023 02:34:19 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1693992872; x=1725528872;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=LvIu2jalOFBUNS2GHr0trWYS6oGZ2VWbpGgznkis4vE=;\n b=jpWm4818R5AvX8UBJ49yP/Amh5sSdVly+MuIy4lxlqAzpT9rxijGdwgG\n GEjDHMRj2FU3/8rCv7bItyiqplgRn8BZ9TUWmeq6cQlUokbG9ANdbzYNe\n js6SwNuQ2Ciy0NcEDOTTP2P/0VLRCYlvKGcG7qhbJyyh1MsSloqMhSRrL\n AoDpsdNj3tzCJ12UXqXpgqI8h8c/gHTgJDgXsVy28IwDuvuM9sqEjEcfO\n PsTKhvK8jxG8g2av2/Q8cXyHKvrSBHJYrnfnozYVmyksbOMnL0GSkH1RW\n ixFWkH7N5KATPoZTANv8JJHHw3OdTHEZ7/30Jmcs8/x+Eii3hwiYjU2S+ Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10824\"; a=\"375919365\"", "E=Sophos;i=\"6.02,231,1688454000\"; d=\"scan'208\";a=\"375919365\"", "E=McAfee;i=\"6600,9927,10824\"; a=\"884623175\"", "E=Sophos;i=\"6.02,231,1688454000\"; d=\"scan'208\";a=\"884623175\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com,\n jingjing.wu@intel.com, beilei.xing@intel.com", "Cc": "mingxia.liu@intel.com,\n\tWenjing Qiao <wenjing.qiao@intel.com>", "Subject": "[PATCH v3 4/9] net/cpfl: setup ctrl path", "Date": "Wed, 6 Sep 2023 09:34:02 +0000", "Message-Id": "<20230906093407.3635038-5-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230906093407.3635038-1-wenjing.qiao@intel.com>", "References": "<20230901113158.1654044-1-yuying.zhang@intel.com>\n <20230906093407.3635038-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Setup the control vport and control queue for flow offloading.\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 267 +++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_ethdev.h | 14 ++\n drivers/net/cpfl/cpfl_vchnl.c | 144 ++++++++++++++++++\n 3 files changed, 425 insertions(+)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 3c4a6a4724..22f3e72894 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -1657,6 +1657,10 @@ cpfl_handle_vchnl_event_msg(struct cpfl_adapter_ext *adapter, uint8_t *msg, uint\n \t\treturn;\n \t}\n \n+\t/* ignore if it is ctrl vport */\n+\tif (adapter->ctrl_vport.base.vport_id == vc_event->vport_id)\n+\t\treturn;\n+\n \tvport = cpfl_find_vport(adapter, vc_event->vport_id);\n \tif (!vport) {\n \t\tPMD_DRV_LOG(ERR, \"Can't find vport.\");\n@@ -1852,6 +1856,260 @@ cpfl_dev_alarm_handler(void *param)\n \trte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter);\n }\n \n+static int\n+cpfl_stop_cfgqs(struct cpfl_adapter_ext *adapter)\n+{\n+\tint i, ret;\n+\n+\tfor (i = 0; i < CPFL_TX_CFGQ_NUM; i++) {\n+\t\tret = idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false, false);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to disable Tx config queue.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < CPFL_RX_CFGQ_NUM; i++) {\n+\t\tret = idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true, false);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to disable Rx config queue.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_start_cfgqs(struct cpfl_adapter_ext *adapter)\n+{\n+\tint i, ret;\n+\n+\tret = cpfl_config_ctlq_tx(adapter);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Tx config queue.\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = cpfl_config_ctlq_rx(adapter);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Rx config queue.\");\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < CPFL_TX_CFGQ_NUM; i++) {\n+\t\tret = idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false, true);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to enable Tx config queue.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < CPFL_RX_CFGQ_NUM; i++) {\n+\t\tret = idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true, true);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to enable Rx config queue.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+cpfl_remove_cfgqs(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct idpf_hw *hw = (struct idpf_hw *)(&adapter->base.hw);\n+\tstruct cpfl_ctlq_create_info *create_cfgq_info;\n+\tint i;\n+\n+\tcreate_cfgq_info = adapter->cfgq_info;\n+\n+\tfor (i = 0; i < CPFL_CFGQ_NUM; i++) {\n+\t\tcpfl_vport_ctlq_remove(hw, adapter->ctlqp[i]);\n+\t\tif (create_cfgq_info[i].ring_mem.va)\n+\t\t\tidpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].ring_mem);\n+\t\tif (create_cfgq_info[i].buf_mem.va)\n+\t\t\tidpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].buf_mem);\n+\t}\n+}\n+\n+static int\n+cpfl_add_cfgqs(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct idpf_ctlq_info *cfg_cq;\n+\tint ret = 0;\n+\tint i = 0;\n+\n+\tfor (i = 0; i < CPFL_CFGQ_NUM; i++) {\n+\t\tret = cpfl_vport_ctlq_add((struct idpf_hw *)(&adapter->base.hw),\n+\t\t\t\t\t &adapter->cfgq_info[i],\n+\t\t\t\t\t &cfg_cq);\n+\t\tif (ret || !cfg_cq) {\n+\t\t\tPMD_DRV_LOG(ERR, \"ctlq add failed for queue id: %d\",\n+\t\t\t\t adapter->cfgq_info[i].id);\n+\t\t\tcpfl_remove_cfgqs(adapter);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tPMD_DRV_LOG(INFO, \"added cfgq to hw. queue id: %d\",\n+\t\t\t adapter->cfgq_info[i].id);\n+\t\tadapter->ctlqp[i] = cfg_cq;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#define CPFL_CFGQ_RING_LEN\t\t512\n+#define CPFL_CFGQ_DESCRIPTOR_SIZE\t32\n+#define CPFL_CFGQ_BUFFER_SIZE\t\t256\n+#define CPFL_CFGQ_RING_SIZE\t\t512\n+\n+static int\n+cpfl_cfgq_setup(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_ctlq_create_info *create_cfgq_info;\n+\tstruct cpfl_vport *vport;\n+\tint i, err;\n+\tuint32_t ring_size = CPFL_CFGQ_RING_SIZE * sizeof(struct idpf_ctlq_desc);\n+\tuint32_t buf_size = CPFL_CFGQ_RING_SIZE * CPFL_CFGQ_BUFFER_SIZE;\n+\n+\tvport = &adapter->ctrl_vport;\n+\tcreate_cfgq_info = adapter->cfgq_info;\n+\n+\tfor (i = 0; i < CPFL_CFGQ_NUM; i++) {\n+\t\tif (i % 2 == 0) {\n+\t\t\t/* Setup Tx config queue */\n+\t\t\tcreate_cfgq_info[i].id = vport->base.chunks_info.tx_start_qid + i / 2;\n+\t\t\tcreate_cfgq_info[i].type = IDPF_CTLQ_TYPE_CONFIG_TX;\n+\t\t\tcreate_cfgq_info[i].len = CPFL_CFGQ_RING_SIZE;\n+\t\t\tcreate_cfgq_info[i].buf_size = CPFL_CFGQ_BUFFER_SIZE;\n+\t\t\tmemset(&create_cfgq_info[i].reg, 0, sizeof(struct idpf_ctlq_reg));\n+\t\t\tcreate_cfgq_info[i].reg.tail = vport->base.chunks_info.tx_qtail_start +\n+\t\t\t\ti / 2 * vport->base.chunks_info.tx_qtail_spacing;\n+\t\t} else {\n+\t\t\t/* Setup Rx config queue */\n+\t\t\tcreate_cfgq_info[i].id = vport->base.chunks_info.rx_start_qid + i / 2;\n+\t\t\tcreate_cfgq_info[i].type = IDPF_CTLQ_TYPE_CONFIG_RX;\n+\t\t\tcreate_cfgq_info[i].len = CPFL_CFGQ_RING_SIZE;\n+\t\t\tcreate_cfgq_info[i].buf_size = CPFL_CFGQ_BUFFER_SIZE;\n+\t\t\tmemset(&create_cfgq_info[i].reg, 0, sizeof(struct idpf_ctlq_reg));\n+\t\t\tcreate_cfgq_info[i].reg.tail = vport->base.chunks_info.rx_qtail_start +\n+\t\t\t\ti / 2 * vport->base.chunks_info.rx_qtail_spacing;\n+\t\t\tif (!idpf_alloc_dma_mem(&adapter->base.hw, &create_cfgq_info[i].buf_mem,\n+\t\t\t\t\t\tbuf_size)) {\n+\t\t\t\terr = -ENOMEM;\n+\t\t\t\tgoto free_mem;\n+\t\t\t}\n+\t\t}\n+\t\tif (!idpf_alloc_dma_mem(&adapter->base.hw, &create_cfgq_info[i].ring_mem,\n+\t\t\t\t\tring_size)) {\n+\t\t\terr = -ENOMEM;\n+\t\t\tgoto free_mem;\n+\t\t}\n+\t}\n+\treturn 0;\n+free_mem:\n+\tfor (i = 0; i < CPFL_CFGQ_NUM; i++) {\n+\t\tif (create_cfgq_info[i].ring_mem.va)\n+\t\t\tidpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].ring_mem);\n+\t\tif (create_cfgq_info[i].buf_mem.va)\n+\t\t\tidpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].buf_mem);\n+\t}\n+\treturn err;\n+}\n+\n+static int\n+cpfl_init_ctrl_vport(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_vport *vport = &adapter->ctrl_vport;\n+\tstruct virtchnl2_create_vport *vport_info =\n+\t\t(struct virtchnl2_create_vport *)adapter->ctrl_vport_recv_info;\n+\tint i;\n+\n+\tvport->itf.adapter = adapter;\n+\tvport->base.adapter = &adapter->base;\n+\tvport->base.vport_id = vport_info->vport_id;\n+\n+\tfor (i = 0; i < vport_info->chunks.num_chunks; i++) {\n+\t\tif (vport_info->chunks.chunks[i].type == VIRTCHNL2_QUEUE_TYPE_TX) {\n+\t\t\tvport->base.chunks_info.tx_start_qid =\n+\t\t\t\tvport_info->chunks.chunks[i].start_queue_id;\n+\t\t\tvport->base.chunks_info.tx_qtail_start =\n+\t\t\tvport_info->chunks.chunks[i].qtail_reg_start;\n+\t\t\tvport->base.chunks_info.tx_qtail_spacing =\n+\t\t\tvport_info->chunks.chunks[i].qtail_reg_spacing;\n+\t\t} else if (vport_info->chunks.chunks[i].type == VIRTCHNL2_QUEUE_TYPE_RX) {\n+\t\t\tvport->base.chunks_info.rx_start_qid =\n+\t\t\t\tvport_info->chunks.chunks[i].start_queue_id;\n+\t\t\tvport->base.chunks_info.rx_qtail_start =\n+\t\t\tvport_info->chunks.chunks[i].qtail_reg_start;\n+\t\t\tvport->base.chunks_info.rx_qtail_spacing =\n+\t\t\tvport_info->chunks.chunks[i].qtail_reg_spacing;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(ERR, \"Unsupported chunk type\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+cpfl_ctrl_path_close(struct cpfl_adapter_ext *adapter)\n+{\n+\tcpfl_remove_cfgqs(adapter);\n+\tcpfl_stop_cfgqs(adapter);\n+\tidpf_vc_vport_destroy(&adapter->ctrl_vport.base);\n+}\n+\n+static int\n+cpfl_ctrl_path_open(struct cpfl_adapter_ext *adapter)\n+{\n+\tint ret;\n+\n+\tret = cpfl_vc_create_ctrl_vport(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to create control vport\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = cpfl_init_ctrl_vport(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init control vport\");\n+\t\tgoto err_init_ctrl_vport;\n+\t}\n+\n+\tret = cpfl_cfgq_setup(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to setup control queues\");\n+\t\tgoto err_cfgq_setup;\n+\t}\n+\n+\tret = cpfl_add_cfgqs(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to add control queues\");\n+\t\tgoto err_add_cfgq;\n+\t}\n+\n+\tret = cpfl_start_cfgqs(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to start control queues\");\n+\t\tgoto err_start_cfgqs;\n+\t}\n+\n+\treturn 0;\n+\n+err_start_cfgqs:\n+\tcpfl_stop_cfgqs(adapter);\n+err_add_cfgq:\n+\tcpfl_remove_cfgqs(adapter);\n+err_cfgq_setup:\n+err_init_ctrl_vport:\n+\tidpf_vc_vport_destroy(&adapter->ctrl_vport.base);\n+\n+\treturn ret;\n+}\n+\n static struct virtchnl2_get_capabilities req_caps = {\n \t.csum_caps =\n \tVIRTCHNL2_CAP_TX_CSUM_L3_IPV4 |\n@@ -2019,6 +2277,12 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a\n \t\tgoto err_vports_alloc;\n \t}\n \n+\tret = cpfl_ctrl_path_open(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to setup control path\");\n+\t\tgoto err_create_ctrl_vport;\n+\t}\n+\n \tadapter->cur_vports = 0;\n \tadapter->cur_vport_nb = 0;\n \n@@ -2026,6 +2290,8 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a\n \n \treturn ret;\n \n+err_create_ctrl_vport:\n+\trte_free(adapter->vports);\n err_vports_alloc:\n \trte_eal_alarm_cancel(cpfl_dev_alarm_handler, adapter);\n \tcpfl_repr_whitelist_uninit(adapter);\n@@ -2260,6 +2526,7 @@ cpfl_find_adapter_ext(struct rte_pci_device *pci_dev)\n static void\n cpfl_adapter_ext_deinit(struct cpfl_adapter_ext *adapter)\n {\n+\tcpfl_ctrl_path_close(adapter);\n \trte_eal_alarm_cancel(cpfl_dev_alarm_handler, adapter);\n \tcpfl_vport_map_uninit(adapter);\n \tidpf_adapter_deinit(&adapter->base);\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex 2151605987..40bba8da00 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -22,6 +22,7 @@\n #include \"cpfl_logs.h\"\n #include \"cpfl_cpchnl.h\"\n #include \"cpfl_representor.h\"\n+#include \"cpfl_controlq.h\"\n \n /* Currently, backend supports up to 8 vports */\n #define CPFL_MAX_VPORT_NUM\t8\n@@ -89,6 +90,10 @@\n \n #define CPFL_FLOW_FILE_LEN 100\n \n+#define CPFL_RX_CFGQ_NUM\t4\n+#define CPFL_TX_CFGQ_NUM\t4\n+#define CPFL_CFGQ_NUM\t\t8\n+\n #define CPFL_INVALID_HW_ID\tUINT16_MAX\n #define CPFL_META_CHUNK_LENGTH\t1024\n #define CPFL_META_LENGTH\t32\n@@ -204,11 +209,20 @@ struct cpfl_adapter_ext {\n \trte_spinlock_t repr_lock;\n \tstruct rte_hash *repr_whitelist_hash;\n \n+\t/* ctrl vport and ctrl queues. */\n+\tstruct cpfl_vport ctrl_vport;\n+\tuint8_t ctrl_vport_recv_info[IDPF_DFLT_MBX_BUF_SIZE];\n+\tstruct idpf_ctlq_info *ctlqp[CPFL_CFGQ_NUM];\n+\tstruct cpfl_ctlq_create_info cfgq_info[CPFL_CFGQ_NUM];\n+\n \tstruct cpfl_metadata meta;\n };\n \n TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext);\n \n+int cpfl_vc_create_ctrl_vport(struct cpfl_adapter_ext *adapter);\n+int cpfl_config_ctlq_rx(struct cpfl_adapter_ext *adapter);\n+int cpfl_config_ctlq_tx(struct cpfl_adapter_ext *adapter);\n int cpfl_vport_info_create(struct cpfl_adapter_ext *adapter,\n \t\t\t struct cpfl_vport_id *vport_identity,\n \t\t\t struct cpchnl2_vport_info *vport_info);\ndiff --git a/drivers/net/cpfl/cpfl_vchnl.c b/drivers/net/cpfl/cpfl_vchnl.c\nindex a21a4a451f..932840a972 100644\n--- a/drivers/net/cpfl/cpfl_vchnl.c\n+++ b/drivers/net/cpfl/cpfl_vchnl.c\n@@ -70,3 +70,147 @@ cpfl_cc_vport_info_get(struct cpfl_adapter_ext *adapter,\n \n \treturn 0;\n }\n+\n+int\n+cpfl_vc_create_ctrl_vport(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct virtchnl2_create_vport vport_msg;\n+\tstruct idpf_cmd_info args;\n+\tint err = -1;\n+\n+\tmemset(&vport_msg, 0, sizeof(struct virtchnl2_create_vport));\n+\tvport_msg.vport_type = rte_cpu_to_le_16(VIRTCHNL2_VPORT_TYPE_DEFAULT);\n+\tvport_msg.txq_model = rte_cpu_to_le_16(VIRTCHNL2_QUEUE_MODEL_SINGLE);\n+\tvport_msg.rxq_model = rte_cpu_to_le_16(VIRTCHNL2_QUEUE_MODEL_SINGLE);\n+\tvport_msg.num_tx_q = CPFL_TX_CFGQ_NUM;\n+\tvport_msg.num_tx_complq = 0;\n+\tvport_msg.num_rx_q = CPFL_RX_CFGQ_NUM;\n+\tvport_msg.num_rx_bufq = 0;\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CREATE_VPORT;\n+\targs.in_args = (uint8_t *)&vport_msg;\n+\targs.in_args_size = sizeof(vport_msg);\n+\targs.out_buffer = adapter->base.mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_vc_cmd_execute(&adapter->base, &args);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Failed to execute command of VIRTCHNL2_OP_CREATE_VPORT\");\n+\t\treturn err;\n+\t}\n+\n+\trte_memcpy(adapter->ctrl_vport_recv_info, args.out_buffer,\n+\t\t IDPF_DFLT_MBX_BUF_SIZE);\n+\treturn err;\n+}\n+\n+int\n+cpfl_config_ctlq_rx(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_vport *vport = &adapter->ctrl_vport;\n+\tstruct virtchnl2_config_rx_queues *vc_rxqs = NULL;\n+\tstruct virtchnl2_rxq_info *rxq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err, i;\n+\n+\tif (vport->base.rxq_model != VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\tPMD_DRV_LOG(ERR, \"This rxq model isn't supported.\");\n+\t\terr = -EINVAL;\n+\t\treturn err;\n+\t}\n+\n+\tnum_qs = CPFL_RX_CFGQ_NUM;\n+\tsize = sizeof(*vc_rxqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_rxq_info);\n+\tvc_rxqs = rte_zmalloc(\"cfg_rxqs\", size, 0);\n+\tif (!vc_rxqs) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_rx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_rxqs->vport_id = vport->base.vport_id;\n+\tvc_rxqs->num_qinfo = num_qs;\n+\n+\tfor (i = 0; i < num_qs; i++) {\n+\t\trxq_info = &vc_rxqs->qinfo[i];\n+\t\trxq_info->dma_ring_addr = adapter->ctlqp[2 * i + 1]->desc_ring.pa;\n+\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_CONFIG_RX;\n+\t\trxq_info->queue_id = adapter->cfgq_info[2 * i + 1].id;\n+\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\trxq_info->data_buffer_size = adapter->cfgq_info[2 * i + 1].buf_size;\n+\t\trxq_info->max_pkt_size = vport->base.max_pkt_len;\n+\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M;\n+\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\t\trxq_info->ring_len = adapter->cfgq_info[2 * i + 1].len;\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_rxqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->base.mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_vc_cmd_execute(&adapter->base, &args);\n+\trte_free(vc_rxqs);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES\");\n+\n+\treturn err;\n+}\n+\n+int\n+cpfl_config_ctlq_tx(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_vport *vport = &adapter->ctrl_vport;\n+\tstruct virtchnl2_config_tx_queues *vc_txqs = NULL;\n+\tstruct virtchnl2_txq_info *txq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err, i;\n+\n+\tif (vport->base.txq_model != VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\tPMD_DRV_LOG(ERR, \"This txq model isn't supported.\");\n+\t\terr = -EINVAL;\n+\t\treturn err;\n+\t}\n+\n+\tnum_qs = CPFL_TX_CFGQ_NUM;\n+\tsize = sizeof(*vc_txqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_txq_info);\n+\tvc_txqs = rte_zmalloc(\"cfg_txqs\", size, 0);\n+\tif (!vc_txqs) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_tx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_txqs->vport_id = vport->base.vport_id;\n+\tvc_txqs->num_qinfo = num_qs;\n+\n+\tfor (i = 0; i < num_qs; i++) {\n+\t\ttxq_info = &vc_txqs->qinfo[i];\n+\t\ttxq_info->dma_ring_addr = adapter->ctlqp[2 * i]->desc_ring.pa;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_CONFIG_TX;\n+\t\ttxq_info->queue_id = adapter->cfgq_info[2 * i].id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_QUEUE;\n+\t\ttxq_info->ring_len = adapter->cfgq_info[2 * i].len;\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_txqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->base.mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_vc_cmd_execute(&adapter->base, &args);\n+\trte_free(vc_txqs);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES\");\n+\n+\treturn err;\n+}\n", "prefixes": [ "v3", "4/9" ] }