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GET /api/patches/130170/?format=api
{ "id": 130170, "url": "http://patches.dpdk.org/api/patches/130170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/10660b2852115b92ccc6cc193c5b693183217a80.1691768110.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<10660b2852115b92ccc6cc193c5b693183217a80.1691768110.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/10660b2852115b92ccc6cc193c5b693183217a80.1691768110.git.anatoly.burakov@intel.com", "date": "2023-08-11T16:14:45", "name": "[v1,2/3] dma/idxd: implement inter-domain operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b3b36b5cb5e1d86245182e1a51fd45988cece8c", "submitter": { "id": 4, "url": "http://patches.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/10660b2852115b92ccc6cc193c5b693183217a80.1691768110.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 29192, "url": "http://patches.dpdk.org/api/series/29192/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29192", "date": "2023-08-11T16:14:43", "name": "Add support for inter-domain DMA operations", "version": 1, "mbox": "http://patches.dpdk.org/series/29192/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130170/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/130170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E586E43036;\n\tFri, 11 Aug 2023 18:15:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 899E543263;\n\tFri, 11 Aug 2023 18:14:56 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 605E24325B\n for <dev@dpdk.org>; Fri, 11 Aug 2023 18:14:54 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Aug 2023 09:14:53 -0700", "from silpixa00401191.ir.intel.com ([10.55.128.139])\n by orsmga005.jf.intel.com with ESMTP; 11 Aug 2023 09:14:52 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1691770494; x=1723306494;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=uMB5kj5+vSi1VMbevPMCWbbdcZkECN8Da0bbS0rZozI=;\n b=jCaHpwKupvN2hsiRSxzJDS7zHW8g+xDrMQHppoyFwsQDfXv4xf1OhVpp\n 1yCJXI+HbsH+YAtx16IVCLteYkUrPeJrhyI4pAu7rr7uK5VwAfAGZXfED\n PAN/zMfgtfqIuOW2knHrRR+JWtGoQ1mRQyJ3o7kPXz0fgAWwbuQc9UhPl\n RHiEM9QUzpLH9LzYp2xnzRvDDcuuMamzO97Q1B5n5vKfD7opVrLER/ARb\n DqYqRzlJ2uSOFZBWqcbzWIM9rAwTLyiigcZIzs+TrPEoJxTyN4Zk2fbeH\n ZxAy3InV3Yry/0avWxDzRg6h/BoILKOtWt3wOfRTCiczwKsClKTqM4iWK w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10799\"; a=\"351312941\"", "E=Sophos;i=\"6.01,166,1684825200\"; d=\"scan'208\";a=\"351312941\"", "E=McAfee;i=\"6600,9927,10799\"; a=\"906499504\"", "E=Sophos;i=\"6.01,166,1684825200\"; d=\"scan'208\";a=\"906499504\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org, Chengwen Feng <fengchengwen@huawei.com>,\n Kevin Laatz <kevin.laatz@intel.com>,\n Bruce Richardson <bruce.richardson@intel.com>", "Cc": "Vladimir Medvedkin <vladimir.medvedkin@intel.com>", "Subject": "[PATCH v1 2/3] dma/idxd: implement inter-domain operations", "Date": "Fri, 11 Aug 2023 16:14:45 +0000", "Message-Id": "\n <10660b2852115b92ccc6cc193c5b693183217a80.1691768110.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1691768109.git.anatoly.burakov@intel.com>", "References": "<cover.1691768109.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implement inter-domain copy and fill operations defined in the newly\nadded DMA device API.\n\nSigned-off-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n doc/guides/prog_guide/dmadev.rst | 4 +\n drivers/dma/idxd/idxd_bus.c | 35 +++++++++\n drivers/dma/idxd/idxd_common.c | 123 +++++++++++++++++++++++++++----\n drivers/dma/idxd/idxd_hw_defs.h | 14 +++-\n drivers/dma/idxd/idxd_internal.h | 7 ++\n 5 files changed, 165 insertions(+), 18 deletions(-)", "diff": "diff --git a/doc/guides/prog_guide/dmadev.rst b/doc/guides/prog_guide/dmadev.rst\nindex e4e5196416..c2a957e971 100644\n--- a/doc/guides/prog_guide/dmadev.rst\n+++ b/doc/guides/prog_guide/dmadev.rst\n@@ -126,6 +126,10 @@ destination PASID to perform the operation. When `src_handle` value is set,\n Currently, source and destination handles are opaque values the user has to get\n from private API's of those DMA device drivers that support the operation.\n \n+List of drivers supporting inter-domain operations:\n+\n+- Intel(R) IDXD driver\n+\n \n Querying Device Statistics\n ~~~~~~~~~~~~~~~~~~~~~~~~~~\ndiff --git a/drivers/dma/idxd/idxd_bus.c b/drivers/dma/idxd/idxd_bus.c\nindex 3b2d4c2b65..787bc4e2d7 100644\n--- a/drivers/dma/idxd/idxd_bus.c\n+++ b/drivers/dma/idxd/idxd_bus.c\n@@ -7,6 +7,7 @@\n #include <unistd.h>\n #include <sys/mman.h>\n #include <libgen.h>\n+#include <inttypes.h>\n \n #include <bus_driver.h>\n #include <dev_driver.h>\n@@ -187,6 +188,31 @@ read_wq_int(struct rte_dsa_device *dev, const char *filename,\n \treturn ret;\n }\n \n+static int\n+read_gen_cap(struct rte_dsa_device *dev, uint64_t *gen_cap)\n+{\n+\tchar sysfs_node[PATH_MAX];\n+\tFILE *f;\n+\n+\tsnprintf(sysfs_node, sizeof(sysfs_node), \"%s/dsa%d/gen_cap\",\n+\t\tdsa_get_sysfs_path(), dev->addr.device_id);\n+\tf = fopen(sysfs_node, \"r\");\n+\tif (f == NULL) {\n+\t\tIDXD_PMD_ERR(\"%s(): opening file '%s' failed: %s\",\n+\t\t\t\t__func__, sysfs_node, strerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\tif (fscanf(f, \"%\" PRIx64, gen_cap) != 1) {\n+\t\tIDXD_PMD_ERR(\"%s(): error reading file '%s': %s\",\n+\t\t\t\t__func__, sysfs_node, strerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\tfclose(f);\n+\treturn 0;\n+}\n+\n static int\n read_device_int(struct rte_dsa_device *dev, const char *filename,\n \t\tint *value)\n@@ -219,6 +245,7 @@ idxd_probe_dsa(struct rte_dsa_device *dev)\n {\n \tstruct idxd_dmadev idxd = {0};\n \tint ret = 0;\n+\tuint64_t gen_cap;\n \n \tIDXD_PMD_INFO(\"Probing device %s on numa node %d\",\n \t\t\tdev->wq_name, dev->device.numa_node);\n@@ -232,6 +259,14 @@ idxd_probe_dsa(struct rte_dsa_device *dev)\n \tidxd.u.bus.dsa_id = dev->addr.device_id;\n \tidxd.sva_support = 1;\n \n+\tret = read_gen_cap(dev, &gen_cap);\n+\tif (ret) {\n+\t\tIDXD_PMD_ERR(\"Failed to read gen_cap for %s\", dev->wq_name);\n+\t\treturn ret;\n+\t}\n+\tif (gen_cap & IDXD_INTERDOM_SUPPORT)\n+\t\tidxd.inter_dom_support = 1;\n+\n \tidxd.portal = idxd_bus_mmap_wq(dev);\n \tif (idxd.portal == NULL) {\n \t\tIDXD_PMD_ERR(\"WQ mmap failed\");\ndiff --git a/drivers/dma/idxd/idxd_common.c b/drivers/dma/idxd/idxd_common.c\nindex 83d53942eb..ffe8614d16 100644\n--- a/drivers/dma/idxd/idxd_common.c\n+++ b/drivers/dma/idxd/idxd_common.c\n@@ -41,7 +41,57 @@ __idxd_movdir64b(volatile void *dst, const struct idxd_hw_desc *src)\n \n __use_avx2\n static __rte_always_inline void\n-__submit(struct idxd_dmadev *idxd)\n+__idxd_enqcmd(volatile void *dst, const struct idxd_hw_desc *src)\n+{\n+\tasm volatile (\".byte 0xf2, 0x0f, 0x38, 0xf8, 0x02\"\n+\t\t\t:\n+\t\t\t: \"a\" (dst), \"d\" (src)\n+\t\t\t: \"memory\");\n+}\n+\n+static inline uint32_t\n+__idxd_get_inter_dom_flags(const enum rte_idxd_ops op)\n+{\n+\tswitch (op) {\n+\tcase idxd_op_memmove:\n+\t\treturn IDXD_FLAG_SRC_ALT_PASID | IDXD_FLAG_DST_ALT_PASID;\n+\tcase idxd_op_fill:\n+\t\treturn IDXD_FLAG_DST_ALT_PASID;\n+\tdefault:\n+\t\t/* no flags needed */\n+\t\treturn 0;\n+\t}\n+}\n+\n+static inline uint32_t\n+__idxd_get_op_flags(enum rte_idxd_ops op, uint64_t flags, bool inter_dom)\n+{\n+\tuint32_t op_flags = op;\n+\tuint32_t flag_mask = IDXD_FLAG_FENCE;\n+\tif (inter_dom) {\n+\t\tflag_mask |= __idxd_get_inter_dom_flags(op);\n+\t\top_flags |= idxd_op_inter_dom;\n+\t}\n+\top_flags = op_flags << IDXD_CMD_OP_SHIFT;\n+\treturn op_flags | (flags & flag_mask) | IDXD_FLAG_CACHE_CONTROL;\n+}\n+\n+static inline uint64_t\n+__idxd_get_alt_pasid(uint64_t flags, uint64_t src_idpte_id,\n+\t\tuint64_t dst_idpte_id)\n+{\n+\t/* hardware is intolerant to inactive fields being non-zero */\n+\tif (!(flags & RTE_DMA_OP_FLAG_SRC_HANDLE))\n+\t\tsrc_idpte_id = 0;\n+\tif (!(flags & RTE_DMA_OP_FLAG_DST_HANDLE))\n+\t\tdst_idpte_id = 0;\n+\treturn (src_idpte_id << IDXD_CMD_DST_IDPTE_IDX_SHIFT) |\n+\t\t\t(dst_idpte_id << IDXD_CMD_DST_IDPTE_IDX_SHIFT);\n+}\n+\n+__use_avx2\n+static __rte_always_inline void\n+__submit(struct idxd_dmadev *idxd, const bool use_enqcmd)\n {\n \trte_prefetch1(&idxd->batch_comp_ring[idxd->batch_idx_read]);\n \n@@ -59,7 +109,10 @@ __submit(struct idxd_dmadev *idxd)\n \t\tdesc.completion = comp_addr;\n \t\tdesc.op_flags |= IDXD_FLAG_REQUEST_COMPLETION;\n \t\t_mm_sfence(); /* fence before writing desc to device */\n-\t\t__idxd_movdir64b(idxd->portal, &desc);\n+\t\tif (use_enqcmd)\n+\t\t\t__idxd_enqcmd(idxd->portal, &desc);\n+\t\telse\n+\t\t\t__idxd_movdir64b(idxd->portal, &desc);\n \t} else {\n \t\tconst struct idxd_hw_desc batch_desc = {\n \t\t\t\t.op_flags = (idxd_op_batch << IDXD_CMD_OP_SHIFT) |\n@@ -71,7 +124,10 @@ __submit(struct idxd_dmadev *idxd)\n \t\t\t\t.size = idxd->batch_size,\n \t\t};\n \t\t_mm_sfence(); /* fence before writing desc to device */\n-\t\t__idxd_movdir64b(idxd->portal, &batch_desc);\n+\t\tif (use_enqcmd)\n+\t\t\t__idxd_enqcmd(idxd->portal, &batch_desc);\n+\t\telse\n+\t\t\t__idxd_movdir64b(idxd->portal, &batch_desc);\n \t}\n \n \tif (++idxd->batch_idx_write > idxd->max_batches)\n@@ -93,7 +149,9 @@ __idxd_write_desc(struct idxd_dmadev *idxd,\n \t\tconst rte_iova_t src,\n \t\tconst rte_iova_t dst,\n \t\tconst uint32_t size,\n-\t\tconst uint32_t flags)\n+\t\tconst uint32_t flags,\n+\t\tconst uint64_t alt_pasid,\n+\t\tconst bool use_enqcmd)\n {\n \tuint16_t mask = idxd->desc_ring_mask;\n \tuint16_t job_id = idxd->batch_start + idxd->batch_size;\n@@ -113,14 +171,14 @@ __idxd_write_desc(struct idxd_dmadev *idxd,\n \t_mm256_store_si256((void *)&idxd->desc_ring[write_idx],\n \t\t\t_mm256_set_epi64x(dst, src, comp_addr, op_flags64));\n \t_mm256_store_si256((void *)&idxd->desc_ring[write_idx].size,\n-\t\t\t_mm256_set_epi64x(0, 0, 0, size));\n+\t\t\t_mm256_set_epi64x(alt_pasid, 0, 0, size));\n \n \tidxd->batch_size++;\n \n \trte_prefetch0_write(&idxd->desc_ring[write_idx + 1]);\n \n \tif (flags & RTE_DMA_OP_FLAG_SUBMIT)\n-\t\t__submit(idxd);\n+\t\t__submit(idxd, use_enqcmd);\n \n \treturn job_id;\n }\n@@ -134,10 +192,26 @@ idxd_enqueue_copy(void *dev_private, uint16_t qid __rte_unused, rte_iova_t src,\n \t * but check it at compile time to be sure.\n \t */\n \tRTE_BUILD_BUG_ON(RTE_DMA_OP_FLAG_FENCE != IDXD_FLAG_FENCE);\n-\tuint32_t memmove = (idxd_op_memmove << IDXD_CMD_OP_SHIFT) |\n-\t\t\tIDXD_FLAG_CACHE_CONTROL | (flags & IDXD_FLAG_FENCE);\n-\treturn __idxd_write_desc(dev_private, memmove, src, dst, length,\n-\t\t\tflags);\n+\tuint32_t op_flags = __idxd_get_op_flags(idxd_op_memmove, flags, false);\n+\treturn __idxd_write_desc(dev_private, op_flags, src, dst, length,\n+\t\t\tflags, 0, false);\n+}\n+\n+__use_avx2\n+int\n+idxd_enqueue_copy_inter_dom(void *dev_private, uint16_t qid __rte_unused, rte_iova_t src,\n+\t\trte_iova_t dst, unsigned int length,\n+\t\tuint16_t src_idpte_id, uint16_t dst_idpte_id, uint64_t flags)\n+{\n+\t/* we can take advantage of the fact that the fence flag in dmadev and\n+\t * DSA are the same, but check it at compile time to be sure.\n+\t */\n+\tRTE_BUILD_BUG_ON(RTE_DMA_OP_FLAG_FENCE != IDXD_FLAG_FENCE);\n+\tuint32_t op_flags = __idxd_get_op_flags(idxd_op_memmove, flags, true);\n+\tuint64_t alt_pasid = __idxd_get_alt_pasid(flags, src_idpte_id, dst_idpte_id);\n+\t/* currently, we require inter-domain copies to use enqcmd */\n+\treturn __idxd_write_desc(dev_private, op_flags, src, dst, length,\n+\t\t\tflags, alt_pasid, true);\n }\n \n __use_avx2\n@@ -145,17 +219,28 @@ int\n idxd_enqueue_fill(void *dev_private, uint16_t qid __rte_unused, uint64_t pattern,\n \t\trte_iova_t dst, unsigned int length, uint64_t flags)\n {\n-\tuint32_t fill = (idxd_op_fill << IDXD_CMD_OP_SHIFT) |\n-\t\t\tIDXD_FLAG_CACHE_CONTROL | (flags & IDXD_FLAG_FENCE);\n-\treturn __idxd_write_desc(dev_private, fill, pattern, dst, length,\n-\t\t\tflags);\n+\tuint32_t op_flags = __idxd_get_op_flags(idxd_op_fill, flags, false);\n+\treturn __idxd_write_desc(dev_private, op_flags, pattern, dst, length,\n+\t\t\tflags, 0, false);\n+}\n+\n+__use_avx2\n+int\n+idxd_enqueue_fill_inter_dom(void *dev_private, uint16_t qid __rte_unused,\n+\t\tuint64_t pattern, rte_iova_t dst, unsigned int length,\n+\t\tuint16_t dst_idpte_id, uint64_t flags)\n+{\n+\tuint32_t op_flags = __idxd_get_op_flags(idxd_op_fill, flags, true);\n+\tuint64_t alt_pasid = __idxd_get_alt_pasid(flags, 0, dst_idpte_id);\n+\treturn __idxd_write_desc(dev_private, op_flags, pattern, dst, length,\n+\t\t\tflags, alt_pasid, true);\n }\n \n __use_avx2\n int\n idxd_submit(void *dev_private, uint16_t qid __rte_unused)\n {\n-\t__submit(dev_private);\n+\t__submit(dev_private, false);\n \treturn 0;\n }\n \n@@ -490,6 +575,12 @@ idxd_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *info, uint32_t\n \t};\n \tif (idxd->sva_support)\n \t\tinfo->dev_capa |= RTE_DMA_CAPA_SVA;\n+\n+\tif (idxd->inter_dom_support) {\n+\t\tinfo->dev_capa |= RTE_DMA_CAPA_OPS_INTER_DOM;\n+\t\tinfo->controller_id = idxd->u.bus.dsa_id;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -600,6 +691,8 @@ idxd_dmadev_create(const char *name, struct rte_device *dev,\n \tdmadev->fp_obj->completed_status = idxd_completed_status;\n \tdmadev->fp_obj->burst_capacity = idxd_burst_capacity;\n \tdmadev->fp_obj->dev_private = dmadev->data->dev_private;\n+\tdmadev->fp_obj->copy_inter_dom = idxd_enqueue_copy_inter_dom;\n+\tdmadev->fp_obj->fill_inter_dom = idxd_enqueue_fill_inter_dom;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\ndiff --git a/drivers/dma/idxd/idxd_hw_defs.h b/drivers/dma/idxd/idxd_hw_defs.h\nindex a38540f283..441e9d29a4 100644\n--- a/drivers/dma/idxd/idxd_hw_defs.h\n+++ b/drivers/dma/idxd/idxd_hw_defs.h\n@@ -9,18 +9,24 @@\n * Defines used in the data path for interacting with IDXD hardware.\n */\n #define IDXD_CMD_OP_SHIFT 24\n+#define IDXD_CMD_SRC_IDPTE_IDX_SHIFT 32\n+#define IDXD_CMD_DST_IDPTE_IDX_SHIFT 48\n enum rte_idxd_ops {\n \tidxd_op_nop = 0,\n \tidxd_op_batch,\n \tidxd_op_drain,\n \tidxd_op_memmove,\n-\tidxd_op_fill\n+\tidxd_op_fill,\n+\tidxd_op_inter_dom = 0x20\n };\n \n #define IDXD_FLAG_FENCE (1 << 0)\n #define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)\n #define IDXD_FLAG_REQUEST_COMPLETION (1 << 3)\n+#define IDXD_INTERDOM_SUPPORT (1 << 6)\n #define IDXD_FLAG_CACHE_CONTROL (1 << 8)\n+#define IDXD_FLAG_SRC_ALT_PASID (1 << 16)\n+#define IDXD_FLAG_DST_ALT_PASID (1 << 17)\n \n /**\n * Hardware descriptor used by DSA hardware, for both bursts and\n@@ -42,8 +48,10 @@ struct idxd_hw_desc {\n \n \tuint16_t intr_handle; /* completion interrupt handle */\n \n-\t/* remaining 26 bytes are reserved */\n-\tuint16_t reserved[13];\n+\t/* next 22 bytes are reserved */\n+\tuint16_t reserved[11];\n+\tuint16_t src_pasid_hndl; /* pasid handle for source */\n+\tuint16_t dest_pasid_hndl; /* pasid handle for destination */\n } __rte_aligned(64);\n \n #define IDXD_COMP_STATUS_INCOMPLETE 0\ndiff --git a/drivers/dma/idxd/idxd_internal.h b/drivers/dma/idxd/idxd_internal.h\nindex cd4177721d..fb999d29f7 100644\n--- a/drivers/dma/idxd/idxd_internal.h\n+++ b/drivers/dma/idxd/idxd_internal.h\n@@ -70,6 +70,7 @@ struct idxd_dmadev {\n \tstruct rte_dma_dev *dmadev;\n \tstruct rte_dma_vchan_conf qcfg;\n \tuint8_t sva_support;\n+\tuint8_t\tinter_dom_support;\n \tuint8_t qid;\n \n \tunion {\n@@ -92,8 +93,14 @@ int idxd_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info,\n \t\tuint32_t size);\n int idxd_enqueue_copy(void *dev_private, uint16_t qid, rte_iova_t src,\n \t\trte_iova_t dst, unsigned int length, uint64_t flags);\n+int idxd_enqueue_copy_inter_dom(void *dev_private, uint16_t qid, rte_iova_t src,\n+\t\trte_iova_t dst, unsigned int length,\n+\t\tuint16_t src_idpte_id, uint16_t dst_idpte_id, uint64_t flags);\n int idxd_enqueue_fill(void *dev_private, uint16_t qid, uint64_t pattern,\n \t\trte_iova_t dst, unsigned int length, uint64_t flags);\n+int idxd_enqueue_fill_inter_dom(void *dev_private, uint16_t qid, uint64_t pattern,\n+\t\trte_iova_t dst, unsigned int length, uint16_t dst_idpte_id,\n+\t\tuint64_t flags);\n int idxd_submit(void *dev_private, uint16_t qid);\n uint16_t idxd_completed(void *dev_private, uint16_t qid, uint16_t max_ops,\n \t\tuint16_t *last_idx, bool *has_error);\n", "prefixes": [ "v1", "2/3" ] }