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GET /api/patches/130131/?format=api
{ "id": 130131, "url": "http://patches.dpdk.org/api/patches/130131/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-17-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230811085805.441256-17-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230811085805.441256-17-ndabilpuram@marvell.com", "date": "2023-08-11T08:57:51", "name": "[17/31] common/cnxk: expose different params for bp config", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "27cedde76a9f071b514d8d64ebef3f98b4abe779", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-17-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 29177, "url": "http://patches.dpdk.org/api/series/29177/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29177", "date": "2023-08-11T08:57:35", "name": "[01/31] common/cnxk: add aura ref count mechanism", "version": 1, "mbox": "http://patches.dpdk.org/series/29177/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130131/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/130131/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3162C43032;\n\tFri, 11 Aug 2023 10:59:55 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CEF604324E;\n\tFri, 11 Aug 2023 10:59:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A02DF43293\n for <dev@dpdk.org>; Fri, 11 Aug 2023 10:59:02 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37AMk3fg002130 for <dev@dpdk.org>; Fri, 11 Aug 2023 01:59:01 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r9e-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 11 Aug 2023 01:59:01 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 11 Aug 2023 01:59:00 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 11 Aug 2023 01:59:00 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id E16AD3F706B;\n Fri, 11 Aug 2023 01:58:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=AryHH6F24PP4iQQsNyXVHNeb0Rr0/6HNr/XXhSKb41M=;\n b=VFs+5XP455OdM5pWQAKL3hvDy3KAy7T72xYMIB1eHFZ35X9NS5ZZ7GxVbkrfeDJfPFNs\n GzwQyByKyeNqFWxdKI/wWRPA6G/NcKwCcioLKeHh3WXl3MnZMzIjPMaZAylcH3SaBT2u\n +MmppwUiquvm3j27nLn/K8IdhKwPGtNdiqa5dkeBNmYDo7uzDi5aGXo2CcMVedzfG1rH\n vcCE4j+9lm5058d6xenrvF0Y3geQSUfIu2qeOFOGUzjD+pkrJF6L8NK3c7rKpJ5272iG\n Snj0lrb9mVLBnxLG3ij39nfe3WBqYyAWK8lVnFO110RfbP50EQKJ4sXCLZhWUJEGJta2 zw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 17/31] common/cnxk: expose different params for bp config", "Date": "Fri, 11 Aug 2023 14:27:51 +0530", "Message-ID": "<20230811085805.441256-17-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "References": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D", "X-Proofpoint-GUID": "CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nCurrently same bp percentage is applied on SPB and\nLPB pool but both pools can be configured with different\nbp level.\n\nAdded one more parameter so that separate threshold parameters\ncan be passed for SPB and LPB pools.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 3 ++-\n drivers/common/cnxk/roc_nix_fc.c | 14 +++++++++-----\n 2 files changed, 11 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 377b9604ea..bb55fbe971 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -196,10 +196,11 @@ struct roc_nix_fc_cfg {\n \t\t\tuint32_t rq;\n \t\t\tuint16_t tc;\n \t\t\tuint16_t cq_drop;\n-\t\t\tbool enable;\n \t\t\tuint64_t pool;\n \t\t\tuint64_t spb_pool;\n \t\t\tuint64_t pool_drop_pct;\n+\t\t\tuint64_t spb_pool_drop_pct;\n+\t\t\tbool enable;\n \t\t} rq_cfg;\n \n \t\tstruct {\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 2a58567751..12bfb9816b 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -282,8 +282,8 @@ static int\n nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint64_t pool_drop_pct, spb_pool_drop_pct;\n \tstruct roc_nix_fc_cfg tmp;\n-\tuint64_t pool_drop_pct;\n \tstruct roc_nix_rq *rq;\n \tint rc;\n \n@@ -295,14 +295,18 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tif (fc_cfg->rq_cfg.enable && !pool_drop_pct)\n \t\t\tpool_drop_pct = ROC_NIX_AURA_THRESH;\n \n-\t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool,\n-\t\t\t\t fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n-\t\t\t\t fc_cfg->rq_cfg.tc, pool_drop_pct);\n+\t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, fc_cfg->rq_cfg.enable,\n+\t\t\t\t roc_nix->force_rx_aura_bp, fc_cfg->rq_cfg.tc, pool_drop_pct);\n \n \t\tif (rq->spb_ena) {\n+\t\t\tspb_pool_drop_pct = fc_cfg->rq_cfg.spb_pool_drop_pct;\n+\t\t\t/* Use default value for zero pct */\n+\t\t\tif (!spb_pool_drop_pct)\n+\t\t\t\tspb_pool_drop_pct = ROC_NIX_AURA_THRESH;\n+\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool,\n \t\t\t\t\t fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n-\t\t\t\t\t fc_cfg->rq_cfg.tc, pool_drop_pct);\n+\t\t\t\t\t fc_cfg->rq_cfg.tc, spb_pool_drop_pct);\n \t\t}\n \n \t\tif (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)\n", "prefixes": [ "17/31" ] }