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GET /api/patches/130119/?format=api
{ "id": 130119, "url": "http://patches.dpdk.org/api/patches/130119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-5-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230811085805.441256-5-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230811085805.441256-5-ndabilpuram@marvell.com", "date": "2023-08-11T08:57:39", "name": "[05/31] common/cnxk: support rate limit on PFC TM tree", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d244edf6e4dbb91c482d66bff01eb7cc1f51ff5d", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-5-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 29177, "url": "http://patches.dpdk.org/api/series/29177/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29177", "date": "2023-08-11T08:57:35", "name": "[01/31] common/cnxk: add aura ref count mechanism", "version": 1, "mbox": "http://patches.dpdk.org/series/29177/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130119/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/130119/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D318843032;\n\tFri, 11 Aug 2023 10:58:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D57564326D;\n\tFri, 11 Aug 2023 10:58:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7989743271\n for <dev@dpdk.org>; Fri, 11 Aug 2023 10:58:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37AN2LhS011196 for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:25 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g7y-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:24 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 11 Aug 2023 01:58:22 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 11 Aug 2023 01:58:22 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 877F63F706A;\n Fri, 11 Aug 2023 01:58:20 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=DFn57ShgH1uxGl1zXOkYWT0M/xzx+zDOalUd4p+L/7Q=;\n b=SxTrTFJjIjI/CyXB1/hHiDBfSXfwjxNKleDoeUg5r6XSZ31yDkDSz93B++du02qYlOSe\n tKfnLo07NJ/N7uy26McAVSS/BpYLD4oKpwxJHYG0nwN3q50PX6yUDveQA5b2KzDgDsQI\n 74s0J6dZ+VDB+O9J/E6eMt4bEWV7uBOAIeoNAh4IWaMfdleEPcrL9fXKQ+hCcfkyUB+0\n lBa4fUCW1e0A89uQ4mV9Q1a5O0hBviOTExvxfSB5lFWPsEkJVVqco9EfwFCzPHwQ9Lze\n NTISZ8nLVVqlEG96kNe0qxiObJnBmKIjy1OFPooRfbMs9N9b81ui9UVJTi/0gDGLNOPz hQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 05/31] common/cnxk: support rate limit on PFC TM tree", "Date": "Fri, 11 Aug 2023 14:27:39 +0530", "Message-ID": "<20230811085805.441256-5-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "References": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "abXP39VS7Av572sl-KKTR-Y0W6LVEyTt", "X-Proofpoint-GUID": "abXP39VS7Av572sl-KKTR-Y0W6LVEyTt", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nNew SQ rate limit API to support SQ rate limit on PFC tree.\nIn PFC tree each SQ had its one to one mapped TL3, this patch\nconfigures shaper rate on TL3. Also configures the TL2 with\nlink rate.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 9 ++-\n drivers/common/cnxk/roc_nix_tm_ops.c | 98 ++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 3 files changed, 106 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 9c2ba9a685..1d84f4de9d 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -707,8 +707,13 @@ int __roc_api roc_nix_tm_node_stats_get(struct roc_nix *roc_nix,\n /*\n * TM ratelimit tree API.\n */\n-int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid,\n-\t\t\t\t uint64_t rate);\n+int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate);\n+\n+/*\n+ * TM PFC tree ratelimit API.\n+ */\n+int __roc_api roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate);\n+\n /*\n * TM hierarchy enable/disable API.\n */\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 4e88ad1beb..e1cef7a670 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -1032,6 +1032,104 @@ roc_nix_tm_init(struct roc_nix *roc_nix)\n \treturn rc;\n }\n \n+int\n+roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile profile;\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_tm_node *node, *parent;\n+\tstruct roc_nix_link_info link_info;\n+\n+\tvolatile uint64_t *reg, *regval;\n+\tstruct nix_txschq_config *req;\n+\tuint64_t tl2_rate = 0;\n+\tuint16_t flags;\n+\tuint8_t k = 0;\n+\tint rc;\n+\n+\tif ((nix->tm_tree != ROC_NIX_TM_PFC) || !(nix->tm_flags & NIX_TM_HIERARCHY_ENA))\n+\t\treturn NIX_ERR_TM_INVALID_TREE;\n+\n+\tnode = nix_tm_node_search(nix, qid, nix->tm_tree);\n+\n+\t/* check if we found a valid leaf node */\n+\tif (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||\n+\t node->parent->hw_id == NIX_TM_HW_ID_INVALID) {\n+\t\treturn NIX_ERR_TM_INVALID_NODE;\n+\t}\n+\n+\t/* Get the link Speed */\n+\tif (roc_nix_mac_link_info_get(roc_nix, &link_info))\n+\t\treturn -EINVAL;\n+\n+\tif (link_info.status)\n+\t\ttl2_rate = link_info.speed * (uint64_t)1E6;\n+\n+\t/* Configure TL3 of leaf node with requested rate */\n+\tparent = node->parent;\t /* SMQ/MDQ */\n+\tparent = parent->parent; /* TL4 */\n+\tparent = parent->parent; /* TL3 */\n+\tflags = parent->flags;\n+\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n+\treq->lvl = parent->hw_lvl;\n+\treg = req->reg;\n+\tregval = req->regval;\n+\n+\tif (rate == 0) {\n+\t\tk += nix_tm_sw_xoff_prep(parent, true, ®[k], ®val[k]);\n+\t\tflags &= ~NIX_TM_NODE_ENABLED;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!(flags & NIX_TM_NODE_ENABLED)) {\n+\t\tk += nix_tm_sw_xoff_prep(parent, false, ®[k], ®val[k]);\n+\t\tflags |= NIX_TM_NODE_ENABLED;\n+\t}\n+\n+\t/* Use only PIR for rate limit */\n+\tmemset(&profile, 0, sizeof(profile));\n+\tprofile.peak.rate = rate;\n+\t/* Minimum burst of ~4us Bytes of Tx */\n+\tprofile.peak.size =\n+\t\tPLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), (4ul * rate) / ((uint64_t)1E6 * 8));\n+\tif (!nix->tm_rate_min || nix->tm_rate_min > rate)\n+\t\tnix->tm_rate_min = rate;\n+\n+\tk += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]);\n+exit:\n+\treq->num_regs = k;\n+\trc = mbox_process(mbox);\n+\tmbox_put(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tparent->flags = flags;\n+\n+\t/* If link is up then configure TL2 with link speed */\n+\tif (tl2_rate && (flags & NIX_TM_NODE_ENABLED)) {\n+\t\tk = 0;\n+\t\tparent = parent->parent;\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n+\t\treq->lvl = parent->hw_lvl;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\n+\t\t/* Use only PIR for rate limit */\n+\t\tmemset(&profile, 0, sizeof(profile));\n+\t\tprofile.peak.rate = tl2_rate;\n+\t\t/* Minimum burst of ~4us Bytes of Tx */\n+\t\tprofile.peak.size = PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix),\n+\t\t\t\t\t (4ul * tl2_rate) / ((uint64_t)1E6 * 8));\n+\t\tk += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]);\n+\t\treq->num_regs = k;\n+\t\trc = mbox_process(mbox);\n+\t\tmbox_put(mbox);\n+\t}\n+\treturn rc;\n+}\n+\n int\n roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)\n {\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 8c71497df8..1436c90e12 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -379,6 +379,7 @@ INTERNAL {\n \troc_nix_tm_node_suspend_resume;\n \troc_nix_tm_prealloc_res;\n \troc_nix_tm_pfc_prepare_tree;\n+\troc_nix_tm_pfc_rlimit_sq;\n \troc_nix_tm_prepare_rate_limited_tree;\n \troc_nix_tm_rlimit_sq;\n \troc_nix_tm_root_has_sp;\n", "prefixes": [ "05/31" ] }