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GET /api/patches/130118/?format=api
{ "id": 130118, "url": "http://patches.dpdk.org/api/patches/130118/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230811085805.441256-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230811085805.441256-4-ndabilpuram@marvell.com", "date": "2023-08-11T08:57:38", "name": "[04/31] common/cnxk: add workaround for CPT ctx fetch issue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4e54665d969547ca89c7a175e7e4c95cdb00ef7d", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230811085805.441256-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 29177, "url": "http://patches.dpdk.org/api/series/29177/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29177", "date": "2023-08-11T08:57:35", "name": "[01/31] common/cnxk: add aura ref count mechanism", "version": 1, "mbox": "http://patches.dpdk.org/series/29177/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130118/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/130118/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8AECB43032;\n\tFri, 11 Aug 2023 10:58:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 817AA43266;\n\tFri, 11 Aug 2023 10:58:23 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 6A4D740F16\n for <dev@dpdk.org>; Fri, 11 Aug 2023 10:58:22 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37AMjlLm001536 for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:21 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r5w-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:21 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 11 Aug 2023 01:58:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 11 Aug 2023 01:58:19 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 9848B3F7081;\n Fri, 11 Aug 2023 01:58:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=mbao0JEJAn2WMgMgLFxmyByE8ETbY4eQO+ERdUaNnMY=;\n b=KycYRiiE4cZw/irlOxbxcI67HeF5gxb1dGfcq47sUYes9DaQpOVW86w7K6zUJ499ttAp\n ID/+3e0y8gVXNPKqbf91ii7jDASPJW9IY1t7SSCPJwepgms/A1tq9YnQY+hVknTMlijZ\n jwlzfR5PUo8lJzxZgeeUOo1c+tG0EloerkS7cvmiMgL8PXyNDu15Gkqzz+O5MeARvccx\n jk2cc68uRgA5ez8PWxph3GwZQD1zGvz4IgB3cc1vKYpneWcK7fIFEKLCqpyyFPsc0cJf\n I5gOW5GmpWTi+Hp41BwlBeU6FSWzWTRY42Ino/3ogj4aNcNYsIr82rH6k5nDh+ZN0m2o TQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 04/31] common/cnxk: add workaround for CPT ctx fetch issue", "Date": "Fri, 11 Aug 2023 14:27:38 +0530", "Message-ID": "<20230811085805.441256-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "References": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "hcobNQOL1bhEBHSc67xOl8kwErKH-LdO", "X-Proofpoint-GUID": "hcobNQOL1bhEBHSc67xOl8kwErKH-LdO", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add workaround for CPT context fetch issue in CN10KB\nby setting CTX_ILEN to that of CTX_SIZE and enabling\nFLR_FLUSH in CPT_LF_CTX_CTL.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_cpt.c | 23 ++++++++++++++++++++---\n drivers/common/cnxk/roc_cpt.h | 2 ++\n drivers/common/cnxk/roc_cpt_priv.h | 4 ++--\n drivers/common/cnxk/roc_errata.h | 7 +++++++\n drivers/common/cnxk/roc_ie_ot.h | 3 +++\n drivers/common/cnxk/roc_mbox.h | 4 ++++\n drivers/common/cnxk/roc_nix_inl.c | 14 +++++++++++++-\n drivers/common/cnxk/roc_nix_inl_dev.c | 10 +++++++++-\n 8 files changed, 60 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex d235ff51ca..981e85a204 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -331,6 +331,8 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipse\n \treq->param2 = cfg->param2;\n \treq->opcode = cfg->opcode;\n \treq->bpid = cfg->bpid;\n+\treq->ctx_ilen_valid = cfg->ctx_ilen_valid;\n+\treq->ctx_ilen = cfg->ctx_ilen;\n \n \trc = mbox_process(mbox);\n exit:\n@@ -460,8 +462,8 @@ cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)\n }\n \n int\n-cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n-\t bool inl_dev_sso)\n+cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, bool inl_dev_sso,\n+\t bool ctx_ilen_valid, uint8_t ctx_ilen)\n {\n \tstruct cpt_lf_alloc_req_msg *req;\n \tstruct mbox *mbox = mbox_get(dev->mbox);\n@@ -485,6 +487,8 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n \t\treq->sso_pf_func = idev_sso_pffunc_get();\n \treq->eng_grpmsk = eng_grpmsk;\n \treq->blkaddr = blkaddr;\n+\treq->ctx_ilen_valid = ctx_ilen_valid;\n+\treq->ctx_ilen = ctx_ilen;\n \n \trc = mbox_process(mbox);\n exit:\n@@ -587,6 +591,8 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tuint8_t blkaddr[ROC_CPT_MAX_BLKS];\n \tstruct msix_offset_rsp *rsp;\n+\tbool ctx_ilen_valid = false;\n+\tuint16_t ctx_ilen = 0;\n \tuint8_t eng_grpmsk;\n \tint blknum = 0;\n \tint rc, i;\n@@ -618,7 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)\n \t\t (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |\n \t\t (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);\n \n-\trc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false);\n+\tif (roc_errata_cpt_has_ctx_fetch_issue()) {\n+\t\tctx_ilen_valid = true;\n+\t\t/* Inbound SA size is max context size */\n+\t\tctx_ilen = (PLT_ALIGN(ROC_OT_IPSEC_SA_SZ_MAX, ROC_ALIGN) / 128) - 1;\n+\t}\n+\n+\trc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false, ctx_ilen_valid, ctx_ilen);\n \tif (rc)\n \t\tgoto lfs_detach;\n \n@@ -1108,6 +1120,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf)\n \tlf_inprog.s.eena = 1;\n \tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n \n+\tif (roc_errata_cpt_has_ctx_fetch_issue()) {\n+\t\t/* Enable flush on FLR */\n+\t\tplt_write64(1, lf->rbase + CPT_LF_CTX_CTL);\n+\t}\n+\n \tcpt_lf_dump(lf);\n }\n \ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 910bd37a0c..787bccb27d 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -161,6 +161,8 @@ struct roc_cpt_inline_ipsec_inb_cfg {\n \tuint16_t bpid;\n \tuint32_t credit_th;\n \tuint8_t egrp;\n+\tuint8_t ctx_ilen_valid : 1;\n+\tuint8_t ctx_ilen : 7;\n };\n \n int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,\ndiff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h\nindex 61dec9a168..4ed87c857b 100644\n--- a/drivers/common/cnxk/roc_cpt_priv.h\n+++ b/drivers/common/cnxk/roc_cpt_priv.h\n@@ -21,8 +21,8 @@ roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)\n int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify,\n \t\t uint16_t nb_lf);\n int cpt_lfs_detach(struct dev *dev);\n-int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,\n-\t\t bool inl_dev_sso);\n+int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, bool inl_dev_sso,\n+\t\t bool ctx_ilen_valid, uint8_t ctx_ilen);\n int cpt_lfs_free(struct dev *dev);\n int cpt_lf_init(struct roc_cpt_lf *lf);\n void cpt_lf_fini(struct roc_cpt_lf *lf);\ndiff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h\nindex 22d2406e94..6f84e06603 100644\n--- a/drivers/common/cnxk/roc_errata.h\n+++ b/drivers/common/cnxk/roc_errata.h\n@@ -82,6 +82,13 @@ roc_errata_cpt_hang_on_x2p_bp(void)\n \treturn roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1();\n }\n \n+/* Errata IPBUCPT-38756 */\n+static inline bool\n+roc_errata_cpt_has_ctx_fetch_issue(void)\n+{\n+\treturn roc_model_is_cn10kb();\n+}\n+\n /* IPBUNIXRX-40400 */\n static inline bool\n roc_errata_nix_no_meta_aura(void)\ndiff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h\nindex b7fcdf9ba7..af2691e0eb 100644\n--- a/drivers/common/cnxk/roc_ie_ot.h\n+++ b/drivers/common/cnxk/roc_ie_ot.h\n@@ -570,6 +570,9 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==\n PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==\n \t\t 31 * sizeof(uint64_t));\n \n+#define ROC_OT_IPSEC_SA_SZ_MAX \\\n+\t(PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct roc_ot_ipsec_outb_sa)))\n+\n void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,\n \t\t\t\t\tbool is_inline);\n void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 2f85b2f755..f038d3e02b 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -2002,6 +2002,8 @@ struct cpt_lf_alloc_req_msg {\n \tuint16_t __io sso_pf_func;\n \tuint16_t __io eng_grpmsk;\n \tuint8_t __io blkaddr;\n+\tuint8_t __io ctx_ilen_valid : 1;\n+\tuint8_t __io ctx_ilen : 7;\n };\n \n #define CPT_INLINE_INBOUND 0\n@@ -2083,6 +2085,8 @@ struct cpt_rx_inline_lf_cfg_msg {\n \tuint32_t __io credit_th;\n \tuint16_t __io bpid;\n \tuint32_t __io reserved;\n+\tuint8_t __io ctx_ilen_valid : 1;\n+\tuint8_t __io ctx_ilen : 7;\n };\n \n struct cpt_caps_rsp_msg {\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 16f858f561..5cb1f11f53 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -851,6 +851,11 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \t\t\tnix->cpt_nixbpid = bpids[0];\n \t\t\tcfg.bpid = nix->cpt_nixbpid;\n \t\t}\n+\n+\t\tif (roc_errata_cpt_has_ctx_fetch_issue()) {\n+\t\t\tcfg.ctx_ilen_valid = true;\n+\t\t\tcfg.ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1;\n+\t\t}\n \t}\n \n \t/* Do onetime Inbound Inline config in CPTPF */\n@@ -931,7 +936,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n \tstruct dev *dev = &nix->dev;\n \tstruct msix_offset_rsp *rsp;\n \tstruct nix_inl_dev *inl_dev;\n+\tbool ctx_ilen_valid = false;\n \tsize_t sa_sz, ring_sz;\n+\tuint8_t ctx_ilen = 0;\n \tuint16_t sso_pffunc;\n \tuint8_t eng_grpmask;\n \tuint64_t blkaddr, i;\n@@ -967,12 +974,17 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n \t\treturn rc;\n \t}\n \n+\tif (!roc_model_is_cn9k() && roc_errata_cpt_has_ctx_fetch_issue()) {\n+\t\tctx_ilen = (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ / 128) - 1;\n+\t\tctx_ilen_valid = true;\n+\t}\n+\n \t/* Alloc CPT LF */\n \teng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |\n \t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |\n \t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);\n \trc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,\n-\t\t\t !roc_nix->ipsec_out_sso_pffunc);\n+\t\t\t !roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid, ctx_ilen);\n \tif (rc) {\n \t\tplt_err(\"Failed to alloc CPT LF resources, rc=%d\", rc);\n \t\tgoto lf_detach;\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex d76158e30d..2863d5da51 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -176,7 +176,9 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso)\n {\n \tstruct roc_cpt_lf *lf = &inl_dev->cpt_lf;\n \tstruct dev *dev = &inl_dev->dev;\n+\tbool ctx_ilen_valid = false;\n \tuint8_t eng_grpmask;\n+\tuint8_t ctx_ilen = 0;\n \tint rc;\n \n \tif (!inl_dev->attach_cptlf)\n@@ -186,7 +188,13 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso)\n \teng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |\n \t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |\n \t\t 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);\n-\trc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso);\n+\tif (roc_errata_cpt_has_ctx_fetch_issue()) {\n+\t\tctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1;\n+\t\tctx_ilen_valid = true;\n+\t}\n+\n+\trc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso, ctx_ilen_valid,\n+\t\t\t ctx_ilen);\n \tif (rc) {\n \t\tplt_err(\"Failed to alloc CPT LF resources, rc=%d\", rc);\n \t\treturn rc;\n", "prefixes": [ "04/31" ] }