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GET /api/patches/130029/?format=api
{ "id": 130029, "url": "http://patches.dpdk.org/api/patches/130029/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230809155134.539287-17-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230809155134.539287-17-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230809155134.539287-17-beilei.xing@intel.com", "date": "2023-08-09T15:51:31", "name": "[16/19] net/cpfl: support representor data path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0940c91497083121f0e4348edb85763ee31d1b56", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230809155134.539287-17-beilei.xing@intel.com/mbox/", "series": [ { "id": 29139, "url": "http://patches.dpdk.org/api/series/29139/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29139", "date": "2023-08-09T15:51:15", "name": "net/cpfl: support port representor", "version": 1, "mbox": "http://patches.dpdk.org/series/29139/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130029/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/130029/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9004443016;\n\tWed, 9 Aug 2023 09:35:09 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 970AF432A9;\n\tWed, 9 Aug 2023 09:33:38 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 78ACF432A5\n for <dev@dpdk.org>; Wed, 9 Aug 2023 09:33:36 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2023 00:33:35 -0700", "from dpdk-beileix-icelake.sh.intel.com ([10.67.116.252])\n by fmsmga005.fm.intel.com with ESMTP; 09 Aug 2023 00:33:34 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1691566416; x=1723102416;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=K4HLYXRZgENhd+k7aruSItn0URpJJilXTr+mtBk5Gr0=;\n b=AA0uSNOpeqJIzO+0d8FvAEfDLEczPISTiNzuR0itJGkBcxVFs1dffE2C\n /zfrj7P7QNIKsiF4xZI4ZV0KGPU7jII27LsZlzfJ0+nSF9730Fs7uVFRx\n o9My1IR6zKTbMZezUsyWbS814OvgwQJOGbaQFyzKnYHVwKPVBGx2F6Ua3\n f1wHx0igS8IvlNDJjKYFzQa0kMLS28QdSVbTSzhVt6cvTdpeAfSRmGlgp\n 73Wn8+Jth2lD8UEJGW9AQ3ZwED/FwjKRSP8Kf6qsz7plS32Sd1PC9bzIX\n UNdEDLufjF1nexox9Dnr/bYpC8yCszjlZ+EFdPxGd2giLJamkWjBI3de9 g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10795\"; a=\"356014537\"", "E=Sophos;i=\"6.01,158,1684825200\"; d=\"scan'208\";a=\"356014537\"", "E=McAfee;i=\"6600,9927,10795\"; a=\"1062337463\"", "E=Sophos;i=\"6.01,158,1684825200\"; d=\"scan'208\";a=\"1062337463\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com,\n\tmingxia.liu@intel.com", "Cc": "dev@dpdk.org,\n\tBeilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH 16/19] net/cpfl: support representor data path", "Date": "Wed, 9 Aug 2023 15:51:31 +0000", "Message-Id": "<20230809155134.539287-17-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230809155134.539287-1-beilei.xing@intel.com>", "References": "<20230809155134.539287-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nAdd Rx/Tx burst for port representor.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_representor.c | 83 +++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.c | 121 ++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.h | 4 +\n 3 files changed, 208 insertions(+)", "diff": "diff --git a/drivers/net/cpfl/cpfl_representor.c b/drivers/net/cpfl/cpfl_representor.c\nindex 79cb7f76d4..51b70ea346 100644\n--- a/drivers/net/cpfl/cpfl_representor.c\n+++ b/drivers/net/cpfl/cpfl_representor.c\n@@ -491,6 +491,87 @@ static const struct eth_dev_ops cpfl_repr_dev_ops = {\n \t.stats_reset\t\t= idpf_repr_stats_reset,\n };\n \n+#define MAX_IDPF_REPRENSENTOR_BURST 128\n+static uint16_t\n+cpfl_repr_rx_burst(void *rxq,\n+\t\t struct rte_mbuf **rx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct cpfl_repr_rx_queue *rx_queue = rxq;\n+\tstruct rte_ring *ring = rx_queue->rx_ring;\n+\tstruct rte_mbuf *mbuf[MAX_IDPF_REPRENSENTOR_BURST] = {NULL};\n+\tunsigned int nb_recv;\n+\tuint16_t i;\n+\n+\tif (unlikely(!ring))\n+\t\treturn 0;\n+\n+\tnb_recv = rte_ring_dequeue_burst(ring, (void **)mbuf,\n+\t\t\t\t\t RTE_MIN(nb_pkts, MAX_IDPF_REPRENSENTOR_BURST), NULL);\n+\tfor (i = 0; i < nb_recv; i++) {\n+\t\tif (mbuf[i]->pool != rx_queue->mb_pool) {\n+\t\t\t/* need copy if mpools used for vport and represntor queue are different */\n+\t\t\trx_pkts[i] = rte_pktmbuf_copy(mbuf[i], rx_queue->mb_pool, 0, UINT32_MAX);\n+\t\t\trte_pktmbuf_free(mbuf[i]);\n+\t\t} else {\n+\t\t\trx_pkts[i] = mbuf[i];\n+\t\t}\n+\t}\n+\n+\t__atomic_fetch_add(&rx_queue->stats.packets, nb_recv, __ATOMIC_RELAXED);\n+\t/* TODO: bytes stats */\n+\treturn nb_recv;\n+}\n+\n+static uint16_t\n+cpfl_get_vsi_from_vf_representor(struct cpfl_repr *repr)\n+{\n+\treturn repr->vport_info->vport_info.vsi_id;\n+}\n+\n+static uint16_t\n+cpfl_repr_tx_burst(void *txq,\n+\t\t struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct cpfl_repr_tx_queue *tx_queue = txq;\n+\tstruct idpf_tx_queue *hw_txq = &tx_queue->txq->base;\n+\tstruct cpfl_repr *repr;\n+\tuint16_t vsi_id;\n+\tuint16_t nb;\n+\n+\tif (unlikely(!tx_queue->txq))\n+\t\treturn 0;\n+\n+\trepr = tx_queue->repr;\n+\n+\tif (!hw_txq) {\n+\t\tPMD_INIT_LOG(ERR, \"No Queue associated with representor host_id: %d, %s %d\",\n+\t\t\t repr->repr_id.host_id,\n+\t\t\t (repr->repr_id.type == RTE_ETH_REPRESENTOR_VF) ? \"vf\" : \"pf\",\n+\t\t\t (repr->repr_id.type == RTE_ETH_REPRESENTOR_VF) ? repr->repr_id.vf_id :\n+\t\t\t repr->repr_id.pf_id);\n+\t\treturn 0;\n+\t}\n+\n+\tif (repr->repr_id.type == RTE_ETH_REPRESENTOR_VF) {\n+\t\tvsi_id = cpfl_get_vsi_from_vf_representor(repr);\n+\t} else {\n+\t\t/* TODO: RTE_ETH_REPRESENTOR_PF */\n+\t\tPMD_INIT_LOG(ERR, \"Get vsi from pf representor is not supported.\");\n+\t\treturn 0;\n+\t}\n+\n+\trte_spinlock_lock(&tx_queue->txq->lock);\n+\tnb = cpfl_xmit_pkts_to_vsi(tx_queue->txq, tx_pkts, nb_pkts, vsi_id);\n+\trte_spinlock_unlock(&tx_queue->txq->lock);\n+\n+\t__atomic_fetch_add(&tx_queue->stats.packets, nb, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&tx_queue->stats.errors, nb, __ATOMIC_RELAXED);\n+\t/* TODO: bytes stats */\n+\treturn nb;\n+}\n+\n static int\n cpfl_repr_init(struct rte_eth_dev *eth_dev, void *init_param)\n {\n@@ -507,6 +588,8 @@ cpfl_repr_init(struct rte_eth_dev *eth_dev, void *init_param)\n \t\trepr->func_up = true;\n \n \teth_dev->dev_ops = &cpfl_repr_dev_ops;\n+\teth_dev->rx_pkt_burst = cpfl_repr_rx_burst;\n+\teth_dev->tx_pkt_burst = cpfl_repr_tx_burst;\n \n \teth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;\n \t/* bit[15:14] type\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex df6a8c1940..882efe04cf 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -616,6 +616,9 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \ttxq->ops = &def_txq_ops;\n \tcpfl_vport->nb_data_txq++;\n \ttxq->q_set = true;\n+\n+\trte_spinlock_init(&cpfl_txq->lock);\n+\n \tdev->data->tx_queues[queue_idx] = cpfl_txq;\n \n \treturn 0;\n@@ -1409,6 +1412,124 @@ cpfl_stop_queues(struct rte_eth_dev *dev)\n \t}\n }\n \n+static inline void\n+cpfl_set_tx_switch_ctx(uint16_t vsi_id, bool is_vsi,\n+\t\t volatile union idpf_flex_tx_ctx_desc *ctx_desc)\n+{\n+\tuint16_t cmd_dtype;\n+\n+\t/* Use TX Native TSO Context Descriptor to carry VSI\n+\t * so TSO is not supported\n+\t */\n+\tif (is_vsi) {\n+\t\tcmd_dtype = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX |\n+\t\t\tIDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI;\n+\t\tctx_desc->tso.qw0.mss_rt =\n+\t\t\trte_cpu_to_le_16((uint16_t)vsi_id &\n+\t\t\t\t IDPF_TXD_FLEX_CTX_MSS_RT_M);\n+\t} else {\n+\t\tcmd_dtype = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX |\n+\t\t\tIDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_UPLNK;\n+\t}\n+\n+\tctx_desc->tso.qw1.cmd_dtype = rte_cpu_to_le_16(cmd_dtype);\n+}\n+\n+/* Transmit pkts to destination VSI,\n+ * much similar as idpf_splitq_xmit_pkts\n+ */\n+uint16_t\n+cpfl_xmit_pkts_to_vsi(struct cpfl_tx_queue *cpfl_txq, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts, uint16_t vsi_id)\n+{\n+\tvolatile struct idpf_flex_tx_sched_desc *txr;\n+\tvolatile struct idpf_flex_tx_sched_desc *txd;\n+\tvolatile union idpf_flex_tx_ctx_desc *ctx_desc;\n+\tstruct idpf_tx_entry *sw_ring;\n+\tstruct idpf_tx_entry *txe, *txn;\n+\tuint16_t nb_used, tx_id, sw_id;\n+\tstruct idpf_tx_queue *txq;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t nb_to_clean;\n+\tuint16_t nb_tx = 0;\n+\n+\tif (unlikely(!cpfl_txq))\n+\t\treturn nb_tx;\n+\n+\ttxq = &cpfl_txq->base;\n+\tif (unlikely(!txq) || unlikely(!txq->q_started))\n+\t\treturn nb_tx;\n+\n+\ttxr = txq->desc_ring;\n+\tsw_ring = txq->sw_ring;\n+\ttx_id = txq->tx_tail;\n+\tsw_id = txq->sw_tail;\n+\ttxe = &sw_ring[sw_id];\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = tx_pkts[nb_tx];\n+\n+\t\tif (txq->nb_free <= txq->free_thresh) {\n+\t\t\t/* TODO: Need to refine, refer to idpf_splitq_xmit_pkts */\n+\t\t\tnb_to_clean = 2 * txq->rs_thresh;\n+\t\t\twhile (nb_to_clean--)\n+\t\t\t\tidpf_split_tx_free(txq->complq);\n+\t\t}\n+\n+\t\tif (txq->nb_free < tx_pkt->nb_segs + 1)\n+\t\t\tbreak;\n+\t\t/* need context desc carry target vsi, no TSO support. */\n+\t\tnb_used = tx_pkt->nb_segs + 1;\n+\n+\t\t/* context descriptor prepare*/\n+\t\tctx_desc = (volatile union idpf_flex_tx_ctx_desc *)&txr[tx_id];\n+\n+\t\tcpfl_set_tx_switch_ctx(vsi_id, true, ctx_desc);\n+\t\ttx_id++;\n+\t\tif (tx_id == txq->nb_tx_desc)\n+\t\t\ttx_id = 0;\n+\n+\t\tdo {\n+\t\t\ttxd = &txr[tx_id];\n+\t\t\ttxn = &sw_ring[txe->next_id];\n+\t\t\ttxe->mbuf = tx_pkt;\n+\n+\t\t\t/* Setup TX descriptor */\n+\t\t\ttxd->buf_addr =\n+\t\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova(tx_pkt));\n+\t\t\ttxd->qw1.cmd_dtype = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE;\n+\t\t\ttxd->qw1.rxr_bufsize = tx_pkt->data_len;\n+\t\t\ttxd->qw1.compl_tag = sw_id;\n+\t\t\ttx_id++;\n+\t\t\tif (tx_id == txq->nb_tx_desc)\n+\t\t\t\ttx_id = 0;\n+\t\t\tsw_id = txe->next_id;\n+\t\t\ttxe = txn;\n+\t\t\ttx_pkt = tx_pkt->next;\n+\t\t} while (tx_pkt);\n+\n+\t\t/* fill the last descriptor with End of Packet (EOP) bit */\n+\t\ttxd->qw1.cmd_dtype |= IDPF_TXD_FLEX_FLOW_CMD_EOP;\n+\n+\t\ttxq->nb_free = (uint16_t)(txq->nb_free - nb_used);\n+\t\ttxq->nb_used = (uint16_t)(txq->nb_used + nb_used);\n+\n+\t\tif (txq->nb_used >= 32) {\n+\t\t\ttxd->qw1.cmd_dtype |= IDPF_TXD_FLEX_FLOW_CMD_RE;\n+\t\t\t/* Update txq RE bit counters */\n+\t\t\ttxq->nb_used = 0;\n+\t\t}\n+\t}\n+\n+\t/* update the tail pointer if any packets were processed */\n+\tif (likely(nb_tx)) {\n+\t\tIDPF_PCI_REG_WRITE(txq->qtx_tail, tx_id);\n+\t\ttxq->tx_tail = tx_id;\n+\t\ttxq->sw_tail = sw_id;\n+\t}\n+\treturn nb_tx;\n+}\n+\n uint16_t\n cpfl_dummy_recv_pkts(__rte_unused void *queue,\n \t\t __rte_unused struct rte_mbuf **tx_pkts,\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex 914a0485b5..463ab73323 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -72,6 +72,7 @@ struct cpfl_txq_hairpin_info {\n struct cpfl_tx_queue {\n \tstruct idpf_tx_queue base;\n \tstruct cpfl_txq_hairpin_info hairpin_info;\n+\trte_spinlock_t lock;\n };\n \n static inline uint16_t\n@@ -124,4 +125,7 @@ uint16_t cpfl_dummy_recv_pkts(void *queue,\n uint16_t cpfl_dummy_xmit_pkts(void *queue,\n \t\t\t struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n+uint16_t cpfl_xmit_pkts_to_vsi(struct cpfl_tx_queue *txq,\n+\t\t\t struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts, uint16_t vsi_id);\n #endif /* _CPFL_RXTX_H_ */\n", "prefixes": [ "16/19" ] }