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GET /api/patches/129877/?format=api
{ "id": 129877, "url": "http://patches.dpdk.org/api/patches/129877/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230803075038.307012-9-david.marchand@redhat.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230803075038.307012-9-david.marchand@redhat.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230803075038.307012-9-david.marchand@redhat.com", "date": "2023-08-03T07:50:31", "name": "[08/14] pci: define some PM constants", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "67363fdc612bd6719fa2b506a9de176f1bbaddae", "submitter": { "id": 1173, "url": "http://patches.dpdk.org/api/people/1173/?format=api", "name": "David Marchand", "email": "david.marchand@redhat.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230803075038.307012-9-david.marchand@redhat.com/mbox/", "series": [ { "id": 29101, "url": "http://patches.dpdk.org/api/series/29101/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29101", "date": "2023-08-03T07:50:23", "name": "Cleanup PCI(e) drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/29101/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/129877/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/129877/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C49AD42FC1;\n\tThu, 3 Aug 2023 09:51:52 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 674244326D;\n\tThu, 3 Aug 2023 09:51:21 +0200 (CEST)", "from us-smtp-delivery-124.mimecast.com\n (us-smtp-delivery-124.mimecast.com [170.10.129.124])\n by mails.dpdk.org (Postfix) with ESMTP id EFBAA4161A\n for <dev@dpdk.org>; Thu, 3 Aug 2023 09:51:19 +0200 (CEST)", "from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com\n [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS\n (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n us-mta-401-8wCHJuXdOgSgjmq_h9UTCQ-1; Thu, 03 Aug 2023 03:51:16 -0400", "from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com\n [10.11.54.3])\n (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n (No client certificate requested)\n by mimecast-mx02.redhat.com (Postfix) with ESMTPS id DCF0E803FDC;\n Thu, 3 Aug 2023 07:51:15 +0000 (UTC)", "from dmarchan.redhat.com (unknown [10.45.224.120])\n by smtp.corp.redhat.com (Postfix) with ESMTP id 9782F1121325;\n Thu, 3 Aug 2023 07:51:14 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1691049079;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=FzcgL50t9WptunuoNahpG5w2gKKASJhPStJaGmhuhOs=;\n b=V6nk2Hqz4dAhELtl1ScHkVbR7RSHpO0ZrmsjLkXeud5fBEQeH2itPZvcb/1A4+Fa2UECg7\n zoGIk0NYl6tVN3xJ+tIsor/N7QlTr9EqsOUz7exbAfM3aai1wRn0p9WJMvxeJ2asAcZYuu\n dcEfsLUhDTODsuVgn/dFFnLTSVxTI04=", "X-MC-Unique": "8wCHJuXdOgSgjmq_h9UTCQ-1", "From": "David Marchand <david.marchand@redhat.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com,\n nipun.gupta@amd.com, Julien Aube <julien_dpdk@jaube.fr>,\n Gaetan Rivet <grive@u256.net>", "Subject": "[PATCH 08/14] pci: define some PM constants", "Date": "Thu, 3 Aug 2023 09:50:31 +0200", "Message-ID": "<20230803075038.307012-9-david.marchand@redhat.com>", "In-Reply-To": "<20230803075038.307012-1-david.marchand@redhat.com>", "References": "<20230803075038.307012-1-david.marchand@redhat.com>", "MIME-Version": "1.0", "X-Scanned-By": "MIMEDefang 3.1 on 10.11.54.3", "X-Mimecast-Spam-Score": "0", "X-Mimecast-Originator": "redhat.com", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain; charset=\"US-ASCII\"; x-default=true", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Define some PCI Power Management constants and use them in existing\ndrivers.\n\nSigned-off-by: David Marchand <david.marchand@redhat.com>\n---\n drivers/net/bnx2x/bnx2x.c | 17 +++++++++--------\n drivers/net/bnx2x/bnx2x.h | 5 -----\n lib/pci/rte_pci.h | 6 ++++++\n 3 files changed, 15 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex e3f14400cc..faf061beba 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -5843,17 +5843,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)\n \t\treturn 0;\n \t}\n \n-\tpci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,\n+\tpci_read(sc, (sc->devinfo.pcie_pm_cap_reg + RTE_PCI_PM_CTRL), &pmcsr,\n \t\t 2);\n \n \tswitch (state) {\n \tcase PCI_PM_D0:\n \t\tpci_write_word(sc,\n \t\t\t (sc->devinfo.pcie_pm_cap_reg +\n-\t\t\t\tPCIR_POWER_STATUS),\n-\t\t\t ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));\n+\t\t\t\tRTE_PCI_PM_CTRL),\n+\t\t\t ((pmcsr & ~RTE_PCI_PM_CTRL_STATE_MASK) | RTE_PCI_PM_CTRL_PME_STATUS));\n \n-\t\tif (pmcsr & PCIM_PSTAT_DMASK) {\n+\t\tif (pmcsr & RTE_PCI_PM_CTRL_STATE_MASK) {\n \t\t\t/* delay required during transition out of D3hot */\n \t\t\tDELAY(20000);\n \t\t}\n@@ -5866,16 +5866,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)\n \t\t\treturn 0;\n \t\t}\n \n-\t\tpmcsr &= ~PCIM_PSTAT_DMASK;\n-\t\tpmcsr |= PCIM_PSTAT_D3;\n+\t\tpmcsr &= ~RTE_PCI_PM_CTRL_STATE_MASK;\n+\t\t/* D3 power state */\n+\t\tpmcsr |= 0x3;\n \n \t\tif (sc->wol) {\n-\t\t\tpmcsr |= PCIM_PSTAT_PMEENABLE;\n+\t\t\tpmcsr |= RTE_PCI_PM_CTRL_PME_ENABLE;\n \t\t}\n \n \t\tpci_write_long(sc,\n \t\t\t (sc->devinfo.pcie_pm_cap_reg +\n-\t\t\t\tPCIR_POWER_STATUS), pmcsr);\n+\t\t\t\tRTE_PCI_PM_CTRL), pmcsr);\n \n \t\t/*\n \t\t * No more memory access after this point until device is brought back\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 60af75d336..1efa166316 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -41,11 +41,6 @@\n #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL\n #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD\n #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ\n-#define PCIR_POWER_STATUS PCI_PM_CTRL\n-#define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK\n-#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS\n-#define PCIM_PSTAT_D3 0x3\n-#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE\n #else\n #include <dev/pci/pcireg.h>\n #endif\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex 429904cff9..b7e1ff5d78 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -56,6 +56,12 @@ extern \"C\" {\n #define RTE_PCI_CAP_ID_MSIX\t0x11\t/* MSI-X */\n #define RTE_PCI_CAP_SIZEOF\t4\n \n+/* Power Management Registers */\n+#define RTE_PCI_PM_CTRL\t\t\t4\t/* PM control and status register */\n+#define RTE_PCI_PM_CTRL_STATE_MASK\t0x0003\t/* Current power state (D0 to D3) */\n+#define RTE_PCI_PM_CTRL_PME_ENABLE\t0x0100\t/* PME pin enable */\n+#define RTE_PCI_PM_CTRL_PME_STATUS\t0x8000\t/* PME pin status */\n+\n /* MSI-X registers */\n #define RTE_PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n #define RTE_PCI_MSIX_FLAGS_QSIZE\t0x07ff\t/* Table size */\n", "prefixes": [ "08/14" ] }