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GET /api/patches/128996/?format=api
{ "id": 128996, "url": "http://patches.dpdk.org/api/patches/128996/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230626112906.1455326-1-vikash.chandrax.poddar@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230626112906.1455326-1-vikash.chandrax.poddar@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230626112906.1455326-1-vikash.chandrax.poddar@intel.com", "date": "2023-06-26T11:29:06", "name": "[v3] common/qat: fix detach QAT crypto compress build", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "73010b6c13159e700ea87e49444382d32f6ebbf5", "submitter": { "id": 2961, "url": "http://patches.dpdk.org/api/people/2961/?format=api", "name": "Vikash Poddar", "email": "vikash.chandrax.poddar@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230626112906.1455326-1-vikash.chandrax.poddar@intel.com/mbox/", "series": [ { "id": 28650, "url": "http://patches.dpdk.org/api/series/28650/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28650", "date": "2023-06-26T11:29:06", "name": "[v3] common/qat: fix detach QAT crypto compress build", "version": 3, "mbox": "http://patches.dpdk.org/series/28650/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128996/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/128996/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1719142D59;\n\tMon, 26 Jun 2023 13:29:38 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E156041149;\n\tMon, 26 Jun 2023 13:29:37 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 692E54067B;\n Mon, 26 Jun 2023 13:29:35 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Jun 2023 04:29:34 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com.) ([10.237.222.80])\n by fmsmga002.fm.intel.com with ESMTP; 26 Jun 2023 04:29:31 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1687778975; x=1719314975;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=rJdOkM13BIJFEG/c9MbQMi1r9A5b9vxy8ln6/0EDbhs=;\n b=DQp/pKqQXUIVKsdDpkPJfEHTaOGYqjUZ9w25uxbc2bZa5B0PS5l+bDez\n pyhPdMHvr0JZVm8+hnHt0E5ruhlFPQS3mYheGYLsvorDEEAky1k3/y5kz\n 86fPxn30HgaCk5TWBow8LJsuGD27WnEmCKphcQBpxNRrv/Gxt3GCmWSvw\n JsIfQyJavEbxlBURiEwyFYQ2yJNAp+wfwC8aPqslUcdPdh07m3gyFJSs7\n fXdXvWNahEm3KwVVpUMkWPoXBqf23AMfPbc8aw5hMEK2Qbmvl4bUwfZPA\n PU3MoXq4vVXeJ2YMMimPJadycxxW0q+1gv4WRDlbI8tFjaeLf6R8F7y15 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10752\"; a=\"424912706\"", "E=Sophos;i=\"6.01,159,1684825200\"; d=\"scan'208\";a=\"424912706\"", "E=McAfee;i=\"6600,9927,10752\"; a=\"829195712\"", "E=Sophos;i=\"6.01,159,1684825200\"; d=\"scan'208\";a=\"829195712\"" ], "X-ExtLoop1": "1", "From": "Vikash Poddar <vikash.chandrax.poddar@intel.com>", "To": "Kai Ji <kai.ji@intel.com>, Fan Zhang <fanzhang.oss@gmail.com>,\n Ashish Gupta <ashish.gupta@marvell.com>", "Cc": "dev@dpdk.org, Vikash Poddar <vikash.chandrax.poddar@intel.com>,\n bruce.richardson@intel.com, stable@dpdk.org", "Subject": "[PATCH v3] common/qat: fix detach QAT crypto compress build", "Date": "Mon, 26 Jun 2023 11:29:06 +0000", "Message-Id": "<20230626112906.1455326-1-vikash.chandrax.poddar@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230623144747.1379182-1-vikash.chandrax.poddar@intel.com>", "References": "<20230623144747.1379182-1-vikash.chandrax.poddar@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "qat_qp.c is a common file for QAT crypto and\ncompress. Moved compress function from common\nfile to compress QAT file qat_comp.c\n\nBugzilla ID: 1237\nFixes: 2ca75c65af4c (\"common/qat: build drivers from common folder\")\nCc: bruce.richardson@intel.com\nCc: stable@dpdk.org\n\nSigned-off-by: Vikash Poddar <vikash.chandrax.poddar@intel.com>\n---\nv3:\nFixed commit message\nv2:\nFixed coding style issue\n---\n drivers/common/qat/meson.build | 8 --\n drivers/common/qat/qat_qp.c | 187 --------------------------------\n drivers/common/qat/qat_qp.h | 20 +++-\n drivers/compress/qat/qat_comp.c | 182 +++++++++++++++++++++++++++++++\n drivers/compress/qat/qat_comp.h | 3 +\n 5 files changed, 201 insertions(+), 199 deletions(-)", "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex b84e5b3c6c..95b52b78c3 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -54,14 +54,6 @@ if libipsecmb.found() and libcrypto_3.found()\n endif\n endif\n \n-# The driver should not build if both compression and crypto are disabled\n-#FIXME common code depends on compression files so check only compress!\n-if not qat_compress # and not qat_crypto\n- build = false\n- reason = '' # rely on reason for compress/crypto above\n- subdir_done()\n-endif\n-\n deps += ['bus_pci', 'cryptodev', 'net', 'compressdev']\n sources += files(\n 'qat_common.c',\ndiff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 348a1d574d..197e8bac75 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -490,20 +490,6 @@ adf_configure_queues(struct qat_qp *qp, enum qat_device_gen qat_dev_gen)\n \treturn 0;\n }\n \n-static inline void\n-txq_write_tail(enum qat_device_gen qat_dev_gen,\n-\t\tstruct qat_qp *qp, struct qat_queue *q)\n-{\n-\tstruct qat_qp_hw_spec_funcs *ops =\n-\t\tqat_qp_hw_spec[qat_dev_gen];\n-\n-\t/*\n-\t * Pointer check should be done during\n-\t * initialization\n-\t */\n-\tops->qat_qp_csr_write_tail(qp, q);\n-}\n-\n static inline void\n qat_qp_csr_write_head(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,\n \t\t\tstruct qat_queue *q, uint32_t new_head)\n@@ -672,179 +658,6 @@ qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,\n \treturn nb_ops_sent;\n }\n \n-/* Use this for compression only - but keep consistent with above common\n- * function as much as possible.\n- */\n-uint16_t\n-qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)\n-{\n-\tregister struct qat_queue *queue;\n-\tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n-\tregister uint32_t nb_ops_sent = 0;\n-\tregister int nb_desc_to_build;\n-\tuint16_t nb_ops_possible = nb_ops;\n-\tregister uint8_t *base_addr;\n-\tregister uint32_t tail;\n-\n-\tint descriptors_built, total_descriptors_built = 0;\n-\tint nb_remaining_descriptors;\n-\tint overflow = 0;\n-\n-\tif (unlikely(nb_ops == 0))\n-\t\treturn 0;\n-\n-\t/* read params used a lot in main loop into registers */\n-\tqueue = &(tmp_qp->tx_q);\n-\tbase_addr = (uint8_t *)queue->base_addr;\n-\ttail = queue->tail;\n-\n-\t/* Find how many can actually fit on the ring */\n-\t{\n-\t\t/* dequeued can only be written by one thread, but it may not\n-\t\t * be this thread. As it's 4-byte aligned it will be read\n-\t\t * atomically here by any Intel CPU.\n-\t\t * enqueued can wrap before dequeued, but cannot\n-\t\t * lap it as var size of enq/deq (uint32_t) > var size of\n-\t\t * max_inflights (uint16_t). In reality inflights is never\n-\t\t * even as big as max uint16_t, as it's <= ADF_MAX_DESC.\n-\t\t * On wrapping, the calculation still returns the correct\n-\t\t * positive value as all three vars are unsigned.\n-\t\t */\n-\t\tuint32_t inflights =\n-\t\t\ttmp_qp->enqueued - tmp_qp->dequeued;\n-\n-\t\t/* Find how many can actually fit on the ring */\n-\t\toverflow = (inflights + nb_ops) - tmp_qp->max_inflights;\n-\t\tif (overflow > 0) {\n-\t\t\tnb_ops_possible = nb_ops - overflow;\n-\t\t\tif (nb_ops_possible == 0)\n-\t\t\t\treturn 0;\n-\t\t}\n-\n-\t\t/* QAT has plenty of work queued already, so don't waste cycles\n-\t\t * enqueueing, wait til the application has gathered a bigger\n-\t\t * burst or some completed ops have been dequeued\n-\t\t */\n-\t\tif (tmp_qp->min_enq_burst_threshold && inflights >\n-\t\t\t\tQAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <\n-\t\t\t\ttmp_qp->min_enq_burst_threshold) {\n-\t\t\ttmp_qp->stats.threshold_hit_count++;\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\n-\t/* At this point nb_ops_possible is assuming a 1:1 mapping\n-\t * between ops and descriptors.\n-\t * Fewer may be sent if some ops have to be split.\n-\t * nb_ops_possible is <= burst size.\n-\t * Find out how many spaces are actually available on the qp in case\n-\t * more are needed.\n-\t */\n-\tnb_remaining_descriptors = nb_ops_possible\n-\t\t\t + ((overflow >= 0) ? 0 : overflow * (-1));\n-\tQAT_DP_LOG(DEBUG, \"Nb ops requested %d, nb descriptors remaining %d\",\n-\t\t\tnb_ops, nb_remaining_descriptors);\n-\n-\twhile (nb_ops_sent != nb_ops_possible &&\n-\t\t\t\tnb_remaining_descriptors > 0) {\n-\t\tstruct qat_comp_op_cookie *cookie =\n-\t\t\t\ttmp_qp->op_cookies[tail >> queue->trailz];\n-\n-\t\tdescriptors_built = 0;\n-\n-\t\tQAT_DP_LOG(DEBUG, \"--- data length: %u\",\n-\t\t\t ((struct rte_comp_op *)*ops)->src.length);\n-\n-\t\tnb_desc_to_build = qat_comp_build_request(*ops,\n-\t\t\t\tbase_addr + tail, cookie, tmp_qp->qat_dev_gen);\n-\t\tQAT_DP_LOG(DEBUG, \"%d descriptors built, %d remaining, \"\n-\t\t\t\"%d ops sent, %d descriptors needed\",\n-\t\t\ttotal_descriptors_built, nb_remaining_descriptors,\n-\t\t\tnb_ops_sent, nb_desc_to_build);\n-\n-\t\tif (unlikely(nb_desc_to_build < 0)) {\n-\t\t\t/* this message cannot be enqueued */\n-\t\t\ttmp_qp->stats.enqueue_err_count++;\n-\t\t\tif (nb_ops_sent == 0)\n-\t\t\t\treturn 0;\n-\t\t\tgoto kick_tail;\n-\t\t} else if (unlikely(nb_desc_to_build > 1)) {\n-\t\t\t/* this op is too big and must be split - get more\n-\t\t\t * descriptors and retry\n-\t\t\t */\n-\n-\t\t\tQAT_DP_LOG(DEBUG, \"Build %d descriptors for this op\",\n-\t\t\t\t\tnb_desc_to_build);\n-\n-\t\t\tnb_remaining_descriptors -= nb_desc_to_build;\n-\t\t\tif (nb_remaining_descriptors >= 0) {\n-\t\t\t\t/* There are enough remaining descriptors\n-\t\t\t\t * so retry\n-\t\t\t\t */\n-\t\t\t\tint ret2 = qat_comp_build_multiple_requests(\n-\t\t\t\t\t\t*ops, tmp_qp, tail,\n-\t\t\t\t\t\tnb_desc_to_build);\n-\n-\t\t\t\tif (unlikely(ret2 < 1)) {\n-\t\t\t\t\tQAT_DP_LOG(DEBUG,\n-\t\t\t\t\t\t\t\"Failed to build (%d) descriptors, status %d\",\n-\t\t\t\t\t\t\tnb_desc_to_build, ret2);\n-\n-\t\t\t\t\tqat_comp_free_split_op_memzones(cookie,\n-\t\t\t\t\t\t\tnb_desc_to_build - 1);\n-\n-\t\t\t\t\ttmp_qp->stats.enqueue_err_count++;\n-\n-\t\t\t\t\t/* This message cannot be enqueued */\n-\t\t\t\t\tif (nb_ops_sent == 0)\n-\t\t\t\t\t\treturn 0;\n-\t\t\t\t\tgoto kick_tail;\n-\t\t\t\t} else {\n-\t\t\t\t\tdescriptors_built = ret2;\n-\t\t\t\t\ttotal_descriptors_built +=\n-\t\t\t\t\t\t\tdescriptors_built;\n-\t\t\t\t\tnb_remaining_descriptors -=\n-\t\t\t\t\t\t\tdescriptors_built;\n-\t\t\t\t\tQAT_DP_LOG(DEBUG,\n-\t\t\t\t\t\t\t\"Multiple descriptors (%d) built ok\",\n-\t\t\t\t\t\t\tdescriptors_built);\n-\t\t\t\t}\n-\t\t\t} else {\n-\t\t\t\tQAT_DP_LOG(ERR, \"For the current op, number of requested descriptors (%d) \"\n-\t\t\t\t\t\t\"exceeds number of available descriptors (%d)\",\n-\t\t\t\t\t\tnb_desc_to_build,\n-\t\t\t\t\t\tnb_remaining_descriptors +\n-\t\t\t\t\t\t\tnb_desc_to_build);\n-\n-\t\t\t\tqat_comp_free_split_op_memzones(cookie,\n-\t\t\t\t\t\tnb_desc_to_build - 1);\n-\n-\t\t\t\t/* Not enough extra descriptors */\n-\t\t\t\tif (nb_ops_sent == 0)\n-\t\t\t\t\treturn 0;\n-\t\t\t\tgoto kick_tail;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tdescriptors_built = 1;\n-\t\t\ttotal_descriptors_built++;\n-\t\t\tnb_remaining_descriptors--;\n-\t\t\tQAT_DP_LOG(DEBUG, \"Single descriptor built ok\");\n-\t\t}\n-\n-\t\ttail = adf_modulo(tail + (queue->msg_size * descriptors_built),\n-\t\t\t\t queue->modulo_mask);\n-\t\tops++;\n-\t\tnb_ops_sent++;\n-\t}\n-\n-kick_tail:\n-\tqueue->tail = tail;\n-\ttmp_qp->enqueued += total_descriptors_built;\n-\ttmp_qp->stats.enqueued_count += nb_ops_sent;\n-\ttxq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);\n-\treturn nb_ops_sent;\n-}\n-\n uint16_t\n qat_dequeue_op_burst(void *qp, void **ops,\n \t\tqat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops)\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex d19fc387e4..ae18fb942e 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -127,9 +127,6 @@ uint16_t\n qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,\n \t\tvoid **ops, uint16_t nb_ops);\n \n-uint16_t\n-qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);\n-\n uint16_t\n qat_dequeue_op_burst(void *qp, void **ops,\n \t\tqat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);\n@@ -206,6 +203,21 @@ struct qat_qp_hw_spec_funcs {\n \tqat_qp_get_hw_data_t\t\tqat_qp_get_hw_data;\n };\n \n-extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];\n+extern struct qat_qp_hw_spec_funcs*\n+\tqat_qp_hw_spec[];\n+\n+static inline void\n+txq_write_tail(enum qat_device_gen qat_dev_gen,\n+\t\tstruct qat_qp *qp, struct qat_queue *q)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev_gen];\n+\n+\t/*\n+\t * Pointer check should be done during\n+\t * initialization\n+\t */\n+\tops->qat_qp_csr_write_tail(qp, q);\n+}\n \n #endif /* _QAT_QP_H_ */\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex fe4a4999c6..559948a46a 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -1144,3 +1144,185 @@ qat_comp_stream_free(struct rte_compressdev *dev, void *stream)\n \t}\n \treturn -EINVAL;\n }\n+\n+/**\n+ * Enqueue packets for processing on queue pair of a device\n+ *\n+ * @param qp\n+ * qat queue pair\n+ * @param ops\n+ * Compressdev operation\n+ * @param nb_ops\n+ * number of operations\n+ * @return\n+ * - nb_ops_sent if successful\n+ */\n+uint16_t\n+qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)\n+{\n+\tregister struct qat_queue *queue;\n+\tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n+\tregister uint32_t nb_ops_sent = 0;\n+\tregister int nb_desc_to_build;\n+\tuint16_t nb_ops_possible = nb_ops;\n+\tregister uint8_t *base_addr;\n+\tregister uint32_t tail;\n+\n+\tint descriptors_built, total_descriptors_built = 0;\n+\tint nb_remaining_descriptors;\n+\tint overflow = 0;\n+\n+\tif (unlikely(nb_ops == 0))\n+\t\treturn 0;\n+\n+\t/* read params used a lot in main loop into registers */\n+\tqueue = &(tmp_qp->tx_q);\n+\tbase_addr = (uint8_t *)queue->base_addr;\n+\ttail = queue->tail;\n+\n+\t/* Find how many can actually fit on the ring */\n+\t{\n+\t\t/* dequeued can only be written by one thread, but it may not\n+\t\t * be this thread. As it's 4-byte aligned it will be read\n+\t\t * atomically here by any Intel CPU.\n+\t\t * enqueued can wrap before dequeued, but cannot\n+\t\t * lap it as var size of enq/deq (uint32_t) > var size of\n+\t\t * max_inflights (uint16_t). In reality inflights is never\n+\t\t * even as big as max uint16_t, as it's <= ADF_MAX_DESC.\n+\t\t * On wrapping, the calculation still returns the correct\n+\t\t * positive value as all three vars are unsigned.\n+\t\t */\n+\t\tuint32_t inflights =\n+\t\t\ttmp_qp->enqueued - tmp_qp->dequeued;\n+\n+\t\t/* Find how many can actually fit on the ring */\n+\t\toverflow = (inflights + nb_ops) - tmp_qp->max_inflights;\n+\t\tif (overflow > 0) {\n+\t\t\tnb_ops_possible = nb_ops - overflow;\n+\t\t\tif (nb_ops_possible == 0)\n+\t\t\t\treturn 0;\n+\t\t}\n+\n+\t\t/* QAT has plenty of work queued already, so don't waste cycles\n+\t\t * enqueueing, wait til the application has gathered a bigger\n+\t\t * burst or some completed ops have been dequeued\n+\t\t */\n+\t\tif (tmp_qp->min_enq_burst_threshold && inflights >\n+\t\t\t\tQAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <\n+\t\t\t\ttmp_qp->min_enq_burst_threshold) {\n+\t\t\ttmp_qp->stats.threshold_hit_count++;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\t/* At this point nb_ops_possible is assuming a 1:1 mapping\n+\t * between ops and descriptors.\n+\t * Fewer may be sent if some ops have to be split.\n+\t * nb_ops_possible is <= burst size.\n+\t * Find out how many spaces are actually available on the qp in case\n+\t * more are needed.\n+\t */\n+\tnb_remaining_descriptors = nb_ops_possible\n+\t\t\t + ((overflow >= 0) ? 0 : overflow * (-1));\n+\tQAT_DP_LOG(DEBUG, \"Nb ops requested %d, nb descriptors remaining %d\",\n+\t\t\tnb_ops, nb_remaining_descriptors);\n+\n+\twhile (nb_ops_sent != nb_ops_possible &&\n+\t\t\t\tnb_remaining_descriptors > 0) {\n+\t\tstruct qat_comp_op_cookie *cookie =\n+\t\t\t\ttmp_qp->op_cookies[tail >> queue->trailz];\n+\n+\t\tdescriptors_built = 0;\n+\n+\t\tQAT_DP_LOG(DEBUG, \"--- data length: %u\",\n+\t\t\t ((struct rte_comp_op *)*ops)->src.length);\n+\n+\t\tnb_desc_to_build = qat_comp_build_request(*ops,\n+\t\t\t\tbase_addr + tail, cookie, tmp_qp->qat_dev_gen);\n+\t\tQAT_DP_LOG(DEBUG, \"%d descriptors built, %d remaining, \"\n+\t\t\t\"%d ops sent, %d descriptors needed\",\n+\t\t\ttotal_descriptors_built, nb_remaining_descriptors,\n+\t\t\tnb_ops_sent, nb_desc_to_build);\n+\n+\t\tif (unlikely(nb_desc_to_build < 0)) {\n+\t\t\t/* this message cannot be enqueued */\n+\t\t\ttmp_qp->stats.enqueue_err_count++;\n+\t\t\tif (nb_ops_sent == 0)\n+\t\t\t\treturn 0;\n+\t\t\tgoto kick_tail;\n+\t\t} else if (unlikely(nb_desc_to_build > 1)) {\n+\t\t\t/* this op is too big and must be split - get more\n+\t\t\t * descriptors and retry\n+\t\t\t */\n+\n+\t\t\tQAT_DP_LOG(DEBUG, \"Build %d descriptors for this op\",\n+\t\t\t\t\tnb_desc_to_build);\n+\n+\t\t\tnb_remaining_descriptors -= nb_desc_to_build;\n+\t\t\tif (nb_remaining_descriptors >= 0) {\n+\t\t\t\t/* There are enough remaining descriptors\n+\t\t\t\t * so retry\n+\t\t\t\t */\n+\t\t\t\tint ret2 = qat_comp_build_multiple_requests(\n+\t\t\t\t\t\t*ops, tmp_qp, tail,\n+\t\t\t\t\t\tnb_desc_to_build);\n+\n+\t\t\t\tif (unlikely(ret2 < 1)) {\n+\t\t\t\t\tQAT_DP_LOG(DEBUG,\n+\t\t\t\t\t\t\t\"Failed to build (%d) descriptors, status %d\",\n+\t\t\t\t\t\t\tnb_desc_to_build, ret2);\n+\n+\t\t\t\t\tqat_comp_free_split_op_memzones(cookie,\n+\t\t\t\t\t\t\tnb_desc_to_build - 1);\n+\n+\t\t\t\t\ttmp_qp->stats.enqueue_err_count++;\n+\n+\t\t\t\t\t/* This message cannot be enqueued */\n+\t\t\t\t\tif (nb_ops_sent == 0)\n+\t\t\t\t\t\treturn 0;\n+\t\t\t\t\tgoto kick_tail;\n+\t\t\t\t} else {\n+\t\t\t\t\tdescriptors_built = ret2;\n+\t\t\t\t\ttotal_descriptors_built +=\n+\t\t\t\t\t\t\tdescriptors_built;\n+\t\t\t\t\tnb_remaining_descriptors -=\n+\t\t\t\t\t\t\tdescriptors_built;\n+\t\t\t\t\tQAT_DP_LOG(DEBUG,\n+\t\t\t\t\t\t\t\"Multiple descriptors (%d) built ok\",\n+\t\t\t\t\t\t\tdescriptors_built);\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tQAT_DP_LOG(ERR, \"For the current op, number of requested descriptors (%d) \"\n+\t\t\t\t\t\t\"exceeds number of available descriptors (%d)\",\n+\t\t\t\t\t\tnb_desc_to_build,\n+\t\t\t\t\t\tnb_remaining_descriptors +\n+\t\t\t\t\t\t\tnb_desc_to_build);\n+\n+\t\t\t\tqat_comp_free_split_op_memzones(cookie,\n+\t\t\t\t\t\tnb_desc_to_build - 1);\n+\n+\t\t\t\t/* Not enough extra descriptors */\n+\t\t\t\tif (nb_ops_sent == 0)\n+\t\t\t\t\treturn 0;\n+\t\t\t\tgoto kick_tail;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tdescriptors_built = 1;\n+\t\t\ttotal_descriptors_built++;\n+\t\t\tnb_remaining_descriptors--;\n+\t\t\tQAT_DP_LOG(DEBUG, \"Single descriptor built ok\");\n+\t\t}\n+\n+\t\ttail = adf_modulo(tail + (queue->msg_size * descriptors_built),\n+\t\t\t\t queue->modulo_mask);\n+\t\tops++;\n+\t\tnb_ops_sent++;\n+\t}\n+\n+kick_tail:\n+\tqueue->tail = tail;\n+\ttmp_qp->enqueued += total_descriptors_built;\n+\ttmp_qp->stats.enqueued_count += nb_ops_sent;\n+\ttxq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);\n+\treturn nb_ops_sent;\n+}\ndiff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h\nindex da7b9a6eec..dc220cd6e3 100644\n--- a/drivers/compress/qat/qat_comp.h\n+++ b/drivers/compress/qat/qat_comp.h\n@@ -141,5 +141,8 @@ qat_comp_stream_create(struct rte_compressdev *dev,\n int\n qat_comp_stream_free(struct rte_compressdev *dev, void *stream);\n \n+uint16_t\n+qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);\n+\n #endif\n #endif\n", "prefixes": [ "v3" ] }