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{
    "id": 128715,
    "url": "http://patches.dpdk.org/api/patches/128715/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230614175623.153833-1-arkadiuszx.kusztal@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230614175623.153833-1-arkadiuszx.kusztal@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230614175623.153833-1-arkadiuszx.kusztal@intel.com",
    "date": "2023-06-14T17:56:23",
    "name": "[v3] crypto/qat: add SM3 HMAC to gen4 devices",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8e91b68aa4b0817c8768603acae30575ce839222",
    "submitter": {
        "id": 452,
        "url": "http://patches.dpdk.org/api/people/452/?format=api",
        "name": "Arkadiusz Kusztal",
        "email": "arkadiuszx.kusztal@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230614175623.153833-1-arkadiuszx.kusztal@intel.com/mbox/",
    "series": [
        {
            "id": 28516,
            "url": "http://patches.dpdk.org/api/series/28516/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28516",
            "date": "2023-06-14T17:56:23",
            "name": "[v3] crypto/qat: add SM3 HMAC to gen4 devices",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/28516/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/128715/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/128715/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EECC142CB8;\n\tWed, 14 Jun 2023 19:56:30 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7FD6940FAE;\n\tWed, 14 Jun 2023 19:56:30 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 6FA5B40E0F\n for <dev@dpdk.org>; Wed, 14 Jun 2023 19:56:28 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Jun 2023 10:56:26 -0700",
            "from silpixa00401012.ir.intel.com ([10.243.23.125])\n by orsmga008.jf.intel.com with ESMTP; 14 Jun 2023 10:56:25 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1686765388; x=1718301388;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=cgYv8CfOHIKqrefl2JlJu8rHch9K7Q6mtotOSd0E/Zs=;\n b=A9z/oZyKgJPV3ISyrW1el+KMlNNuCx3pd5BXX99+8jDcxrkCPzE5//2u\n wkXLcUd06y3tSRY+j3nsYLQsvi+Y3vBT7o5R5T5o3x/RUgJ8SH4hFnuq3\n fgol7yQLbPfrybS7Opw3M0lHOZjmwVAvPbUQm9bjlAMpKaAKvIVMEAncJ\n m7cg49u8ACqyufA0Y7uCk8S178NxMd4PI4naAOQCl62JKT1RSt2/9uRrM\n Etzws+uOOuiMKMPj4lMwZvw19qAVLUyuZplINtYOexT1uW+EQYtyFsLU6\n Rj07hIGoPfDzb/FiafEm2fWKw1Paj7GMiF5u6+OlvvkDDCousWSvig49G A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10741\"; a=\"424577184\"",
            "E=Sophos;i=\"6.00,243,1681196400\"; d=\"scan'208\";a=\"424577184\"",
            "E=McAfee;i=\"6600,9927,10741\"; a=\"741908865\"",
            "E=Sophos;i=\"6.00,243,1681196400\"; d=\"scan'208\";a=\"741908865\""
        ],
        "X-ExtLoop1": "1",
        "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, kai.ji@intel.com, ciara.power@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "Subject": "[PATCH v3] crypto/qat: add SM3 HMAC to gen4 devices",
        "Date": "Wed, 14 Jun 2023 17:56:23 +0000",
        "Message-Id": "<20230614175623.153833-1-arkadiuszx.kusztal@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This commit adds SM3 HMAC to Intel QuickAssist Technology PMD\ngeneration 3 and 4 devices.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\nv2:\n- Fixed problem with chaining operations\n- Added implementation of prefix tables\nv3:\n- Added support for gen3 devices\n\n doc/guides/cryptodevs/features/qat.ini       |   1 +\n doc/guides/cryptodevs/qat.rst                |   5 +\n drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  10 ++\n drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |   4 +\n drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |   4 +\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  12 +++\n drivers/crypto/qat/qat_sym_session.c         | 100 +++++++++++++++----\n drivers/crypto/qat/qat_sym_session.h         |   7 ++\n 8 files changed, 122 insertions(+), 21 deletions(-)",
    "diff": "diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini\nindex 70511a3076..6358a43357 100644\n--- a/doc/guides/cryptodevs/features/qat.ini\n+++ b/doc/guides/cryptodevs/features/qat.ini\n@@ -70,6 +70,7 @@ AES XCBC MAC = Y\n ZUC EIA3     = Y\n AES CMAC (128) = Y\n SM3          = Y\n+SM3 HMAC     = Y\n \n ;\n ; Supported AEAD algorithms of the 'qat' crypto driver.\ndiff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex a4a25711ed..2403430cd6 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -51,6 +51,9 @@ Cipher algorithms:\n * ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``\n * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``\n * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``\n+* ``RTE_CRYPTO_CIPHER_SM4_ECB``\n+* ``RTE_CRYPTO_CIPHER_SM4_CBC``\n+* ``RTE_CRYPTO_CIPHER_SM4_CTR``\n \n Hash algorithms:\n \n@@ -76,6 +79,8 @@ Hash algorithms:\n * ``RTE_CRYPTO_AUTH_AES_GMAC``\n * ``RTE_CRYPTO_AUTH_ZUC_EIA3``\n * ``RTE_CRYPTO_AUTH_AES_CMAC``\n+* ``RTE_CRYPTO_AUTH_SM3``\n+* ``RTE_CRYPTO_AUTH_SM3_HMAC``\n \n Supported AEAD algorithms:\n \ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 227a6cebc8..70f0effa62 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -188,6 +188,16 @@ struct icp_qat_fw_la_bulk_req {\n \tQAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \\\n \tQAT_LA_PARTIAL_MASK)\n \n+#define QAT_FW_LA_MODE2 1\n+#define QAT_FW_LA_NO_MODE2 0\n+#define QAT_FW_LA_MODE2_MASK 0x1\n+#define QAT_FW_LA_MODE2_BITPOS 5\n+#define ICP_QAT_FW_HASH_FLAG_MODE2_SET(flags, val) \\\n+QAT_FIELD_SET(flags, \\\n+\t\tval, \\\n+\t\tQAT_FW_LA_MODE2_BITPOS, \\\n+\t\tQAT_FW_LA_MODE2_MASK)\n+\n struct icp_qat_fw_cipher_req_hdr_cd_pars {\n \tunion {\n \t\tstruct {\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\nindex 6013fed721..733d690339 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n@@ -155,6 +155,10 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {\n \tQAT_SYM_PLAIN_AUTH_CAP(SM3,\n \t\tCAP_SET(block_size, 64),\n \t\tCAP_RNG(digest_size, 32, 32, 0)),\n+\tQAT_SYM_AUTH_CAP(SM3_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 16, 64, 4), CAP_RNG(digest_size, 32, 32, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\nindex b219a418ba..a7f50c73df 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n@@ -103,6 +103,10 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {\n \tQAT_SYM_PLAIN_AUTH_CAP(SM3,\n \t\tCAP_SET(block_size, 64),\n \t\tCAP_RNG(digest_size, 32, 32, 0)),\n+\tQAT_SYM_AUTH_CAP(SM3_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 16, 64, 4), CAP_RNG(digest_size, 32, 32, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex e8e92e22d4..6f13a46a78 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -625,6 +625,12 @@ enqueue_one_auth_job_gen1(struct qat_sym_session *ctx,\n \t\trte_memcpy(cipher_param->u.cipher_IV_array, auth_iv->va,\n \t\t\t\tctx->auth_iv.length);\n \t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SM3:\n+\t\tif (ctx->auth_mode == ICP_QAT_HW_AUTH_MODE0)\n+\t\t\tauth_param->u1.aad_adr = 0;\n+\t\telse\n+\t\t\tauth_param->u1.aad_adr = ctx->prefix_paddr;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -678,6 +684,12 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n \t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SM3:\n+\t\tif (ctx->auth_mode == ICP_QAT_HW_AUTH_MODE0)\n+\t\t\tauth_param->u1.aad_adr = 0;\n+\t\telse\n+\t\t\tauth_param->u1.aad_adr = ctx->prefix_paddr;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 9babf13b66..ba5636fcf4 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -129,11 +129,12 @@ qat_sym_cd_crc_set(struct qat_sym_session *cdesc,\n \n static int\n qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n-\t\t\t\t\t\tconst uint8_t *authkey,\n-\t\t\t\t\t\tuint32_t authkeylen,\n-\t\t\t\t\t\tuint32_t aad_length,\n-\t\t\t\t\t\tuint32_t digestsize,\n-\t\t\t\t\t\tunsigned int operation);\n+\tconst uint8_t *authkey,\n+\tuint32_t authkeylen,\n+\tuint32_t aad_length,\n+\tuint32_t digestsize,\n+\tunsigned int operation,\n+\tenum qat_device_gen qat_dev_gen);\n \n static void\n qat_sym_session_init_common_hdr(struct qat_sym_session *session);\n@@ -574,6 +575,8 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t/* Set context descriptor physical address */\n \tsession->cd_paddr = session_paddr +\n \t\t\toffsetof(struct qat_sym_session, cd);\n+\tsession->prefix_paddr = session_paddr +\n+\t\t\toffsetof(struct qat_sym_session, prefix_state);\n \n \tsession->dev_id = internals->dev_id;\n \tsession->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_NONE;\n@@ -752,6 +755,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;\n \t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n \t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SM3_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;\n+\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE2;\n+\t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA1:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n \t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n@@ -877,7 +884,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\t\t\tkey_length,\n \t\t\t\t\t\t0,\n \t\t\t\t\t\tauth_xform->digest_length,\n-\t\t\t\t\t\tauth_xform->op))\n+\t\t\t\t\t\tauth_xform->op,\n+\t\t\t\t\t\tqat_dev_gen))\n \t\t\t\treturn -EINVAL;\n \t\t} else {\n \t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n@@ -892,7 +900,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\t\tkey_length,\n \t\t\t\t\t0,\n \t\t\t\t\tauth_xform->digest_length,\n-\t\t\t\t\tauth_xform->op))\n+\t\t\t\t\tauth_xform->op,\n+\t\t\t\t\tqat_dev_gen))\n \t\t\t\treturn -EINVAL;\n \n \t\t\tif (qat_sym_cd_cipher_set(session,\n@@ -906,7 +915,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\tkey_length,\n \t\t\t\t0,\n \t\t\t\tauth_xform->digest_length,\n-\t\t\t\tauth_xform->op))\n+\t\t\t\tauth_xform->op,\n+\t\t\t\tqat_dev_gen))\n \t\t\treturn -EINVAL;\n \t}\n \n@@ -1012,7 +1022,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t\t\t\taead_xform->key.length,\n \t\t\t\t\taead_xform->aad_length,\n \t\t\t\t\taead_xform->digest_length,\n-\t\t\t\t\tcrypto_operation))\n+\t\t\t\t\tcrypto_operation,\n+\t\t\t\t\tqat_dev_gen))\n \t\t\treturn -EINVAL;\n \t} else {\n \t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n@@ -1029,7 +1040,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t\t\t\taead_xform->key.length,\n \t\t\t\t\taead_xform->aad_length,\n \t\t\t\t\taead_xform->digest_length,\n-\t\t\t\t\tcrypto_operation))\n+\t\t\t\t\tcrypto_operation,\n+\t\t\t\t\tqat_dev_gen))\n \t\t\treturn -EINVAL;\n \n \t\tif (qat_sym_cd_cipher_set(session,\n@@ -1198,6 +1210,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n \t\t/* return maximum block size in this case */\n \t\treturn SHA512_CBLOCK;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SM3:\n+\t\treturn QAT_SM3_BLOCK_SIZE;\n \tdefault:\n \t\tQAT_LOG(ERR, \"invalid hash alg %u\", qat_hash_alg);\n \t\treturn -EFAULT;\n@@ -2078,13 +2092,14 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n }\n \n int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n-\t\t\t\t\t\tconst uint8_t *authkey,\n-\t\t\t\t\t\tuint32_t authkeylen,\n-\t\t\t\t\t\tuint32_t aad_length,\n-\t\t\t\t\t\tuint32_t digestsize,\n-\t\t\t\t\t\tunsigned int operation)\n+\t\tconst uint8_t *authkey,\n+\t\tuint32_t authkeylen,\n+\t\tuint32_t aad_length,\n+\t\tuint32_t digestsize,\n+\t\tunsigned int operation,\n+\t\tenum qat_device_gen qat_dev_gen)\n {\n-\tstruct icp_qat_hw_auth_setup *hash;\n+\tstruct icp_qat_hw_auth_setup *hash, *hash_2 = NULL;\n \tstruct icp_qat_hw_cipher_algo_blk *cipherconfig;\n \tstruct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;\n \tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;\n@@ -2100,6 +2115,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \tuint32_t *aad_len = NULL;\n \tuint32_t wordIndex  = 0;\n \tuint32_t *pTempKey;\n+\tuint8_t *prefix = NULL;\n \tint ret = 0;\n \n \tif (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {\n@@ -2150,6 +2166,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SM3\n \t\t|| cdesc->is_cnt_zero\n \t\t\t)\n \t\thash->auth_counter.counter = 0;\n@@ -2161,6 +2178,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\thash->auth_counter.counter = rte_bswap32(block_size);\n \t}\n \n+\thash_cd_ctrl->hash_cfg_offset = hash_offset >> 3;\n \tcdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_auth_setup);\n \tswitch (cdesc->qat_hash_alg) {\n \tcase ICP_QAT_HW_AUTH_ALGO_SM3:\n@@ -2169,6 +2187,48 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tcdesc->qat_hash_alg);\n \t\tstate2_size = ICP_QAT_HW_SM3_STATE2_SZ;\n+\t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0)\n+\t\t\tbreak;\n+\t\thash_2 = (struct icp_qat_hw_auth_setup *)(cdesc->cd_cur_ptr +\n+\t\t\tstate1_size + state2_size);\n+\t\thash_2->auth_config.config =\n+\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE2,\n+\t\t\t\tcdesc->qat_hash_alg, digestsize);\n+\t\trte_memcpy(cdesc->cd_cur_ptr + state1_size + state2_size +\n+\t\t\tsizeof(*hash_2), sm3InitialState,\n+\t\t\tsizeof(sm3InitialState));\n+\t\thash_cd_ctrl->inner_state1_sz = state1_size;\n+\t\thash_cd_ctrl->inner_state2_sz  = state2_size;\n+\t\thash_cd_ctrl->inner_state2_offset =\n+\t\t\thash_cd_ctrl->hash_cfg_offset +\n+\t\t\t((sizeof(struct icp_qat_hw_auth_setup) +\n+\t\t\tRTE_ALIGN_CEIL(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);\n+\t\thash_cd_ctrl->outer_config_offset =\n+\t\t\thash_cd_ctrl->inner_state2_offset +\n+\t\t\t((hash_cd_ctrl->inner_state2_sz) >> 3);\n+\t\thash_cd_ctrl->outer_state1_sz = state1_size;\n+\t\thash_cd_ctrl->outer_res_sz = state2_size;\n+\t\thash_cd_ctrl->outer_prefix_sz =\n+\t\t\tqat_hash_get_block_size(cdesc->qat_hash_alg);\n+\t\thash_cd_ctrl->outer_prefix_offset =\n+\t\t\tqat_hash_get_block_size(cdesc->qat_hash_alg) >> 3;\n+\t\tauth_param->u2.inner_prefix_sz =\n+\t\t\tqat_hash_get_block_size(cdesc->qat_hash_alg);\n+\t\tauth_param->hash_state_sz = digestsize;\n+\t\tif (qat_dev_gen == QAT_GEN4) {\n+\t\t\tICP_QAT_FW_HASH_FLAG_MODE2_SET(\n+\t\t\t\thash_cd_ctrl->hash_flags,\n+\t\t\t\tQAT_FW_LA_MODE2);\n+\t\t} else {\n+\t\t\thash_cd_ctrl->hash_flags |=\n+\t\t\t\tICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED;\n+\t\t}\n+\t\tprefix = cdesc->prefix_state;\n+\t\trte_memcpy(prefix, authkey, authkeylen);\n+\t\trte_memcpy(prefix + QAT_PREFIX_SIZE, authkey,\n+\t\t\tauthkeylen);\n+\t\tcd_extra_size += sizeof(struct icp_qat_hw_auth_setup) +\n+\t\t\tstate1_size + state2_size;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n \t\tif (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {\n@@ -2529,8 +2589,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t}\n \n \t/* Auth CD config setup */\n-\thash_cd_ctrl->hash_cfg_offset = hash_offset >> 3;\n-\thash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;\n+\thash_cd_ctrl->hash_flags |= ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;\n \thash_cd_ctrl->inner_state1_sz = state1_size;\n \tif (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {\n \t\thash_cd_ctrl->inner_res_sz = 4;\n@@ -2547,13 +2606,10 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t\t((sizeof(struct icp_qat_hw_auth_setup) +\n \t\t\t RTE_ALIGN_CEIL(hash_cd_ctrl->inner_state1_sz, 8))\n \t\t\t\t\t>> 3);\n-\n \tcdesc->cd_cur_ptr += state1_size + state2_size + cd_extra_size;\n \tcd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;\n-\n \tcd_pars->u.s.content_desc_addr = cdesc->cd_paddr;\n \tcd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;\n-\n \treturn 0;\n }\n \n@@ -2860,6 +2916,8 @@ qat_sec_session_set_docsis_parameters(struct rte_cryptodev *dev,\n \t/* Set context descriptor physical address */\n \tsession->cd_paddr = session_paddr +\n \t\t\toffsetof(struct qat_sym_session, cd);\n+\tsession->prefix_paddr = session_paddr +\n+\t\t\toffsetof(struct qat_sym_session, prefix_state);\n \n \t/* Get requested QAT command id - should be cipher */\n \tqat_cmd_id = qat_get_cmd_id(xform);\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 9b5d11ac88..e9d03b232d 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -58,9 +58,14 @@\n #define QAT_CRYPTO_SLICE_UCS\t2\n #define QAT_CRYPTO_SLICE_WCP\t4\n \n+#define QAT_PREFIX_SIZE\t\t64\n+#define QAT_PREFIX_TBL_SIZE\t((QAT_PREFIX_SIZE) * 2)\n+\n #define QAT_SESSION_IS_SLICE_SET(flags, flag)\t\\\n \t(!!((flags) & (flag)))\n \n+#define QAT_SM3_BLOCK_SIZE\t64\n+\n enum qat_sym_proto_flag {\n \tQAT_CRYPTO_PROTO_FLAG_NONE = 0,\n \tQAT_CRYPTO_PROTO_FLAG_CCM = 1,\n@@ -100,8 +105,10 @@ struct qat_sym_session {\n \tenum icp_qat_hw_auth_mode auth_mode;\n \tvoid *bpi_ctx;\n \tstruct qat_sym_cd cd;\n+\tuint8_t prefix_state[QAT_PREFIX_TBL_SIZE] __rte_cache_aligned;\n \tuint8_t *cd_cur_ptr;\n \tphys_addr_t cd_paddr;\n+\tphys_addr_t prefix_paddr;\n \tstruct icp_qat_fw_la_bulk_req fw_req;\n \tuint8_t aad_len;\n \tstruct qat_crypto_instance *inst;\n",
    "prefixes": [
        "v3"
    ]
}