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GET /api/patches/128546/?format=api
{ "id": 128546, "url": "http://patches.dpdk.org/api/patches/128546/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-13-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-13-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-13-gakhil@marvell.com", "date": "2023-06-13T07:16:11", "name": "[v3,12/15] net/cnxk: add MACsec initialization", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c4e2625114349bd5271256996944f87fcab9f2c3", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-13-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128546/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/128546/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 844D842CA0;\n\tTue, 13 Jun 2023 09:18:09 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0769642D6C;\n\tTue, 13 Jun 2023 09:17:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EF91842D6D\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:17:10 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D56eUX006463; Tue, 13 Jun 2023 00:17:10 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235h3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:17:09 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:17:07 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:17:07 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id 235E75E6865;\n Tue, 13 Jun 2023 00:17:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=YAdFEOetmyP/vPinKuSsaInJH7KlT2OFIa3YsTi4nn4=;\n b=U562HJEBwEMmkMgBGxphHexyjW2PGRvui/8iXW5kgFpl4iuTbPGkZy9QVnZuyigGrwor\n MIJ6UssjPd3h3m/sQP7Rula0yLhcizRaJhevvuI/MWoCCl3jAFZXnsAQDPbHDcO+N3HW\n N1dHcne9VMIC0xltsSDbKpUT1MpgIM3Pvm4RnTADk1g3Q3sj7wgXV1vNiv2AxI0RZR8G\n d2lNx1JGFgbMVb0XDnBgZVx3zGeo01V6y9yL64f3AHlsmrmcjTxaljo6xrnpqQVpnvCO\n sFFzN5KZP3O4B+bEgQBKyKIRqLomnLuUzO7R575OHpcRxxPgVwsXd3HRZHTXjyiRYTW6 hA==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 12/15] net/cnxk: add MACsec initialization", "Date": "Tue, 13 Jun 2023 12:46:11 +0530", "Message-ID": "<20230613071614.2259604-13-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "nTq-7k22tGxO2YjS8d69rkZYoK16LeVy", "X-Proofpoint-GUID": "nTq-7k22tGxO2YjS8d69rkZYoK16LeVy", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added initialization routines for MACsec for\ncn10kb platform.\n\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/net/cnxk/cn10k_ethdev_sec.c | 6 ++\n drivers/net/cnxk/cnxk_ethdev.c | 13 +++\n drivers/net/cnxk/cnxk_ethdev.h | 14 +++\n drivers/net/cnxk/cnxk_ethdev_mcs.c | 151 ++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev_mcs.h | 61 +++++++++++\n drivers/net/cnxk/meson.build | 1 +\n 6 files changed, 246 insertions(+)\n create mode 100644 drivers/net/cnxk/cnxk_ethdev_mcs.c\n create mode 100644 drivers/net/cnxk/cnxk_ethdev_mcs.h", "diff": "diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c\nindex 5bc547051d..8dd2c8b7a5 100644\n--- a/drivers/net/cnxk/cn10k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c\n@@ -1090,9 +1090,15 @@ cn10k_eth_sec_ops_override(void)\n \tinit_once = 1;\n \n \t/* Update platform specific ops */\n+\tcnxk_eth_sec_ops.macsec_sa_create = NULL;\n+\tcnxk_eth_sec_ops.macsec_sc_create = NULL;\n+\tcnxk_eth_sec_ops.macsec_sa_destroy = NULL;\n+\tcnxk_eth_sec_ops.macsec_sc_destroy = NULL;\n \tcnxk_eth_sec_ops.session_create = cn10k_eth_sec_session_create;\n \tcnxk_eth_sec_ops.session_destroy = cn10k_eth_sec_session_destroy;\n \tcnxk_eth_sec_ops.capabilities_get = cn10k_eth_sec_capabilities_get;\n \tcnxk_eth_sec_ops.session_update = cn10k_eth_sec_session_update;\n \tcnxk_eth_sec_ops.session_stats_get = cn10k_eth_sec_session_stats_get;\n+\tcnxk_eth_sec_ops.macsec_sc_stats_get = NULL;\n+\tcnxk_eth_sec_ops.macsec_sa_stats_get = NULL;\n }\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 916198d802..5368f0777d 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1961,6 +1961,16 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tif (rc)\n \t\tgoto free_mac_addrs;\n \n+\tif (roc_feature_nix_has_macsec()) {\n+\t\trc = cnxk_mcs_dev_init(dev, 0);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to init MCS\");\n+\t\t\tgoto free_mac_addrs;\n+\t\t}\n+\t\tdev->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP;\n+\t\tdev->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MACSEC_INSERT;\n+\t}\n+\n \tplt_nix_dbg(\"Port=%d pf=%d vf=%d ver=%s hwcap=0x%\" PRIx64\n \t\t \" rxoffload_capa=0x%\" PRIx64 \" txoffload_capa=0x%\" PRIx64,\n \t\t eth_dev->data->port_id, roc_nix_get_pf(nix),\n@@ -2058,6 +2068,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n \t}\n \teth_dev->data->nb_rx_queues = 0;\n \n+\tif (roc_feature_nix_has_macsec())\n+\t\tcnxk_mcs_dev_fini(dev);\n+\n \t/* Free security resources */\n \tnix_security_release(dev);\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex e280d6c05e..d5bb06b823 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -395,6 +395,9 @@ struct cnxk_eth_dev {\n \t/* Reassembly dynfield/flag offsets */\n \tint reass_dynfield_off;\n \tint reass_dynflag_bit;\n+\n+\t/* MCS device */\n+\tstruct cnxk_mcs_dev *mcs_dev;\n };\n \n struct cnxk_eth_rxq_sp {\n@@ -623,6 +626,17 @@ int cnxk_nix_cman_config_set(struct rte_eth_dev *dev, const struct rte_eth_cman_\n \n int cnxk_nix_cman_config_get(struct rte_eth_dev *dev, struct rte_eth_cman_config *config);\n \n+int cnxk_mcs_dev_init(struct cnxk_eth_dev *dev, uint8_t mcs_idx);\n+void cnxk_mcs_dev_fini(struct cnxk_eth_dev *dev);\n+\n+struct cnxk_macsec_sess *cnxk_eth_macsec_sess_get_by_sess(struct cnxk_eth_dev *dev,\n+\t\t\t\t\t\t\t const struct rte_security_session *sess);\n+int cnxk_mcs_flow_configure(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,\n+\t\t\t const struct rte_flow_item pattern[],\n+\t\t\t const struct rte_flow_action actions[], struct rte_flow_error *error,\n+\t\t\t void **mcs_flow);\n+int cnxk_mcs_flow_destroy(struct cnxk_eth_dev *eth_dev, void *mcs_flow);\n+\n /* Other private functions */\n int nix_recalc_mtu(struct rte_eth_dev *eth_dev);\n int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id);\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.c b/drivers/net/cnxk/cnxk_ethdev_mcs.c\nnew file mode 100644\nindex 0000000000..b0205f45c5\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev_mcs.c\n@@ -0,0 +1,151 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#include <cnxk_ethdev.h>\n+#include <cnxk_ethdev_mcs.h>\n+#include <roc_mcs.h>\n+\n+static int\n+cnxk_mcs_event_cb(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg)\n+{\n+\tstruct rte_eth_event_macsec_desc d = {0};\n+\n+\td.metadata = (uint64_t)userdata;\n+\n+\tswitch (desc->type) {\n+\tcase ROC_MCS_EVENT_SECTAG_VAL_ERR:\n+\t\td.type = RTE_ETH_EVENT_MACSEC_SECTAG_VAL_ERR;\n+\t\tswitch (desc->subtype) {\n+\t\tcase ROC_MCS_EVENT_RX_SECTAG_V_EQ1:\n+\t\t\td.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_V_EQ1;\n+\t\t\tbreak;\n+\t\tcase ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1:\n+\t\t\td.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_E_EQ0_C_EQ1;\n+\t\t\tbreak;\n+\t\tcase ROC_MCS_EVENT_RX_SECTAG_SL_GTE48:\n+\t\t\td.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SL_GTE48;\n+\t\t\tbreak;\n+\t\tcase ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1:\n+\t\t\td.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_ES_EQ1_SC_EQ1;\n+\t\t\tbreak;\n+\t\tcase ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1:\n+\t\t\td.subtype = RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SC_EQ1_SCB_EQ1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tplt_err(\"Unknown MACsec sub event : %d\", desc->subtype);\n+\t\t}\n+\t\tbreak;\n+\tcase ROC_MCS_EVENT_RX_SA_PN_HARD_EXP:\n+\t\td.type = RTE_ETH_EVENT_MACSEC_RX_SA_PN_HARD_EXP;\n+\t\tbreak;\n+\tcase ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP:\n+\t\td.type = RTE_ETH_EVENT_MACSEC_RX_SA_PN_SOFT_EXP;\n+\t\tbreak;\n+\tcase ROC_MCS_EVENT_TX_SA_PN_HARD_EXP:\n+\t\td.type = RTE_ETH_EVENT_MACSEC_TX_SA_PN_HARD_EXP;\n+\t\tbreak;\n+\tcase ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP:\n+\t\td.type = RTE_ETH_EVENT_MACSEC_TX_SA_PN_SOFT_EXP;\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_err(\"Unknown MACsec event type: %d\", desc->type);\n+\t}\n+\n+\trte_eth_dev_callback_process(cb_arg, RTE_ETH_EVENT_MACSEC, &d);\n+\n+\treturn 0;\n+}\n+\n+void\n+cnxk_mcs_dev_fini(struct cnxk_eth_dev *dev)\n+{\n+\tstruct cnxk_mcs_dev *mcs_dev = dev->mcs_dev;\n+\tint rc;\n+\n+\trc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_SECTAG_VAL_ERR);\n+\tif (rc)\n+\t\tplt_err(\"Failed to unregister MCS event callback: rc: %d\", rc);\n+\n+\trc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP);\n+\tif (rc)\n+\t\tplt_err(\"Failed to unregister MCS event callback: rc: %d\", rc);\n+\n+\trc = roc_mcs_event_cb_unregister(mcs_dev->mdev, ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP);\n+\tif (rc)\n+\t\tplt_err(\"Failed to unregister MCS event callback: rc: %d\", rc);\n+\n+\t/* Cleanup MACsec dev */\n+\troc_mcs_dev_fini(mcs_dev->mdev);\n+\n+\tplt_free(mcs_dev);\n+}\n+\n+int\n+cnxk_mcs_dev_init(struct cnxk_eth_dev *dev, uint8_t mcs_idx)\n+{\n+\tstruct roc_mcs_intr_cfg intr_cfg = {0};\n+\tstruct roc_mcs_hw_info hw_info = {0};\n+\tstruct cnxk_mcs_dev *mcs_dev;\n+\tint rc;\n+\n+\trc = roc_mcs_hw_info_get(&hw_info);\n+\tif (rc) {\n+\t\tplt_err(\"MCS HW info get failed: rc: %d \", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tmcs_dev = plt_zmalloc(sizeof(struct cnxk_mcs_dev), PLT_CACHE_LINE_SIZE);\n+\tif (!mcs_dev)\n+\t\treturn -ENOMEM;\n+\n+\tmcs_dev->idx = mcs_idx;\n+\tmcs_dev->mdev = roc_mcs_dev_init(mcs_dev->idx);\n+\tif (!mcs_dev->mdev) {\n+\t\tplt_free(mcs_dev);\n+\t\treturn rc;\n+\t}\n+\tmcs_dev->port_id = dev->eth_dev->data->port_id;\n+\n+\tintr_cfg.intr_mask =\n+\t\tROC_MCS_CPM_RX_SECTAG_V_EQ1_INT | ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT |\n+\t\tROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT | ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT |\n+\t\tROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT | ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT |\n+\t\tROC_MCS_CPM_RX_PN_THRESH_REACHED_INT | ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT |\n+\t\tROC_MCS_CPM_TX_PN_THRESH_REACHED_INT | ROC_MCS_CPM_TX_SA_NOT_VALID_INT |\n+\t\tROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT | ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT |\n+\t\tROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT | ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT |\n+\t\tROC_MCS_PAB_RX_CHAN_OVERFLOW_INT | ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT;\n+\n+\trc = roc_mcs_intr_configure(mcs_dev->mdev, &intr_cfg);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to configure MCS interrupts: rc: %d\", rc);\n+\t\tplt_free(mcs_dev);\n+\t\treturn rc;\n+\t}\n+\n+\trc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_SECTAG_VAL_ERR,\n+\t\t\t\t cnxk_mcs_event_cb, dev->eth_dev, mcs_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register MCS event callback: rc: %d\", rc);\n+\t\tplt_free(mcs_dev);\n+\t\treturn rc;\n+\t}\n+\trc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP,\n+\t\t\t\t cnxk_mcs_event_cb, dev->eth_dev, mcs_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register MCS event callback: rc: %d\", rc);\n+\t\tplt_free(mcs_dev);\n+\t\treturn rc;\n+\t}\n+\trc = roc_mcs_event_cb_register(mcs_dev->mdev, ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP,\n+\t\t\t\t cnxk_mcs_event_cb, dev->eth_dev, mcs_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register MCS event callback: rc: %d\", rc);\n+\t\tplt_free(mcs_dev);\n+\t\treturn rc;\n+\t}\n+\tdev->mcs_dev = mcs_dev;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_mcs.h b/drivers/net/cnxk/cnxk_ethdev_mcs.h\nnew file mode 100644\nindex 0000000000..762c299fb8\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev_mcs.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#include <cnxk_ethdev.h>\n+\n+#define CNXK_MACSEC_HASH_KEY 16\n+\n+struct cnxk_mcs_dev {\n+\tuint64_t default_sci;\n+\tvoid *mdev;\n+\tuint8_t port_id;\n+\tuint8_t idx;\n+};\n+\n+struct cnxk_mcs_event_data {\n+\t/* Valid for below events\n+\t * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP\n+\t * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP\n+\t */\n+\tstruct {\n+\t\tuint8_t secy_idx;\n+\t\tuint8_t sc_idx;\n+\t\tuint8_t sa_idx;\n+\t};\n+\t/* Valid for below event\n+\t * - ROC_MCS_EVENT_FIFO_OVERFLOW\n+\t *\n+\t * Upon fatal error notification on a MCS port, driver resets below attributes of active\n+\t * flow entities(sc & sa) and then resets the port.\n+\t * - Reset NEXT_PN of active SAs to 1.\n+\t * - Reset TX active SA for each SC, TX_SA_ACTIVE = 0, SA_INDEX0_VLD = 1.\n+\t * - Clear SA_IN_USE for active ANs in RX_SA_MAP_MEM.\n+\t * - Clear all stats mapping to this port.\n+\t * - Reactivate SA_IN_USE for active ANs in RX_SA_MAP_MEM.\n+\t *\n+\t * UMD driver notifies the following flow entity(sc & sa) details in application callback,\n+\t * application is expected to exchange the Tx/Rx NEXT_PN, TX_SA_ACTIVE, active RX SC AN\n+\t * details with peer device so that peer device can resets it's MACsec flow states and than\n+\t * resume packet transfers.\n+\t */\n+\tstruct {\n+\t\tuint16_t *tx_sa_array; /* Tx SAs whose PN memories were reset (NEXT_PN=1) */\n+\t\tuint16_t *rx_sa_array; /* Rx SAs whose PN memories were reset (NEXT_PN=1) */\n+\t\tuint16_t *tx_sc_array; /* Tx SCs whose active SAs were reset (TX_SA_ACTIVE=0) */\n+\t\tuint16_t *rx_sc_array; /* Rx SCs whose state was reset */\n+\t\tuint8_t *sc_an_array; /* AN of Rx SCs(in rx_sc_array) which were reactivated */\n+\t\tuint8_t num_tx_sa; /* num entries in tx_sa_array */\n+\t\tuint8_t num_rx_sa; /* num entries in rx_sa_array */\n+\t\tuint8_t num_tx_sc; /* num entries in tx_sc_array */\n+\t\tuint8_t num_rx_sc; /* num entries in rx_sc_array */\n+\t\tuint8_t lmac_id; /* lmac_id/port which was recovered from fatal error */\n+\t};\n+};\n+\n+struct cnxk_mcs_event_desc {\n+\tstruct rte_eth_dev *eth_dev;\n+\tenum roc_mcs_event_type type;\n+\tenum roc_mcs_event_subtype subtype;\n+\tstruct cnxk_mcs_event_data metadata;\n+};\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 62b8bb90fb..ae6a7d9aac 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -22,6 +22,7 @@ sources = files(\n 'cnxk_ethdev.c',\n 'cnxk_ethdev_cman.c',\n 'cnxk_ethdev_devargs.c',\n+ 'cnxk_ethdev_mcs.c',\n 'cnxk_ethdev_mtr.c',\n 'cnxk_ethdev_ops.c',\n 'cnxk_ethdev_sec.c',\n", "prefixes": [ "v3", "12/15" ] }