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GET /api/patches/128543/?format=api
{ "id": 128543, "url": "http://patches.dpdk.org/api/patches/128543/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-10-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-10-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-10-gakhil@marvell.com", "date": "2023-06-13T07:16:08", "name": "[v3,09/15] common/cnxk: add MACsec control port configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "f060b72c0dec0506fc4c08d9732c7421545c6529", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-10-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128543/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/128543/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 460F842CA0;\n\tTue, 13 Jun 2023 09:17:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D3FBD42D53;\n\tTue, 13 Jun 2023 09:17:02 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 784F742D48\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:17:01 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D563w1013030; Tue, 13 Jun 2023 00:17:00 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3r4rpkf755-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:17:00 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:58 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id 181CC5E6861;\n Tue, 13 Jun 2023 00:16:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=HhsgVAXBfcuJpwJ/g3lg2qCBjzhYnRz7KK26Ba6H62g=;\n b=cwZPFHXL/nWt93REJus3f34lzp5TtNe7NpWQRxyjFbFXiQb8umCoUsCCNuM/einA430c\n QiQUcvIWaRBUd9+zkRxuvjjZpB2Q2VDX7VAgsfuXILh3EvM/m7l8Qj0b8VuQI1ZQo2W9\n 7hIaDQrok0FxbBYPJWYaPIm4vZlY1C9Xg7P4ad1uJ+H0k/d+qMQE/ZpzFTWgKhdeKihM\n nCX0PoVB6djm9oILAxLkjlJ0gn1WU3bHcb0C9PEIdee6zaeqwO0SaHtYv5l8n5bSh+Ca\n 1rgx0Qrgeuw9IrpZ4mZcUtJ4UqflypFhTycP7RkI9LAE8z0fr4JEFEEON70bglHETyKF EQ==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 09/15] common/cnxk: add MACsec control port configuration", "Date": "Tue, 13 Jun 2023 12:46:08 +0530", "Message-ID": "<20230613071614.2259604-10-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "CuwidzSbrHzKPjb5CPYrFg3gJ9fnGvbB", "X-Proofpoint-GUID": "CuwidzSbrHzKPjb5CPYrFg3gJ9fnGvbB", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs to configure MACsec control port.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 72 ++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.c | 117 ++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 65 ++++++++++++++++++\n drivers/common/cnxk/version.map | 4 ++\n 4 files changed, 258 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex d7c0385a8b..446f49aeaf 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -319,9 +319,17 @@ struct mbox_msghdr {\n \tM(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \\\n \tM(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \\\n \tM(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \\\n+\tM(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, mcs_alloc_ctrl_pkt_rule_req, \\\n+\t mcs_alloc_ctrl_pkt_rule_rsp) \\\n+\tM(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, mcs_free_ctrl_pkt_rule_req, \\\n+\t msg_rsp) \\\n+\tM(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, mcs_ctrl_pkt_rule_write_req, \\\n+\t msg_rsp) \\\n \tM(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \\\n \tM(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp) \\\n \tM(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, mcs_port_cfg_get_rsp) \\\n+\tM(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, mcs_custom_tag_cfg_get_req, \\\n+\t mcs_custom_tag_cfg_get_rsp) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -922,6 +930,53 @@ struct mcs_set_pn_threshold {\n \tuint64_t __io rsvd;\n };\n \n+enum mcs_ctrl_pkt_rule_type {\n+\tMCS_CTRL_PKT_RULE_TYPE_ETH,\n+\tMCS_CTRL_PKT_RULE_TYPE_DA,\n+\tMCS_CTRL_PKT_RULE_TYPE_RANGE,\n+\tMCS_CTRL_PKT_RULE_TYPE_COMBO,\n+\tMCS_CTRL_PKT_RULE_TYPE_MAC,\n+};\n+\n+struct mcs_alloc_ctrl_pkt_rule_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rule_type;\n+\tuint8_t __io mcs_id; /* MCS block ID */\n+\tuint8_t __io dir; /* Macsec ingress or egress side */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_alloc_ctrl_pkt_rule_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rule_idx;\n+\tuint8_t __io rule_type;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_free_ctrl_pkt_rule_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rule_idx;\n+\tuint8_t __io rule_type;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all; /* Free all the rule resources */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_ctrl_pkt_rule_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io data0;\n+\tuint64_t __io data1;\n+\tuint64_t __io data2;\n+\tuint8_t __io rule_idx;\n+\tuint8_t __io rule_type;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_port_cfg_set_req {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io cstm_tag_rel_mode_sel;\n@@ -951,6 +1006,23 @@ struct mcs_port_cfg_get_rsp {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_custom_tag_cfg_get_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_custom_tag_cfg_get_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io cstm_etype[8];\n+\tuint8_t __io cstm_indx[8];\n+\tuint8_t __io cstm_etype_en;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_port_reset_req {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io reset;\ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nindex e6e6197a49..1e3235ad73 100644\n--- a/drivers/common/cnxk/roc_mcs.c\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -140,6 +140,88 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p\n \treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n }\n \n+int\n+roc_mcs_ctrl_pkt_rule_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_ctrl_pkt_rule_req *req,\n+\t\t\t struct roc_mcs_alloc_ctrl_pkt_rule_rsp *rsp)\n+{\n+\tstruct mcs_alloc_ctrl_pkt_rule_req *rule_req;\n+\tstruct mcs_alloc_ctrl_pkt_rule_rsp *rule_rsp;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL || rsp == NULL)\n+\t\treturn -EINVAL;\n+\n+\trule_req = mbox_alloc_msg_mcs_alloc_ctrl_pkt_rule(mcs->mbox);\n+\tif (rule_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trule_req->rule_type = req->rule_type;\n+\trule_req->mcs_id = mcs->idx;\n+\trule_req->dir = req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rule_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trsp->rule_type = rule_rsp->rule_type;\n+\trsp->rule_idx = rule_rsp->rule_idx;\n+\trsp->dir = rule_rsp->dir;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_ctrl_pkt_rule_free(struct roc_mcs *mcs, struct roc_mcs_free_ctrl_pkt_rule_req *req)\n+{\n+\tstruct mcs_free_ctrl_pkt_rule_req *rule_req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\n+\trule_req = mbox_alloc_msg_mcs_free_ctrl_pkt_rule(mcs->mbox);\n+\tif (rule_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trule_req->rule_type = req->rule_type;\n+\trule_req->rule_idx = req->rule_idx;\n+\trule_req->mcs_id = mcs->idx;\n+\trule_req->dir = req->dir;\n+\trule_req->all = req->all;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_ctrl_pkt_rule_write(struct roc_mcs *mcs, struct roc_mcs_ctrl_pkt_rule_write_req *req)\n+{\n+\tstruct mcs_ctrl_pkt_rule_write_req *rule_req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\n+\trule_req = mbox_alloc_msg_mcs_ctrl_pkt_rule_write(mcs->mbox);\n+\tif (rule_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trule_req->rule_type = req->rule_type;\n+\trule_req->rule_idx = req->rule_idx;\n+\trule_req->mcs_id = mcs->idx;\n+\trule_req->dir = req->dir;\n+\trule_req->data0 = req->data0;\n+\trule_req->data1 = req->data1;\n+\trule_req->data2 = req->data2;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n int\n roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req)\n {\n@@ -198,6 +280,41 @@ roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req,\n \treturn 0;\n }\n \n+int\n+roc_mcs_custom_tag_cfg_get(struct roc_mcs *mcs, struct roc_mcs_custom_tag_cfg_get_req *req,\n+\t\t\t struct roc_mcs_custom_tag_cfg_get_rsp *rsp)\n+{\n+\tstruct mcs_custom_tag_cfg_get_req *get_req;\n+\tstruct mcs_custom_tag_cfg_get_rsp *get_rsp;\n+\tint i, rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\n+\tget_req = mbox_alloc_msg_mcs_custom_tag_cfg_get(mcs->mbox);\n+\tif (get_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tget_req->dir = req->dir;\n+\tget_req->mcs_id = mcs->idx;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&get_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < 8; i++) {\n+\t\trsp->cstm_etype[i] = get_rsp->cstm_etype[i];\n+\t\trsp->cstm_indx[i] = get_rsp->cstm_indx[i];\n+\t}\n+\n+\trsp->cstm_etype_en = get_rsp->cstm_etype_en;\n+\trsp->dir = get_rsp->dir;\n+\n+\treturn 0;\n+}\n+\n int\n roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)\n {\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex d06057726f..e8d6b070db 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -163,6 +163,45 @@ struct roc_mcs_set_pn_threshold {\n \tuint64_t rsvd;\n };\n \n+enum roc_mcs_ctrl_pkt_rule_type {\n+\tROC_MCS_CTRL_PKT_RULE_TYPE_ETH,\n+\tROC_MCS_CTRL_PKT_RULE_TYPE_DA,\n+\tROC_MCS_CTRL_PKT_RULE_TYPE_RANGE,\n+\tROC_MCS_CTRL_PKT_RULE_TYPE_COMBO,\n+\tROC_MCS_CTRL_PKT_RULE_TYPE_MAC,\n+};\n+\n+struct roc_mcs_alloc_ctrl_pkt_rule_req {\n+\tuint8_t rule_type;\n+\tuint8_t dir; /* Macsec ingress or egress side */\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_alloc_ctrl_pkt_rule_rsp {\n+\tuint8_t rule_idx;\n+\tuint8_t rule_type;\n+\tuint8_t dir;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_free_ctrl_pkt_rule_req {\n+\tuint8_t rule_idx;\n+\tuint8_t rule_type;\n+\tuint8_t dir;\n+\tuint8_t all; /* Free all the rule resources */\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_ctrl_pkt_rule_write_req {\n+\tuint64_t data0;\n+\tuint64_t data1;\n+\tuint64_t data2;\n+\tuint8_t rule_idx;\n+\tuint8_t rule_type;\n+\tuint8_t dir;\n+\tuint64_t rsvd;\n+};\n+\n struct roc_mcs_port_cfg_set_req {\n \t/* Index of custom tag (= cstm_indx[x] in roc_mcs_custom_tag_cfg_get_rsp struct) to use\n \t * when TX SECY_PLCY_MEMX[SECTAG_INSERT_MODE] = 0 (relative offset mode)\n@@ -195,6 +234,19 @@ struct roc_mcs_port_cfg_get_rsp {\n \tuint64_t rsvd;\n };\n \n+struct roc_mcs_custom_tag_cfg_get_req {\n+\tuint8_t dir;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_custom_tag_cfg_get_rsp {\n+\tuint16_t cstm_etype[8]; /* EthType/TPID */\n+\tuint8_t cstm_indx[8];\t/* Custom tag index used to identify the VLAN etype */\n+\tuint8_t cstm_etype_en;\t/* bitmap of enabled custom tags */\n+\tuint8_t dir;\n+\tuint64_t rsvd;\n+};\n+\n struct roc_mcs_port_reset_req {\n \tuint8_t port_id;\n \tuint64_t rsvd;\n@@ -411,6 +463,10 @@ __roc_api int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_\n /* Set port config */\n __roc_api int roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req,\n \t\t\t\t struct roc_mcs_port_cfg_get_rsp *rsp);\n+/* Get custom tag config */\n+__roc_api int roc_mcs_custom_tag_cfg_get(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_custom_tag_cfg_get_req *req,\n+\t\t\t\t\t struct roc_mcs_custom_tag_cfg_get_rsp *rsp);\n \n /* Resource allocation and free */\n __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n@@ -456,6 +512,15 @@ __roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs,\n __roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs,\n \t\t\t\t\t struct roc_mcs_flowid_ena_dis_entry *entry);\n \n+/* Control packet rule alloc, free and write */\n+__roc_api int roc_mcs_ctrl_pkt_rule_alloc(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_alloc_ctrl_pkt_rule_req *req,\n+\t\t\t\t\t struct roc_mcs_alloc_ctrl_pkt_rule_rsp *rsp);\n+__roc_api int roc_mcs_ctrl_pkt_rule_free(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_free_ctrl_pkt_rule_req *req);\n+__roc_api int roc_mcs_ctrl_pkt_rule_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_ctrl_pkt_rule_write_req *req);\n+\n /* Flow id stats get */\n __roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n \t\t\t\t struct roc_mcs_flowid_stats *stats);\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 6c0defa27e..914d0d2caa 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -136,6 +136,10 @@ INTERNAL {\n \troc_se_ciph_key_set;\n \troc_se_ctx_init;\n \troc_mcs_active_lmac_set;\n+\troc_mcs_ctrl_pkt_rule_alloc;\n+\troc_mcs_ctrl_pkt_rule_free;\n+\troc_mcs_ctrl_pkt_rule_write;\n+\troc_mcs_custom_tag_cfg_get;\n \troc_mcs_dev_init;\n \troc_mcs_dev_fini;\n \troc_mcs_dev_get;\n", "prefixes": [ "v3", "09/15" ] }