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GET /api/patches/128542/?format=api
{ "id": 128542, "url": "http://patches.dpdk.org/api/patches/128542/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-9-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-9-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-9-gakhil@marvell.com", "date": "2023-06-13T07:16:07", "name": "[v3,08/15] common/cnxk: add MACsec port configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b60762c19eb9fdad6bd475458cc4bac78bf4c8ca", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-9-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128542/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/128542/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6BA1A42CA0;\n\tTue, 13 Jun 2023 09:17:39 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D3D4A42D43;\n\tTue, 13 Jun 2023 09:16:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 419BE42D4E\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:16:58 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D567pt005545; Tue, 13 Jun 2023 00:16:57 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235gg-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:16:57 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:55 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id 267FC5E6865;\n Tue, 13 Jun 2023 00:16:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Et2Tu3rvClukitvBpXHWYjVlg0NGi8KxTYjU6eKOXB0=;\n b=kPn8qXC08IamPCCvVjll6nWJl1cz2fleUUX4zao6oBHleTlGnJMiwxF+6Xa3Yr97faSd\n lCEMhfulyBcJr3tX4e2ce9PPgte/DPHinTiJF5ZSaUtZ0Q2CBjlq62Fg+ViaU3Ltmci0\n kPgMJVBKfxpTnRWJcWHg6Y27DAKgoVFLMoAGseXk3+85seyhB/3z7crPnw53GfE43nhf\n 0vAA3dX+tTHB6xvJi4WG6cMq9N82ghUdrhyqB0OKaLzduo2ancA8qmyxrCsiQNVsPAWa\n dTj2MewXVr5snyenx0+o/co3ygsp7L5OxSfcEFV5ZSYn04Ag7zaJ8HbT4e1TEc1IY8rw xg==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 08/15] common/cnxk: add MACsec port configuration", "Date": "Tue, 13 Jun 2023 12:46:07 +0530", "Message-ID": "<20230613071614.2259604-9-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "w9VWKwGBY1681RVAZAG_zaBksWNYmbXO", "X-Proofpoint-GUID": "w9VWKwGBY1681RVAZAG_zaBksWNYmbXO", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs for MACsec port configurations\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 40 ++++\n drivers/common/cnxk/roc_mcs.c | 346 ++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 48 +++++\n drivers/common/cnxk/version.map | 4 +\n 4 files changed, 438 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex d964ba9f9d..d7c0385a8b 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -319,6 +319,9 @@ struct mbox_msghdr {\n \tM(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \\\n \tM(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \\\n \tM(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \\\n+\tM(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \\\n+\tM(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp) \\\n+\tM(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, mcs_port_cfg_get_rsp) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -919,6 +922,43 @@ struct mcs_set_pn_threshold {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_port_cfg_set_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io cstm_tag_rel_mode_sel;\n+\tuint8_t __io custom_hdr_enb;\n+\tuint8_t __io fifo_skid;\n+\tuint8_t __io lmac_mode;\n+\tuint8_t __io lmac_id;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_port_cfg_get_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io lmac_id;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_port_cfg_get_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io cstm_tag_rel_mode_sel;\n+\tuint8_t __io custom_hdr_enb;\n+\tuint8_t __io fifo_skid;\n+\tuint8_t __io lmac_mode;\n+\tuint8_t __io lmac_id;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_port_reset_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io reset;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io lmac_id;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_stats_req {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io id;\ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nindex e9090da575..e6e6197a49 100644\n--- a/drivers/common/cnxk/roc_mcs.c\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -76,6 +76,25 @@ roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lma\n \treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n }\n \n+static int\n+mcs_port_reset_set(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port, uint8_t reset)\n+{\n+\tstruct mcs_port_reset_req *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_port_reset(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->reset = reset;\n+\treq->lmac_id = port->port_id;\n+\treq->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n int\n roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port)\n {\n@@ -121,6 +140,64 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p\n \treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n }\n \n+int\n+roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req)\n+{\n+\tstruct mcs_port_cfg_set_req *set_req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\n+\tset_req = mbox_alloc_msg_mcs_port_cfg_set(mcs->mbox);\n+\tif (set_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tset_req->cstm_tag_rel_mode_sel = req->cstm_tag_rel_mode_sel;\n+\tset_req->custom_hdr_enb = req->custom_hdr_enb;\n+\tset_req->fifo_skid = req->fifo_skid;\n+\tset_req->lmac_mode = req->port_mode;\n+\tset_req->lmac_id = req->port_id;\n+\tset_req->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req,\n+\t\t struct roc_mcs_port_cfg_get_rsp *rsp)\n+{\n+\tstruct mcs_port_cfg_get_req *get_req;\n+\tstruct mcs_port_cfg_get_rsp *get_rsp;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\n+\tget_req = mbox_alloc_msg_mcs_port_cfg_get(mcs->mbox);\n+\tif (get_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tget_req->lmac_id = req->port_id;\n+\tget_req->mcs_id = mcs->idx;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&get_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trsp->cstm_tag_rel_mode_sel = get_rsp->cstm_tag_rel_mode_sel;\n+\trsp->custom_hdr_enb = get_rsp->custom_hdr_enb;\n+\trsp->fifo_skid = get_rsp->fifo_skid;\n+\trsp->port_mode = get_rsp->lmac_mode;\n+\trsp->port_id = get_rsp->lmac_id;\n+\n+\treturn 0;\n+}\n+\n int\n roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)\n {\n@@ -142,6 +219,275 @@ roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)\n \treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n }\n \n+int\n+roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata, uint8_t port_id)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct roc_mcs_pn_table_write_req pn_table = {0};\n+\tstruct roc_mcs_rx_sc_sa_map rx_map = {0};\n+\tstruct roc_mcs_tx_sc_sa_map tx_map = {0};\n+\tstruct roc_mcs_port_reset_req port = {0};\n+\tstruct roc_mcs_clear_stats stats = {0};\n+\tint tx_cnt = 0, rx_cnt = 0, rc = 0;\n+\tuint64_t set;\n+\tint i;\n+\n+\tport.port_id = port_id;\n+\trc = mcs_port_reset_set(mcs, &port, 1);\n+\n+\t/* Reset TX/RX PN tables */\n+\tfor (i = 0; i < (priv->sa_entries << 1); i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i);\n+\t\tif (set) {\n+\t\t\tpn_table.pn_id = i;\n+\t\t\tpn_table.next_pn = 1;\n+\t\t\tpn_table.dir = MCS_RX;\n+\t\t\tif (i >= priv->sa_entries) {\n+\t\t\t\tpn_table.dir = MCS_TX;\n+\t\t\t\tpn_table.pn_id -= priv->sa_entries;\n+\t\t\t}\n+\t\t\trc = roc_mcs_pn_table_write(mcs, &pn_table);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\tif (i >= priv->sa_entries)\n+\t\t\t\ttx_cnt++;\n+\t\t\telse\n+\t\t\t\trx_cnt++;\n+\t\t}\n+\t}\n+\n+\tif (tx_cnt || rx_cnt) {\n+\t\tmdata->tx_sa_array = plt_zmalloc(tx_cnt * sizeof(uint16_t), 0);\n+\t\tif (tx_cnt && (mdata->tx_sa_array == NULL)) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tmdata->rx_sa_array = plt_zmalloc(rx_cnt * sizeof(uint16_t), 0);\n+\t\tif (rx_cnt && (mdata->rx_sa_array == NULL)) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tmdata->num_tx_sa = tx_cnt;\n+\t\tmdata->num_rx_sa = rx_cnt;\n+\t\tfor (i = 0; i < (priv->sa_entries << 1); i++) {\n+\t\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i);\n+\t\t\tif (set) {\n+\t\t\t\tif (i >= priv->sa_entries)\n+\t\t\t\t\tmdata->tx_sa_array[--tx_cnt] = i - priv->sa_entries;\n+\t\t\t\telse\n+\t\t\t\t\tmdata->rx_sa_array[--rx_cnt] = i;\n+\t\t\t}\n+\t\t}\n+\t}\n+\ttx_cnt = 0;\n+\trx_cnt = 0;\n+\n+\t/* Reset Tx active SA to index:0 */\n+\tfor (i = priv->sc_entries; i < (priv->sc_entries << 1); i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i);\n+\t\tif (set) {\n+\t\t\tuint16_t sc_id = i - priv->sc_entries;\n+\n+\t\t\ttx_map.sa_index0 = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sa_idx0;\n+\t\t\ttx_map.sa_index1 = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sa_idx1;\n+\t\t\ttx_map.rekey_ena = priv->port_rsrc[port_id].sc_conf[sc_id].tx.rekey_enb;\n+\t\t\ttx_map.sectag_sci = priv->port_rsrc[port_id].sc_conf[sc_id].tx.sci;\n+\t\t\ttx_map.sa_index0_vld = 1;\n+\t\t\ttx_map.sa_index1_vld = 0;\n+\t\t\ttx_map.tx_sa_active = 0;\n+\t\t\ttx_map.sc_id = sc_id;\n+\t\t\trc = roc_mcs_tx_sc_sa_map_write(mcs, &tx_map);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\ttx_cnt++;\n+\t\t}\n+\t}\n+\n+\tif (tx_cnt) {\n+\t\tmdata->tx_sc_array = plt_zmalloc(tx_cnt * sizeof(uint16_t), 0);\n+\t\tif (tx_cnt && (mdata->tx_sc_array == NULL)) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tmdata->num_tx_sc = tx_cnt;\n+\t\tfor (i = priv->sc_entries; i < (priv->sc_entries << 1); i++) {\n+\t\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i);\n+\t\t\tif (set)\n+\t\t\t\tmdata->tx_sc_array[--tx_cnt] = i - priv->sc_entries;\n+\t\t}\n+\t}\n+\n+\t/* Clear SA_IN_USE for active ANs in RX CPM */\n+\tfor (i = 0; i < priv->sc_entries; i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i);\n+\t\tif (set) {\n+\t\t\trx_map.sa_index = priv->port_rsrc[port_id].sc_conf[i].rx.sa_idx;\n+\t\t\trx_map.an = priv->port_rsrc[port_id].sc_conf[i].rx.an;\n+\t\t\trx_map.sa_in_use = 0;\n+\t\t\trx_map.sc_id = i;\n+\t\t\trc = roc_mcs_rx_sc_sa_map_write(mcs, &rx_map);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\trx_cnt++;\n+\t\t}\n+\t}\n+\n+\t/* Reset flow(flow/secy/sc/sa) stats mapped to this PORT */\n+\tfor (i = 0; i < (priv->tcam_entries << 1); i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].tcam_bmap, i);\n+\t\tif (set) {\n+\t\t\tstats.type = MCS_FLOWID_STATS;\n+\t\t\tstats.id = i;\n+\t\t\tstats.dir = MCS_RX;\n+\t\t\tif (i >= priv->sa_entries) {\n+\t\t\t\tstats.dir = MCS_TX;\n+\t\t\t\tstats.id -= priv->tcam_entries;\n+\t\t\t}\n+\t\t\trc = roc_mcs_stats_clear(mcs, &stats);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t}\n+\tfor (i = 0; i < (priv->secy_entries << 1); i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].secy_bmap, i);\n+\t\tif (set) {\n+\t\t\tstats.type = MCS_SECY_STATS;\n+\t\t\tstats.id = i;\n+\t\t\tstats.dir = MCS_RX;\n+\t\t\tif (i >= priv->sa_entries) {\n+\t\t\t\tstats.dir = MCS_TX;\n+\t\t\t\tstats.id -= priv->secy_entries;\n+\t\t\t}\n+\t\t\trc = roc_mcs_stats_clear(mcs, &stats);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t}\n+\tfor (i = 0; i < (priv->sc_entries << 1); i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i);\n+\t\tif (set) {\n+\t\t\tstats.type = MCS_SC_STATS;\n+\t\t\tstats.id = i;\n+\t\t\tstats.dir = MCS_RX;\n+\t\t\tif (i >= priv->sa_entries) {\n+\t\t\t\tstats.dir = MCS_TX;\n+\t\t\t\tstats.id -= priv->sc_entries;\n+\t\t\t}\n+\t\t\trc = roc_mcs_stats_clear(mcs, &stats);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t}\n+\tif (roc_model_is_cn10kb_a0()) {\n+\t\tfor (i = 0; i < (priv->sa_entries << 1); i++) {\n+\t\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sa_bmap, i);\n+\t\t\tif (set) {\n+\t\t\t\tstats.type = MCS_SA_STATS;\n+\t\t\t\tstats.id = i;\n+\t\t\t\tstats.dir = MCS_RX;\n+\t\t\t\tif (i >= priv->sa_entries) {\n+\t\t\t\t\tstats.dir = MCS_TX;\n+\t\t\t\t\tstats.id -= priv->sa_entries;\n+\t\t\t\t}\n+\t\t\t\trc = roc_mcs_stats_clear(mcs, &stats);\n+\t\t\t\tif (rc)\n+\t\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\t}\n+\t{\n+\t\tstats.type = MCS_PORT_STATS;\n+\t\tstats.id = port_id;\n+\t\trc = roc_mcs_stats_clear(mcs, &stats);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\tif (rx_cnt) {\n+\t\tmdata->rx_sc_array = plt_zmalloc(rx_cnt * sizeof(uint16_t), 0);\n+\t\tif (mdata->rx_sc_array == NULL) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tmdata->sc_an_array = plt_zmalloc(rx_cnt * sizeof(uint8_t), 0);\n+\t\tif (mdata->sc_an_array == NULL) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tmdata->num_rx_sc = rx_cnt;\n+\t}\n+\n+\t/* Reactivate in-use ANs for active SCs in RX CPM */\n+\tfor (i = 0; i < priv->sc_entries; i++) {\n+\t\tset = plt_bitmap_get(priv->port_rsrc[port_id].sc_bmap, i);\n+\t\tif (set) {\n+\t\t\trx_map.sa_index = priv->port_rsrc[port_id].sc_conf[i].rx.sa_idx;\n+\t\t\trx_map.an = priv->port_rsrc[port_id].sc_conf[i].rx.an;\n+\t\t\trx_map.sa_in_use = 1;\n+\t\t\trx_map.sc_id = i;\n+\t\t\trc = roc_mcs_rx_sc_sa_map_write(mcs, &rx_map);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\tmdata->rx_sc_array[--rx_cnt] = i;\n+\t\t\tmdata->sc_an_array[rx_cnt] = priv->port_rsrc[port_id].sc_conf[i].rx.an;\n+\t\t}\n+\t}\n+\n+\tport.port_id = port_id;\n+\trc = mcs_port_reset_set(mcs, &port, 0);\n+\n+\treturn rc;\n+exit:\n+\tif (mdata->num_tx_sa)\n+\t\tplt_free(mdata->tx_sa_array);\n+\tif (mdata->num_rx_sa)\n+\t\tplt_free(mdata->rx_sa_array);\n+\tif (mdata->num_tx_sc)\n+\t\tplt_free(mdata->tx_sc_array);\n+\tif (mdata->num_rx_sc) {\n+\t\tplt_free(mdata->rx_sc_array);\n+\t\tplt_free(mdata->sc_an_array);\n+\t}\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_port_reset(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port)\n+{\n+\tstruct roc_mcs_event_desc desc = {0};\n+\tint rc;\n+\n+\t/* Initiate port reset and software recovery */\n+\trc = roc_mcs_port_recovery(mcs, &desc.metadata, port->port_id);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tdesc.type = ROC_MCS_EVENT_PORT_RESET_RECOVERY;\n+\t/* Notify the entity details to the application which are recovered */\n+\tmcs_event_cb_process(mcs, &desc);\n+\n+exit:\n+\tif (desc.metadata.num_tx_sa)\n+\t\tplt_free(desc.metadata.tx_sa_array);\n+\tif (desc.metadata.num_rx_sa)\n+\t\tplt_free(desc.metadata.rx_sa_array);\n+\tif (desc.metadata.num_tx_sc)\n+\t\tplt_free(desc.metadata.tx_sc_array);\n+\tif (desc.metadata.num_rx_sc) {\n+\t\tplt_free(desc.metadata.rx_sc_array);\n+\t\tplt_free(desc.metadata.sc_an_array);\n+\t}\n+\n+\treturn rc;\n+}\n+\n int\n roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,\n \t\t\t roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata)\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex b2ca6ee51b..d06057726f 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -163,6 +163,43 @@ struct roc_mcs_set_pn_threshold {\n \tuint64_t rsvd;\n };\n \n+struct roc_mcs_port_cfg_set_req {\n+\t/* Index of custom tag (= cstm_indx[x] in roc_mcs_custom_tag_cfg_get_rsp struct) to use\n+\t * when TX SECY_PLCY_MEMX[SECTAG_INSERT_MODE] = 0 (relative offset mode)\n+\t */\n+\tuint8_t cstm_tag_rel_mode_sel;\n+\t/* In ingress path, custom_hdr_enb = 1 when the port is expected to receive pkts\n+\t * that have 8B custom header before DMAC\n+\t */\n+\tuint8_t custom_hdr_enb;\n+\t/* Valid fifo skid values are 14,28,56 for 25G,50G,100G respectively\n+\t * FIFOs need to be configured based on the port_mode, valid only for 105N\n+\t */\n+\tuint8_t fifo_skid;\n+\tuint8_t port_mode; /* 2'b00 - 25G or less, 2'b01 - 50G, 2'b10 - 100G */\n+\tuint8_t port_id;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_port_cfg_get_req {\n+\tuint8_t port_id;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_port_cfg_get_rsp {\n+\tuint8_t cstm_tag_rel_mode_sel;\n+\tuint8_t custom_hdr_enb;\n+\tuint8_t fifo_skid;\n+\tuint8_t port_mode;\n+\tuint8_t port_id;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_port_reset_req {\n+\tuint8_t port_id;\n+\tuint64_t rsvd;\n+};\n+\n struct roc_mcs_stats_req {\n \tuint8_t id;\n \tuint8_t dir;\n@@ -367,6 +404,13 @@ __roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_ac\n __roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port);\n /* (X)PN threshold set */\n __roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn);\n+/* Reset port */\n+__roc_api int roc_mcs_port_reset(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port);\n+/* Get port config */\n+__roc_api int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req);\n+/* Set port config */\n+__roc_api int roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req,\n+\t\t\t\t struct roc_mcs_port_cfg_get_rsp *rsp);\n \n /* Resource allocation and free */\n __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n@@ -436,4 +480,8 @@ __roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_even\n /* Configure interrupts */\n __roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config);\n \n+/* Port recovery from fatal errors */\n+__roc_api int roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata,\n+\t\t\t\t uint8_t port_id);\n+\n #endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex d10dfcd84e..6c0defa27e 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -151,6 +151,10 @@ INTERNAL {\n \troc_mcs_pn_table_write;\n \troc_mcs_pn_table_read;\n \troc_mcs_pn_threshold_set;\n+\troc_mcs_port_cfg_get;\n+\troc_mcs_port_cfg_set;\n+\troc_mcs_port_recovery;\n+\troc_mcs_port_reset;\n \troc_mcs_port_stats_get;\n \troc_mcs_rsrc_alloc;\n \troc_mcs_rsrc_free;\n", "prefixes": [ "v3", "08/15" ] }