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GET /api/patches/128541/?format=api
{ "id": 128541, "url": "http://patches.dpdk.org/api/patches/128541/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-8-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-8-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-8-gakhil@marvell.com", "date": "2023-06-13T07:16:06", "name": "[v3,07/15] common/cnxk: add MACsec interrupt APIs", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b8f1c561f9db3fe8ebc8bbd7a9f44b256d9ce375", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-8-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128541/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/128541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EFD0242CA0;\n\tTue, 13 Jun 2023 09:17:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8EFB542D2C;\n\tTue, 13 Jun 2023 09:16:56 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 57A2442C54\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:16:55 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D567ps005545; Tue, 13 Jun 2023 00:16:54 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235gd-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:16:54 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:52 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id 313885C68E3;\n Tue, 13 Jun 2023 00:16:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=aErj/XDmUu3jTcRLrVur8/nXAEqrLijOCUjQ7MDdDe8=;\n b=PPokREFFm1jJrbJ9/Azy9f0VCYQwIJnwJtdfUnlAT+d9i+pflb/yaxjL8E6qir90gaHb\n MSkzoeks8TuwXrSHnNm5jHUccsZa/oZu/oii/mYDP7HRB5FQ+CqKqbuHSvRnBhExhuxR\n RNx8Gxkp9C8LvUSRVymK25ZLHmbiNfVc8DVlp6ypR60+cfXu7NWZAoWnrKYcuiAysopI\n Ngeg7WWcxmQ0XT/6916e5Fe1oh4R+puUuoCSi1w48D6NMjxHFz4NNWX5eSy3+B9TRwRz\n wxHOxKh2JM2v2p3SabZQeI/wmnR2Cr6phmGYUL9l9u92TymnbOq80wK4/5yLNxu8IHRX Sg==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 07/15] common/cnxk: add MACsec interrupt APIs", "Date": "Tue, 13 Jun 2023 12:46:06 +0530", "Message-ID": "<20230613071614.2259604-8-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "DnlWzprCHA1JmANxl-UQOLuPZX3hhDR4", "X-Proofpoint-GUID": "DnlWzprCHA1JmANxl-UQOLuPZX3hhDR4", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs to support various MACsec interrupts.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_dev.c | 86 +++++++++++++++++\n drivers/common/cnxk/roc_mbox.h | 37 +++++++-\n drivers/common/cnxk/roc_mcs.c | 117 +++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 144 +++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs_priv.h | 8 ++\n drivers/common/cnxk/version.map | 3 +\n 6 files changed, 394 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 571679c968..4b0ba218ed 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -527,6 +527,91 @@ pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg)\n \t}\n }\n \n+static int\n+mbox_up_handler_mcs_intr_notify(struct dev *dev, struct mcs_intr_info *info, struct msg_rsp *rsp)\n+{\n+\tstruct roc_mcs_event_desc desc = {0};\n+\tstruct roc_mcs *mcs;\n+\n+\tplt_base_dbg(\"pf:%d/vf:%d msg id 0x%x (%s) from: pf:%d/vf:%d\", dev_get_pf(dev->pf_func),\n+\t\t dev_get_vf(dev->pf_func), info->hdr.id, mbox_id2name(info->hdr.id),\n+\t\t dev_get_pf(info->hdr.pcifunc), dev_get_vf(info->hdr.pcifunc));\n+\n+\tmcs = roc_idev_mcs_get(info->mcs_id);\n+\tif (!mcs)\n+\t\tgoto exit;\n+\n+\tif (info->intr_mask) {\n+\t\tswitch (info->intr_mask) {\n+\t\tcase MCS_CPM_RX_SECTAG_V_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_V_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_SL_GTE48_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_SL_GTE48;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_PACKET_XPN_EQ0_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_RX_SA_PN_HARD_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_PN_THRESH_REACHED_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_PACKET_XPN_EQ0_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_TX_SA_PN_HARD_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_PN_THRESH_REACHED_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_SA_NOT_VALID_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SA_NOT_VALID;\n+\t\t\tbreak;\n+\t\tcase MCS_BBE_RX_DFIFO_OVERFLOW_INT:\n+\t\tcase MCS_BBE_TX_DFIFO_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_DATA_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tcase MCS_BBE_RX_PLFIFO_OVERFLOW_INT:\n+\t\tcase MCS_BBE_TX_PLFIFO_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tcase MCS_PAB_RX_CHAN_OVERFLOW_INT:\n+\t\tcase MCS_PAB_TX_CHAN_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tmcs_event_cb_process(mcs, &desc);\n+\t}\n+\n+exit:\n+\trsp->hdr.rc = 0;\n+\treturn 0;\n+}\n+\n static int\n mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg,\n \t\t\t struct msg_rsp *rsp)\n@@ -615,6 +700,7 @@ mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)\n \t\treturn err; \\\n \t}\n \t\tMBOX_UP_CGX_MESSAGES\n+\t\tMBOX_UP_MCS_MESSAGES\n #undef M\n \t}\n \ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 3f3a6aadc8..d964ba9f9d 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -316,6 +316,7 @@ struct mbox_msghdr {\n \tM(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \\\n \tM(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, mcs_port_stats) \\\n \tM(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \\\n+\tM(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \\\n \tM(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \\\n \tM(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \\\n \n@@ -324,9 +325,11 @@ struct mbox_msghdr {\n \tM(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \\\n \tM(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)\n \n+#define MBOX_UP_MCS_MESSAGES M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)\n+\n enum {\n #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,\n-\tMBOX_MESSAGES MBOX_UP_CGX_MESSAGES\n+\tMBOX_MESSAGES MBOX_UP_CGX_MESSAGES MBOX_UP_MCS_MESSAGES\n #undef M\n };\n \n@@ -867,6 +870,38 @@ struct mcs_set_active_lmac {\n \tuint64_t __io rsvd;\n };\n \n+#define MCS_CPM_RX_SECTAG_V_EQ1_INT\t BIT_ULL(0)\n+#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)\n+#define MCS_CPM_RX_SECTAG_SL_GTE48_INT\t BIT_ULL(2)\n+#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)\n+#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)\n+#define MCS_CPM_RX_PACKET_XPN_EQ0_INT\t BIT_ULL(5)\n+#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)\n+#define MCS_CPM_TX_PACKET_XPN_EQ0_INT\t BIT_ULL(7)\n+#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)\n+#define MCS_CPM_TX_SA_NOT_VALID_INT\t BIT_ULL(9)\n+#define MCS_BBE_RX_DFIFO_OVERFLOW_INT\t BIT_ULL(10)\n+#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT\t BIT_ULL(11)\n+#define MCS_BBE_TX_DFIFO_OVERFLOW_INT\t BIT_ULL(12)\n+#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT\t BIT_ULL(13)\n+#define MCS_PAB_RX_CHAN_OVERFLOW_INT\t BIT_ULL(14)\n+#define MCS_PAB_TX_CHAN_OVERFLOW_INT\t BIT_ULL(15)\n+\n+struct mcs_intr_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io intr_mask; /* Interrupt enable mask */\n+\tuint8_t __io mcs_id;\n+};\n+\n+struct mcs_intr_info {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io intr_mask;\n+\tint __io sa_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io lmac_id;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_set_lmac_mode {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nindex 38f1e9b2f7..e9090da575 100644\n--- a/drivers/common/cnxk/roc_mcs.c\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -5,6 +5,18 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+struct mcs_event_cb {\n+\tTAILQ_ENTRY(mcs_event_cb) next;\n+\tenum roc_mcs_event_type event;\n+\troc_mcs_dev_cb_fn cb_fn;\n+\tvoid *cb_arg;\n+\tvoid *ret_param;\n+\tuint32_t active;\n+};\n+TAILQ_HEAD(mcs_event_cb_list, mcs_event_cb);\n+\n+PLT_STATIC_ASSERT(ROC_MCS_MEM_SZ >= (sizeof(struct mcs_priv) + sizeof(struct mcs_event_cb_list)));\n+\n int\n roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info)\n {\n@@ -109,6 +121,107 @@ roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *p\n \treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n }\n \n+int\n+roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)\n+{\n+\tstruct mcs_intr_cfg *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tif (config == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_intr_cfg(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->intr_mask = config->intr_mask;\n+\treq->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,\n+\t\t\t roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb *cb;\n+\n+\tif (cb_fn == NULL || cb_arg == NULL || userdata == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tTAILQ_FOREACH (cb, cb_list, next) {\n+\t\tif (cb->cb_fn == cb_fn && cb->cb_arg == cb_arg && cb->event == event)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (cb == NULL) {\n+\t\tcb = plt_zmalloc(sizeof(struct mcs_event_cb), 0);\n+\t\tif (!cb)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tcb->cb_fn = cb_fn;\n+\t\tcb->cb_arg = cb_arg;\n+\t\tcb->event = event;\n+\t\tmcs->userdata = userdata;\n+\t\tTAILQ_INSERT_TAIL(cb_list, cb, next);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb *cb, *next;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tfor (cb = TAILQ_FIRST(cb_list); cb != NULL; cb = next) {\n+\t\tnext = TAILQ_NEXT(cb, next);\n+\n+\t\tif (cb->event != event)\n+\t\t\tcontinue;\n+\n+\t\tif (cb->active == 0) {\n+\t\t\tTAILQ_REMOVE(cb_list, cb, next);\n+\t\t\tplt_free(cb);\n+\t\t} else {\n+\t\t\treturn -EAGAIN;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb mcs_cb;\n+\tstruct mcs_event_cb *cb;\n+\tint rc = 0;\n+\n+\tTAILQ_FOREACH (cb, cb_list, next) {\n+\t\tif (cb->cb_fn == NULL || cb->event != desc->type)\n+\t\t\tcontinue;\n+\n+\t\tmcs_cb = *cb;\n+\t\tcb->active = 1;\n+\t\tmcs_cb.ret_param = desc;\n+\n+\t\trc = mcs_cb.cb_fn(mcs->userdata, mcs_cb.ret_param, mcs_cb.cb_arg);\n+\t\tcb->active = 0;\n+\t}\n+\n+\treturn rc;\n+}\n+\n static int\n mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap)\n {\n@@ -227,6 +340,7 @@ mcs_alloc_rsrc_bmap(struct roc_mcs *mcs)\n struct roc_mcs *\n roc_mcs_dev_init(uint8_t mcs_idx)\n {\n+\tstruct mcs_event_cb_list *cb_list;\n \tstruct roc_mcs *mcs;\n \tstruct npa_lf *npa;\n \n@@ -255,6 +369,9 @@ roc_mcs_dev_init(uint8_t mcs_idx)\n \tif (mcs_alloc_rsrc_bmap(mcs))\n \t\tgoto exit;\n \n+\tcb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tTAILQ_INIT(cb_list);\n+\n \troc_idev_mcs_set(mcs);\n \tmcs->refcount++;\n \ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex 3fbeee13fa..b2ca6ee51b 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -116,6 +116,34 @@ struct roc_mcs_hw_info {\n \tuint64_t rsvd[16];\n };\n \n+#define ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT\t\t BIT_ULL(0)\n+#define ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT\t BIT_ULL(1)\n+#define ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT\t BIT_ULL(2)\n+#define ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT\t BIT_ULL(3)\n+#define ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)\n+#define ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT\t BIT_ULL(5)\n+#define ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT\t BIT_ULL(6)\n+#define ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT\t BIT_ULL(7)\n+#define ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT\t BIT_ULL(8)\n+#define ROC_MCS_CPM_TX_SA_NOT_VALID_INT\t\t BIT_ULL(9)\n+#define ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT\t BIT_ULL(10)\n+#define ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT\t BIT_ULL(11)\n+#define ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT\t BIT_ULL(12)\n+#define ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT\t BIT_ULL(13)\n+#define ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT\t BIT_ULL(14)\n+#define ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT\t BIT_ULL(15)\n+\n+struct roc_mcs_intr_cfg {\n+\tuint64_t intr_mask; /* Interrupt enable mask */\n+};\n+\n+struct roc_mcs_intr_info {\n+\tuint64_t intr_mask;\n+\tint sa_id;\n+\tuint8_t lmac_id;\n+\tuint64_t rsvd;\n+};\n+\n struct roc_mcs_set_lmac_mode {\n \tuint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\n \tuint8_t lmac_id;\n@@ -205,6 +233,113 @@ struct roc_mcs_clear_stats {\n \tuint8_t all; /* All resources stats mapped to PF are cleared */\n };\n \n+enum roc_mcs_event_subtype {\n+\tROC_MCS_SUBEVENT_UNKNOWN,\n+\n+\t/* subevents of ROC_MCS_EVENT_SECTAG_VAL_ERR sectag validation events\n+\t * ROC_MCS_EVENT_RX_SECTAG_V_EQ1\n+\t *\tValidation check: SecTag.TCI.V = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1\n+\t *\tValidation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_SL_GTE48\n+\t *\tValidation check: SecTag.SL >= 'd48\n+\t * ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1\n+\t *\tValidation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1\n+\t *\tValidation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1\n+\t */\n+\tROC_MCS_EVENT_RX_SECTAG_V_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_SL_GTE48,\n+\tROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1,\n+\n+\t/* subevents of ROC_MCS_EVENT_FIFO_OVERFLOW error event\n+\t * ROC_MCS_EVENT_DATA_FIFO_OVERFLOW:\n+\t *\tNotifies data FIFO overflow fatal error in BBE unit.\n+\t * ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW\n+\t *\tNotifies policy FIFO overflow fatal error in BBE unit.\n+\t * ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,\n+\t *\tNotifies output FIFO overflow fatal error in PAB unit.\n+\t */\n+\tROC_MCS_EVENT_DATA_FIFO_OVERFLOW,\n+\tROC_MCS_EVENT_POLICY_FIFO_OVERFLOW,\n+\tROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,\n+};\n+\n+enum roc_mcs_event_type {\n+\tROC_MCS_EVENT_UNKNOWN,\n+\n+\t/* Notifies BBE_INT_DFIFO/PLFIFO_OVERFLOW or PAB_INT_OVERFLOW\n+\t * interrupts, it's a fatal error that causes packet corruption.\n+\t */\n+\tROC_MCS_EVENT_FIFO_OVERFLOW,\n+\n+\t/* Notifies CPM_RX_SECTAG_X validation error interrupt */\n+\tROC_MCS_EVENT_SECTAG_VAL_ERR,\n+\t/* Notifies CPM_RX_PACKET_XPN_EQ0 (SecTag.PN == 0 in ingress) interrupt */\n+\tROC_MCS_EVENT_RX_SA_PN_HARD_EXP,\n+\t/* Notifies CPM_RX_PN_THRESH_REACHED interrupt */\n+\tROC_MCS_EVENT_RX_SA_PN_SOFT_EXP,\n+\t/* Notifies CPM_TX_PACKET_XPN_EQ0 (PN wrapped in egress) interrupt */\n+\tROC_MCS_EVENT_TX_SA_PN_HARD_EXP,\n+\t/* Notifies CPM_TX_PN_THRESH_REACHED interrupt */\n+\tROC_MCS_EVENT_TX_SA_PN_SOFT_EXP,\n+\t/* Notifies CPM_TX_SA_NOT_VALID interrupt */\n+\tROC_MCS_EVENT_SA_NOT_VALID,\n+\t/* Notifies recovery of software driven port reset */\n+\tROC_MCS_EVENT_PORT_RESET_RECOVERY,\n+};\n+\n+union roc_mcs_event_data {\n+\t/* Valid for below events\n+\t * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP\n+\t * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP\n+\t */\n+\tstruct {\n+\t\tuint8_t secy_idx;\n+\t\tuint8_t sc_idx;\n+\t\tuint8_t sa_idx;\n+\t};\n+\t/* Valid for below event\n+\t * - ROC_MCS_EVENT_FIFO_OVERFLOW\n+\t *\n+\t * Upon fatal error notification on a MCS port, ROC driver resets below attributes of active\n+\t * flow entities(sc & sa) and than resets the port.\n+\t * - Reset NEXT_PN of active SAs to 1.\n+\t * - Reset TX active SA for each SC, TX_SA_ACTIVE = 0, SA_INDEX0_VLD = 1.\n+\t * - Clear SA_IN_USE for active ANs in RX_SA_MAP_MEM.\n+\t * - Clear all stats mapping to this port.\n+\t * - Reactivate SA_IN_USE for active ANs in RX_SA_MAP_MEM.\n+\t *\n+\t * ROC driver notifies the following flow entity(sc & sa) details in application callback,\n+\t * application is expected to exchange the Tx/Rx NEXT_PN, TX_SA_ACTIVE, active RX SC AN\n+\t * details with peer device so that peer device can resets it's MACsec flow states and than\n+\t * resume packet transfers.\n+\t */\n+\tstruct {\n+\t\tuint16_t *tx_sa_array; /* Tx SAs whose PN memories were reset (NEXT_PN=1) */\n+\t\tuint16_t *rx_sa_array; /* Rx SAs whose PN memories were reset (NEXT_PN=1) */\n+\t\tuint16_t *tx_sc_array; /* Tx SCs whose active SAs were reset (TX_SA_ACTIVE=0) */\n+\t\tuint16_t *rx_sc_array; /* Rx SCs whose state was reset */\n+\t\tuint8_t *sc_an_array; /* AN of Rx SCs(in rx_sc_array) which were reactivated */\n+\t\tuint8_t num_tx_sa; /* num entries in tx_sa_array */\n+\t\tuint8_t num_rx_sa; /* num entries in rx_sa_array */\n+\t\tuint8_t num_tx_sc; /* num entries in tx_sc_array */\n+\t\tuint8_t num_rx_sc; /* num entries in rx_sc_array */\n+\t\tuint8_t lmac_id; /* lmac_id/port which was recovered from fatal error */\n+\t};\n+};\n+\n+struct roc_mcs_event_desc {\n+\tenum roc_mcs_event_type type;\n+\tenum roc_mcs_event_subtype subtype;\n+\tunion roc_mcs_event_data metadata;\n+};\n+\n+/** User application callback to be registered for any notifications from driver. */\n+typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg);\n+\n struct roc_mcs {\n \tTAILQ_ENTRY(roc_mcs) next;\n \tstruct plt_pci_device *pci_dev;\n@@ -292,4 +427,13 @@ __roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_r\n /* Clear stats */\n __roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req);\n \n+/* Register user callback routines */\n+__roc_api int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,\n+\t\t\t\t\troc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata);\n+/* Unregister user callback routines */\n+__roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event);\n+\n+/* Configure interrupts */\n+__roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config);\n+\n #endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h\nindex 9e0bbe4392..8da03f4295 100644\n--- a/drivers/common/cnxk/roc_mcs_priv.h\n+++ b/drivers/common/cnxk/roc_mcs_priv.h\n@@ -62,4 +62,12 @@ roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs)\n \treturn (struct mcs_priv *)&roc_mcs->reserved[0];\n }\n \n+static inline void *\n+roc_mcs_to_mcs_cb_list(struct roc_mcs *roc_mcs)\n+{\n+\treturn (void *)((uintptr_t)roc_mcs->reserved + sizeof(struct mcs_priv));\n+}\n+\n+int mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc);\n+\n #endif /* _ROC_MCS_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex d8890e3538..d10dfcd84e 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -139,11 +139,14 @@ INTERNAL {\n \troc_mcs_dev_init;\n \troc_mcs_dev_fini;\n \troc_mcs_dev_get;\n+\troc_mcs_event_cb_register;\n+\troc_mcs_event_cb_unregister;\n \troc_mcs_flowid_entry_enable;\n \troc_mcs_flowid_entry_read;\n \troc_mcs_flowid_entry_write;\n \troc_mcs_flowid_stats_get;\n \troc_mcs_hw_info_get;\n+\troc_mcs_intr_configure;\n \troc_mcs_lmac_mode_set;\n \troc_mcs_pn_table_write;\n \troc_mcs_pn_table_read;\n", "prefixes": [ "v3", "07/15" ] }