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GET /api/patches/128539/?format=api
{ "id": 128539, "url": "http://patches.dpdk.org/api/patches/128539/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-6-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-6-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-6-gakhil@marvell.com", "date": "2023-06-13T07:16:04", "name": "[v3,05/15] common/cnxk: add MACsec PN and LMAC mode configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c4a59704a18820c47c3807acb871de8b9cb77ae6", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-6-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128539/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/128539/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5482542CA0;\n\tTue, 13 Jun 2023 09:17:15 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7714542D38;\n\tTue, 13 Jun 2023 09:16:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 86A8342D2C\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:16:49 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D567pr005545; Tue, 13 Jun 2023 00:16:48 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235fw-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:16:48 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:46 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:46 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id DEE365E6861;\n Tue, 13 Jun 2023 00:16:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=bXI/acpXUZVKal/KYoxd95y8N5Gz8oVwqTMZLMqMVBY=;\n b=KDWAimUcPoz9yr1OmNmPPDR9rsnmMhi3JF6sOrVxugZWeWf62y99M6P8d1mx8tUQU/Qo\n JdxwV6efQu6x9Alzwu+3xPfP7u5CaOLL1O2DwAlgrdcMS8iqolkORqY0kmJ/ePCVpO9T\n PMpSnlApC07ymWK6Z5egWUcBx29RKj9ge2JFEMsjKHjrP04Fi+0kq6PA0pSdoH9GXkF4\n hA1B7I/iGv4G6hjsK8jgzEcnTIncNnAdrIXCc0nmMACAtdha7aYl0n7ZQdnp5MXMVLiL\n QCJlh2D+Q8F+25JJOQBmagAEK7dxW5jSYgwiTFillMgeVXVui6nvgY8XsYtf6swtNmpv og==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 05/15] common/cnxk: add MACsec PN and LMAC mode\n configuration", "Date": "Tue, 13 Jun 2023 12:46:04 +0530", "Message-ID": "<20230613071614.2259604-6-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5KWWCUC-JHZ44i8J01jqeQRM0teKroPK", "X-Proofpoint-GUID": "5KWWCUC-JHZ44i8J01jqeQRM0teKroPK", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs for setting packet number and LMAC\nrelated configurations.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 56 +++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.c | 71 +++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 48 ++++++++++++++++++\n drivers/common/cnxk/roc_mcs_sec_cfg.c | 31 ++++++++++++\n drivers/common/cnxk/version.map | 5 ++\n 5 files changed, 211 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex fcfcc90f6c..62c5c3a3ce 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -308,7 +308,11 @@ struct mbox_msghdr {\n \tM(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \\\n \tM(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \\\n \tM(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \\\n+\tM(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, msg_rsp) \\\n+\tM(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, msg_rsp) \\\n \tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n+\tM(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \\\n+\tM(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -812,6 +816,34 @@ struct mcs_flowid_ena_dis_entry {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_pn_table_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io next_pn;\n+\tuint8_t __io pn_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_cam_entry_read_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_type; /* TCAM/SECY/SC/SA/PN */\n+\tuint8_t __io rsrc_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_cam_entry_read_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io reg_val[10];\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_hw_info {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io num_mcs_blks; /* Number of MCS blocks */\n@@ -822,6 +854,30 @@ struct mcs_hw_info {\n \tuint64_t __io rsvd[16];\n };\n \n+struct mcs_set_active_lmac {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io lmac_bmap; /* bitmap of active lmac per mcs block */\n+\tuint8_t __io mcs_id;\n+\tuint16_t __io channel_base; /* MCS channel base */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_set_lmac_mode {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\n+\tuint8_t __io lmac_id;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_set_pn_threshold {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io threshold;\n+\tuint8_t __io xpn; /* '1' for setting xpn threshold */\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n \n /* NPA mbox message formats */\n \ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nindex 20433eae83..38f1e9b2f7 100644\n--- a/drivers/common/cnxk/roc_mcs.c\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -38,6 +38,77 @@ roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info)\n \treturn rc;\n }\n \n+int\n+roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac)\n+{\n+\tstruct mcs_set_active_lmac *req;\n+\tstruct msg_rsp *rsp;\n+\n+\t/* Only needed for 105N */\n+\tif (!roc_model_is_cnf10kb())\n+\t\treturn 0;\n+\n+\tif (lmac == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_set_active_lmac(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->lmac_bmap = lmac->lmac_bmap;\n+\treq->channel_base = lmac->channel_base;\n+\treq->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port)\n+{\n+\tstruct mcs_set_lmac_mode *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tif (port == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_set_lmac_mode(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->lmac_id = port->lmac_id;\n+\treq->mcs_id = mcs->idx;\n+\treq->mode = port->mode;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn)\n+{\n+\tstruct mcs_set_pn_threshold *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tif (pn == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_set_pn_threshold(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->threshold = pn->threshold;\n+\treq->mcs_id = mcs->idx;\n+\treq->dir = pn->dir;\n+\treq->xpn = pn->xpn;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n static int\n mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap)\n {\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex 38c2d5626a..bedae3bf42 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -88,6 +88,25 @@ struct roc_mcs_flowid_ena_dis_entry {\n \tuint8_t dir;\n };\n \n+struct roc_mcs_pn_table_write_req {\n+\tuint64_t next_pn;\n+\tuint8_t pn_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_cam_entry_read_req {\n+\tuint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */\n+\tuint8_t rsrc_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_cam_entry_read_rsp {\n+\tuint64_t reg_val[10];\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_id;\n+\tuint8_t dir;\n+};\n+\n struct roc_mcs_hw_info {\n \tuint8_t num_mcs_blks; /* Number of MCS blocks */\n \tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n@@ -97,6 +116,24 @@ struct roc_mcs_hw_info {\n \tuint64_t rsvd[16];\n };\n \n+struct roc_mcs_set_lmac_mode {\n+\tuint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\n+\tuint8_t lmac_id;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_set_active_lmac {\n+\tuint32_t lmac_bmap; /* bitmap of active lmac per mcs block */\n+\tuint16_t channel_base; /* MCS channel base */\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_set_pn_threshold {\n+\tuint64_t threshold;\n+\tuint8_t xpn; /* '1' for setting xpn threshold */\n+\tuint8_t dir;\n+\tuint64_t rsvd;\n+};\n \n struct roc_mcs {\n \tTAILQ_ENTRY(roc_mcs) next;\n@@ -119,6 +156,12 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs);\n __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx);\n /* HW info get */\n __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info);\n+/* Active lmac bmap set */\n+__roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac);\n+/* Port bypass mode set */\n+__roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port);\n+/* (X)PN threshold set */\n+__roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn);\n \n /* Resource allocation and free */\n __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n@@ -129,6 +172,11 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n+/* PN Table read and write */\n+__roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_pn_table_write_req *pn_table);\n+__roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_pn_table_write_req *pn_table);\n /* RX SC read, write and enable */\n __roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\ndiff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c\nindex 44b4919bbc..7b3a4c91e8 100644\n--- a/drivers/common/cnxk/roc_mcs_sec_cfg.c\n+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c\n@@ -210,6 +210,37 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused,\n \treturn -ENOTSUP;\n }\n \n+int\n+roc_mcs_pn_table_write(struct roc_mcs *mcs, struct roc_mcs_pn_table_write_req *pn_table)\n+{\n+\tstruct mcs_pn_table_write_req *pn;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (pn_table == NULL)\n+\t\treturn -EINVAL;\n+\n+\tpn = mbox_alloc_msg_mcs_pn_table_write(mcs->mbox);\n+\tif (pn == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tpn->next_pn = pn_table->next_pn;\n+\tpn->pn_id = pn_table->pn_id;\n+\tpn->mcs_id = mcs->idx;\n+\tpn->dir = pn_table->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_pn_table_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_pn_table_write_req *sa __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n \n int\n roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam)\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 3d9da3b187..0591747961 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -135,6 +135,7 @@ INTERNAL {\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n \troc_se_ctx_init;\n+\troc_mcs_active_lmac_set;\n \troc_mcs_dev_init;\n \troc_mcs_dev_fini;\n \troc_mcs_dev_get;\n@@ -142,6 +143,10 @@ INTERNAL {\n \troc_mcs_flowid_entry_read;\n \troc_mcs_flowid_entry_write;\n \troc_mcs_hw_info_get;\n+\troc_mcs_lmac_mode_set;\n+\troc_mcs_pn_table_write;\n+\troc_mcs_pn_table_read;\n+\troc_mcs_pn_threshold_set;\n \troc_mcs_rsrc_alloc;\n \troc_mcs_rsrc_free;\n \troc_mcs_rx_sc_cam_enable;\n", "prefixes": [ "v3", "05/15" ] }