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GET /api/patches/128538/?format=api
{ "id": 128538, "url": "http://patches.dpdk.org/api/patches/128538/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-5-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-5-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-5-gakhil@marvell.com", "date": "2023-06-13T07:16:03", "name": "[v3,04/15] common/cnxk: add MACsec secy and flow configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "99ea25fd1df6950965043a68475e01bd4c89b031", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230613071614.2259604-5-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patches.dpdk.org/api/series/28472/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patches.dpdk.org/series/28472/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128538/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/128538/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC47542CA0;\n\tTue, 13 Jun 2023 09:17:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 97E0342D17;\n\tTue, 13 Jun 2023 09:16:47 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 27FCE42D17\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:16:46 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D56eUT006463; Tue, 13 Jun 2023 00:16:45 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235fg-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:16:45 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:43 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:43 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id B78C75E6864;\n Tue, 13 Jun 2023 00:16:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=WQuT1z3J6RcfQ2zt9uyG1mVNjrNvuKnl3WEjoibd5LI=;\n b=SLKKoGLkBzB6xb5hBuQwOGFsZm3KxeJINgNvb2sA4D+Tm2cpGR3Ba3sRdSaqnFO98SyQ\n mIElky/K1Wj4a4ie43aCJtIaqR98DxpMZRlOp0R3yWH2EqLcw4QKvtF+DDo2NAJhqTDS\n GeCaOfPv7tcP2psO1nSvwi5gl+v5xJtRZOD3JbXCEVgP30WCk28TyKdmaMvwckarkC9i\n adIyzoVRRzPwdcy9BCS2CKQ/W/oCWK9FMi5XR9qOb4BsBRZGNy70dDBB6StgC6w6rgFs\n rNTNgvoM6FT8gxayR4efuRA9RkD3ze7dfl1FCFlVnKpWiolDwciHCc2gLvdtX1pcbl+v Ng==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 04/15] common/cnxk: add MACsec secy and flow configuration", "Date": "Tue, 13 Jun 2023 12:46:03 +0530", "Message-ID": "<20230613071614.2259604-5-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "z8ZS5bbveg4SybvEK_Ze0CbZrHSZRFdi", "X-Proofpoint-GUID": "z8ZS5bbveg4SybvEK_Ze0CbZrHSZRFdi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs to configure MACsec secy policy and\nflow entries.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 38 +++++++++\n drivers/common/cnxk/roc_mcs.h | 37 +++++++++\n drivers/common/cnxk/roc_mcs_sec_cfg.c | 115 ++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 5 ++\n 4 files changed, 195 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 40b761ee99..fcfcc90f6c 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -300,10 +300,14 @@ struct mbox_msghdr {\n \tM(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \\\n \t mcs_alloc_rsrc_rsp) \\\n \tM(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \\\n+\tM(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \\\n+\t msg_rsp) \\\n+\tM(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, msg_rsp) \\\n \tM(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \\\n \tM(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \\\n \tM(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \\\n \tM(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \\\n+\tM(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \\\n \tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n@@ -729,6 +733,31 @@ struct mcs_free_rsrc_req {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_flowid_entry_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io data[4];\n+\tuint64_t __io mask[4];\n+\tuint64_t __io sci; /* CNF10K-B for tx_secy_mem_map */\n+\tuint8_t __io flow_id;\n+\tuint8_t __io secy_id; /* secyid for which flowid is mapped */\n+\t/* sc_id is Valid if dir = MCS_TX, SC_CAM id mapped to flowid */\n+\tuint8_t __io sc_id;\n+\tuint8_t __io ena; /* Enable tcam entry */\n+\tuint8_t __io ctr_pkt;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_secy_plcy_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io plcy;\n+\tuint8_t __io secy_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n /* RX SC_CAM mapping */\n struct mcs_rx_sc_cam_write_req {\n \tstruct mbox_msghdr hdr;\n@@ -774,6 +803,15 @@ struct mcs_rx_sc_sa_map {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_flowid_ena_dis_entry {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io flow_id;\n+\tuint8_t __io ena;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_hw_info {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io num_mcs_blks; /* Number of MCS blocks */\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex e947f93460..38c2d5626a 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -32,6 +32,24 @@ struct roc_mcs_free_rsrc_req {\n \tuint8_t all; /* Free all the cam resources */\n };\n \n+struct roc_mcs_flowid_entry_write_req {\n+\tuint64_t data[4];\n+\tuint64_t mask[4];\n+\tuint64_t sci; /* 105N for tx_secy_mem_map */\n+\tuint8_t flow_id;\n+\tuint8_t secy_id; /* secyid for which flowid is mapped */\n+\tuint8_t sc_id;\t /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */\n+\tuint8_t ena;\t /* Enable tcam entry */\n+\tuint8_t ctr_pkt;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_secy_plcy_write_req {\n+\tuint64_t plcy;\n+\tuint8_t secy_id;\n+\tuint8_t dir;\n+};\n+\n /* RX SC_CAM mapping */\n struct roc_mcs_rx_sc_cam_write_req {\n \tuint64_t sci;\t /* SCI */\n@@ -64,6 +82,12 @@ struct roc_mcs_rx_sc_sa_map {\n \tuint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */\n };\n \n+struct roc_mcs_flowid_ena_dis_entry {\n+\tuint8_t flow_id;\n+\tuint8_t ena;\n+\tuint8_t dir;\n+};\n+\n struct roc_mcs_hw_info {\n \tuint8_t num_mcs_blks; /* Number of MCS blocks */\n \tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n@@ -112,6 +136,11 @@ __roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n __roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+/* SECY policy read and write */\n+__roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_secy_plcy_write_req *secy_plcy);\n+__roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n /* RX SC-SA MAP read and write */\n __roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs,\n \t\t\t\t\t struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);\n@@ -122,4 +151,12 @@ __roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs,\n \t\t\t\t\t struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n __roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs,\n \t\t\t\t\tstruct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n+/* Flow entry read, write and enable */\n+__roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_flowid_entry_write_req *flowid_req);\n+__roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_flowid_entry_write_req *flowid_rsp);\n+__roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_flowid_ena_dis_entry *entry);\n+\n #endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c\nindex 9b87952112..44b4919bbc 100644\n--- a/drivers/common/cnxk/roc_mcs_sec_cfg.c\n+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c\n@@ -267,6 +267,38 @@ roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused,\n \treturn -ENOTSUP;\n }\n \n+int\n+roc_mcs_secy_policy_write(struct roc_mcs *mcs, struct roc_mcs_secy_plcy_write_req *secy_plcy)\n+{\n+\tstruct mcs_secy_plcy_write_req *secy;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (secy_plcy == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsecy = mbox_alloc_msg_mcs_secy_plcy_write(mcs->mbox);\n+\tif (secy == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsecy->plcy = secy_plcy->plcy;\n+\tsecy->secy_id = secy_plcy->secy_id;\n+\tsecy->mcs_id = mcs->idx;\n+\tsecy->dir = secy_plcy->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_secy_policy_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n int\n roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map)\n {\n@@ -380,3 +412,86 @@ roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,\n \n \treturn -ENOTSUP;\n }\n+\n+int\n+roc_mcs_flowid_entry_write(struct roc_mcs *mcs, struct roc_mcs_flowid_entry_write_req *flowid_req)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_flowid_entry_write_req *flow_req;\n+\tstruct msg_rsp *rsp;\n+\tuint8_t port;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (flowid_req == NULL)\n+\t\treturn -EINVAL;\n+\n+\tflow_req = mbox_alloc_msg_mcs_flowid_entry_write(mcs->mbox);\n+\tif (flow_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tmbox_memcpy(flow_req->data, flowid_req->data, sizeof(uint64_t) * 4);\n+\tmbox_memcpy(flow_req->mask, flowid_req->mask, sizeof(uint64_t) * 4);\n+\tflow_req->sci = flowid_req->sci;\n+\tflow_req->flow_id = flowid_req->flow_id;\n+\tflow_req->secy_id = flowid_req->secy_id;\n+\tflow_req->sc_id = flowid_req->sc_id;\n+\tflow_req->ena = flowid_req->ena;\n+\tflow_req->ctr_pkt = flowid_req->ctr_pkt;\n+\tflow_req->mcs_id = mcs->idx;\n+\tflow_req->dir = flowid_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (flow_req->mask[3] & (BIT_ULL(10) | BIT_ULL(11)))\n+\t\treturn rc;\n+\n+\tport = (flow_req->data[3] >> 10) & 0x3;\n+\n+\tplt_bitmap_set(priv->port_rsrc[port].tcam_bmap,\n+\t\t flowid_req->flow_id +\n+\t\t\t ((flowid_req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\tplt_bitmap_set(priv->port_rsrc[port].secy_bmap,\n+\t\t flowid_req->secy_id +\n+\t\t\t ((flowid_req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\n+\tif (flowid_req->dir == MCS_TX)\n+\t\tplt_bitmap_set(priv->port_rsrc[port].sc_bmap, priv->sc_entries + flowid_req->sc_id);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_flowid_entry_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_flowid_entry_write_req *flowid_rsp __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry)\n+{\n+\tstruct mcs_flowid_ena_dis_entry *flow_entry;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (entry == NULL)\n+\t\treturn -EINVAL;\n+\n+\tflow_entry = mbox_alloc_msg_mcs_flowid_ena_entry(mcs->mbox);\n+\tif (flow_entry == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tflow_entry->flow_id = entry->flow_id;\n+\tflow_entry->ena = entry->ena;\n+\tflow_entry->mcs_id = mcs->idx;\n+\tflow_entry->dir = entry->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex dbfda62ad1..3d9da3b187 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -138,6 +138,9 @@ INTERNAL {\n \troc_mcs_dev_init;\n \troc_mcs_dev_fini;\n \troc_mcs_dev_get;\n+\troc_mcs_flowid_entry_enable;\n+\troc_mcs_flowid_entry_read;\n+\troc_mcs_flowid_entry_write;\n \troc_mcs_hw_info_get;\n \troc_mcs_rsrc_alloc;\n \troc_mcs_rsrc_free;\n@@ -148,6 +151,8 @@ INTERNAL {\n \troc_mcs_rx_sc_sa_map_write;\n \troc_mcs_sa_policy_read;\n \troc_mcs_sa_policy_write;\n+\troc_mcs_secy_policy_read;\n+\troc_mcs_secy_policy_write;\n \troc_mcs_tx_sc_sa_map_read;\n \troc_mcs_tx_sc_sa_map_write;\n \troc_nix_bpf_alloc;\n", "prefixes": [ "v3", "04/15" ] }