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GET /api/patches/127741/?format=api
{ "id": 127741, "url": "http://patches.dpdk.org/api/patches/127741/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230531053743.129442-4-miao.li@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230531053743.129442-4-miao.li@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230531053743.129442-4-miao.li@intel.com", "date": "2023-05-31T05:37:41", "name": "[v4,3/4] bus/pci: introduce helper for MMIO read and write", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f3a2a4b177f5bc01e6539e253fd1d3c73a79bb26", "submitter": { "id": 2220, "url": "http://patches.dpdk.org/api/people/2220/?format=api", "name": "Li, Miao", "email": "miao.li@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230531053743.129442-4-miao.li@intel.com/mbox/", "series": [ { "id": 28263, "url": "http://patches.dpdk.org/api/series/28263/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28263", "date": "2023-05-31T05:37:38", "name": "Support VFIO sparse mmap in PCI bus", "version": 4, "mbox": "http://patches.dpdk.org/series/28263/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/127741/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/127741/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3041E42BEB;\n\tWed, 31 May 2023 07:38:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B266442D17;\n\tWed, 31 May 2023 07:38:08 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 3092340A87\n for <dev@dpdk.org>; Wed, 31 May 2023 07:38:04 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 May 2023 22:38:03 -0700", "from dpdk-limiao-icelake.sh.intel.com ([10.67.111.26])\n by orsmga006.jf.intel.com with ESMTP; 30 May 2023 22:38:01 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1685511484; x=1717047484;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=HPST99BHqbXfp59PqBYl4GiL1jA6VL54BUQL7V0cVjg=;\n b=PT6rq30yjuhEUSIj/KnxGfkYhqkvdjpw1cuV1X5cTPpcxbOJSLde58iK\n fTB6yPyalrdukv2JXw/tfXDU9ZwAAS4DDLDiB7jYg5V0lfYAQ0BwoHfa9\n +bvNmqdX7A6zQIIXJRPTig52z1Y+Be7CtIoik4N82TgM5cndeM3i+oJ0Q\n e2/B/MvdrE4Rx4k9QwldKAMcvJVVINZmECk1AFn7fiInwkZcCyzbtzVBJ\n JK1fmI7zEiiE7x47FCQg8d3mgM3lcaXjuK4Io6iMBSi1Wn4/ZKbOlmp5B\n FYAf6eh3h0TT+ZnCHty5/2ar6F6LtjvB2FExAlLwLW2t0qqgBWykvIFNt A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10726\"; a=\"335489295\"", "E=Sophos;i=\"6.00,205,1681196400\"; d=\"scan'208\";a=\"335489295\"", "E=McAfee;i=\"6600,9927,10726\"; a=\"684273531\"", "E=Sophos;i=\"6.00,205,1681196400\"; d=\"scan'208\";a=\"684273531\"" ], "X-ExtLoop1": "1", "From": "Miao Li <miao.li@intel.com>", "To": "dev@dpdk.org", "Cc": "skori@marvell.com, thomas@monjalon.net, david.marchand@redhat.com,\n ferruh.yigit@amd.com, chenbo.xia@intel.com, yahui.cao@intel.com,\n Anatoly Burakov <anatoly.burakov@intel.com>", "Subject": "[PATCH v4 3/4] bus/pci: introduce helper for MMIO read and write", "Date": "Wed, 31 May 2023 05:37:41 +0000", "Message-Id": "<20230531053743.129442-4-miao.li@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230531053743.129442-1-miao.li@intel.com>", "References": "<20230525163116.682000-1-miao.li@intel.com>\n <20230531053743.129442-1-miao.li@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Chenbo Xia <chenbo.xia@intel.com>\n\nThe MMIO regions may not be mmap-able for VFIO-PCI devices.\nIn this case, the driver should explicitly do read and write\nto access these regions.\n\nSigned-off-by: Chenbo Xia <chenbo.xia@intel.com>\nAcked-by: Sunil Kumar Kori <skori@marvell.com>\nAcked-by: Yahui Cao <yahui.cao@intel.com>\n---\n doc/guides/rel_notes/release_23_07.rst | 5 +++\n drivers/bus/pci/bsd/pci.c | 22 ++++++++++++\n drivers/bus/pci/linux/pci.c | 46 ++++++++++++++++++++++++\n drivers/bus/pci/linux/pci_init.h | 10 ++++++\n drivers/bus/pci/linux/pci_uio.c | 22 ++++++++++++\n drivers/bus/pci/linux/pci_vfio.c | 36 +++++++++++++++++++\n drivers/bus/pci/rte_bus_pci.h | 48 ++++++++++++++++++++++++++\n drivers/bus/pci/version.map | 3 ++\n 8 files changed, 192 insertions(+)", "diff": "diff --git a/doc/guides/rel_notes/release_23_07.rst b/doc/guides/rel_notes/release_23_07.rst\nindex a9b1293689..dba39134f1 100644\n--- a/doc/guides/rel_notes/release_23_07.rst\n+++ b/doc/guides/rel_notes/release_23_07.rst\n@@ -55,6 +55,11 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added MMIO read and write APIs to PCI bus.**\n+\n+ Introduced ``rte_pci_mmio_read()`` and ``rte_pci_mmio_write()`` APIs to PCI\n+ bus so that PCI drivers can access PCI memory resources when they are not\n+ mapped to process address space.\n \n Removed Items\n -------------\ndiff --git a/drivers/bus/pci/bsd/pci.c b/drivers/bus/pci/bsd/pci.c\nindex a747eca58c..27f12590d4 100644\n--- a/drivers/bus/pci/bsd/pci.c\n+++ b/drivers/bus/pci/bsd/pci.c\n@@ -489,6 +489,28 @@ int rte_pci_write_config(const struct rte_pci_device *dev,\n \treturn -1;\n }\n \n+/* Read PCI MMIO space. */\n+int rte_pci_mmio_read(const struct rte_pci_device *dev, int bar,\n+\t\t void *buf, size_t len, off_t offset)\n+{\n+\tif (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||\n+\t\t\t(uint64_t)offset + len > dev->mem_resource[bar].len)\n+\t\treturn -1;\n+\tmemcpy(buf, (uint8_t *)dev->mem_resource[bar].addr + offset, len);\n+\treturn len;\n+}\n+\n+/* Write PCI MMIO space. */\n+int rte_pci_mmio_write(const struct rte_pci_device *dev, int bar,\n+\t\t const void *buf, size_t len, off_t offset)\n+{\n+\tif (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||\n+\t\t\t(uint64_t)offset + len > dev->mem_resource[bar].len)\n+\t\treturn -1;\n+\tmemcpy((uint8_t *)dev->mem_resource[bar].addr + offset, buf, len);\n+\treturn len;\n+}\n+\n int\n rte_pci_ioport_map(struct rte_pci_device *dev, int bar,\n \t\tstruct rte_pci_ioport *p)\ndiff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c\nindex 04e21ae20f..3d237398d9 100644\n--- a/drivers/bus/pci/linux/pci.c\n+++ b/drivers/bus/pci/linux/pci.c\n@@ -680,6 +680,52 @@ int rte_pci_write_config(const struct rte_pci_device *device,\n \t}\n }\n \n+/* Read PCI MMIO space. */\n+int rte_pci_mmio_read(const struct rte_pci_device *device, int bar,\n+\t\tvoid *buf, size_t len, off_t offset)\n+{\n+\tchar devname[RTE_DEV_NAME_MAX_LEN] = \"\";\n+\n+\tswitch (device->kdrv) {\n+\tcase RTE_PCI_KDRV_IGB_UIO:\n+\tcase RTE_PCI_KDRV_UIO_GENERIC:\n+\t\treturn pci_uio_mmio_read(device, bar, buf, len, offset);\n+#ifdef VFIO_PRESENT\n+\tcase RTE_PCI_KDRV_VFIO:\n+\t\treturn pci_vfio_mmio_read(device, bar, buf, len, offset);\n+#endif\n+\tdefault:\n+\t\trte_pci_device_name(&device->addr, devname,\n+\t\t\t\t RTE_DEV_NAME_MAX_LEN);\n+\t\tRTE_LOG(ERR, EAL,\n+\t\t\t\"Unknown driver type for %s\\n\", devname);\n+\t\treturn -1;\n+\t}\n+}\n+\n+/* Write PCI MMIO space. */\n+int rte_pci_mmio_write(const struct rte_pci_device *device, int bar,\n+\t\tconst void *buf, size_t len, off_t offset)\n+{\n+\tchar devname[RTE_DEV_NAME_MAX_LEN] = \"\";\n+\n+\tswitch (device->kdrv) {\n+\tcase RTE_PCI_KDRV_IGB_UIO:\n+\tcase RTE_PCI_KDRV_UIO_GENERIC:\n+\t\treturn pci_uio_mmio_write(device, bar, buf, len, offset);\n+#ifdef VFIO_PRESENT\n+\tcase RTE_PCI_KDRV_VFIO:\n+\t\treturn pci_vfio_mmio_write(device, bar, buf, len, offset);\n+#endif\n+\tdefault:\n+\t\trte_pci_device_name(&device->addr, devname,\n+\t\t\t\t RTE_DEV_NAME_MAX_LEN);\n+\t\tRTE_LOG(ERR, EAL,\n+\t\t\t\"Unknown driver type for %s\\n\", devname);\n+\t\treturn -1;\n+\t}\n+}\n+\n int\n rte_pci_ioport_map(struct rte_pci_device *dev, int bar,\n \t\tstruct rte_pci_ioport *p)\ndiff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h\nindex 9f6659ba6e..d842809ccd 100644\n--- a/drivers/bus/pci/linux/pci_init.h\n+++ b/drivers/bus/pci/linux/pci_init.h\n@@ -37,6 +37,11 @@ int pci_uio_read_config(const struct rte_intr_handle *intr_handle,\n int pci_uio_write_config(const struct rte_intr_handle *intr_handle,\n \t\t\t const void *buf, size_t len, off_t offs);\n \n+int pci_uio_mmio_read(const struct rte_pci_device *dev, int bar,\n+\t\t\tvoid *buf, size_t len, off_t offset);\n+int pci_uio_mmio_write(const struct rte_pci_device *dev, int bar,\n+\t\t\tconst void *buf, size_t len, off_t offset);\n+\n int pci_uio_ioport_map(struct rte_pci_device *dev, int bar,\n \t\t struct rte_pci_ioport *p);\n void pci_uio_ioport_read(struct rte_pci_ioport *p,\n@@ -71,6 +76,11 @@ int pci_vfio_read_config(const struct rte_pci_device *dev,\n int pci_vfio_write_config(const struct rte_pci_device *dev,\n \t\t\t const void *buf, size_t len, off_t offs);\n \n+int pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar,\n+\t\t\tvoid *buf, size_t len, off_t offset);\n+int pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar,\n+\t\t\tconst void *buf, size_t len, off_t offset);\n+\n int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,\n \t\t struct rte_pci_ioport *p);\n void pci_vfio_ioport_read(struct rte_pci_ioport *p,\ndiff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c\nindex d52125e49b..2bf16e9369 100644\n--- a/drivers/bus/pci/linux/pci_uio.c\n+++ b/drivers/bus/pci/linux/pci_uio.c\n@@ -55,6 +55,28 @@ pci_uio_write_config(const struct rte_intr_handle *intr_handle,\n \treturn pwrite(uio_cfg_fd, buf, len, offset);\n }\n \n+int\n+pci_uio_mmio_read(const struct rte_pci_device *dev, int bar,\n+\t\t void *buf, size_t len, off_t offset)\n+{\n+\tif (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||\n+\t\t\t(uint64_t)offset + len > dev->mem_resource[bar].len)\n+\t\treturn -1;\n+\tmemcpy(buf, (uint8_t *)dev->mem_resource[bar].addr + offset, len);\n+\treturn len;\n+}\n+\n+int\n+pci_uio_mmio_write(const struct rte_pci_device *dev, int bar,\n+\t\t const void *buf, size_t len, off_t offset)\n+{\n+\tif (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||\n+\t\t\t(uint64_t)offset + len > dev->mem_resource[bar].len)\n+\t\treturn -1;\n+\tmemcpy((uint8_t *)dev->mem_resource[bar].addr + offset, buf, len);\n+\treturn len;\n+}\n+\n static int\n pci_uio_set_bus_master(int dev_fd)\n {\ndiff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex 5aef84b7d0..24b0795fbd 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -1258,6 +1258,42 @@ pci_vfio_ioport_unmap(struct rte_pci_ioport *p)\n \treturn -1;\n }\n \n+int\n+pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar,\n+\t\t void *buf, size_t len, off_t offs)\n+{\n+\tuint64_t size, offset;\n+\tint fd;\n+\n+\tfd = rte_intr_dev_fd_get(dev->intr_handle);\n+\n+\tif (pci_vfio_get_region(dev, bar, &size, &offset) != 0)\n+\t\treturn -1;\n+\n+\tif ((uint64_t)len + offs > size)\n+\t\treturn -1;\n+\n+\treturn pread64(fd, buf, len, offset + offs);\n+}\n+\n+int\n+pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar,\n+\t\t const void *buf, size_t len, off_t offs)\n+{\n+\tuint64_t size, offset;\n+\tint fd;\n+\n+\tfd = rte_intr_dev_fd_get(dev->intr_handle);\n+\n+\tif (pci_vfio_get_region(dev, bar, &size, &offset) != 0)\n+\t\treturn -1;\n+\n+\tif ((uint64_t)len + offs > size)\n+\t\treturn -1;\n+\n+\treturn pwrite64(fd, buf, len, offset + offs);\n+}\n+\n int\n pci_vfio_is_enabled(void)\n {\ndiff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h\nindex b193114fe5..82da087f24 100644\n--- a/drivers/bus/pci/rte_bus_pci.h\n+++ b/drivers/bus/pci/rte_bus_pci.h\n@@ -135,6 +135,54 @@ int rte_pci_read_config(const struct rte_pci_device *device,\n int rte_pci_write_config(const struct rte_pci_device *device,\n \t\tconst void *buf, size_t len, off_t offset);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ *\n+ * Read from a MMIO pci resource.\n+ *\n+ * @param device\n+ * A pointer to a rte_pci_device structure describing the device\n+ * to use\n+ * @param bar\n+ * Index of the io pci resource we want to access.\n+ * @param buf\n+ * A data buffer where the bytes should be read into\n+ * @param len\n+ * The length of the data buffer.\n+ * @param offset\n+ * The offset into MMIO space described by @bar\n+ * @return\n+ * Number of bytes read on success, negative on error.\n+ */\n+__rte_experimental\n+int rte_pci_mmio_read(const struct rte_pci_device *device, int bar,\n+\t\tvoid *buf, size_t len, off_t offset);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ *\n+ * Write to a MMIO pci resource.\n+ *\n+ * @param device\n+ * A pointer to a rte_pci_device structure describing the device\n+ * to use\n+ * @param bar\n+ * Index of the io pci resource we want to access.\n+ * @param buf\n+ * A data buffer containing the bytes should be written\n+ * @param len\n+ * The length of the data buffer.\n+ * @param offset\n+ * The offset into MMIO space described by @bar\n+ * @return\n+ * Number of bytes written on success, negative on error.\n+ */\n+__rte_experimental\n+int rte_pci_mmio_write(const struct rte_pci_device *device, int bar,\n+\t\tconst void *buf, size_t len, off_t offset);\n+\n /**\n * Initialize a rte_pci_ioport object for a pci device io resource.\n *\ndiff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map\nindex 161ab86d3b..00fde139ca 100644\n--- a/drivers/bus/pci/version.map\n+++ b/drivers/bus/pci/version.map\n@@ -21,6 +21,9 @@ EXPERIMENTAL {\n \n \t# added in 21.08\n \trte_pci_set_bus_master;\n+\t# added in 23.07\n+\trte_pci_mmio_read;\n+\trte_pci_mmio_write;\n };\n \n INTERNAL {\n", "prefixes": [ "v4", "3/4" ] }