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GET /api/patches/127429/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 127429,
    "url": "http://patches.dpdk.org/api/patches/127429/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-23-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230525095904.3967080-23-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230525095904.3967080-23-ndabilpuram@marvell.com",
    "date": "2023-05-25T09:58:55",
    "name": "[v3,23/32] net/cnxk: support for inbound without inline dev mode",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "038e0986672f4a65a48fc5037ddfbb48b57b4497",
    "submitter": {
        "id": 1202,
        "url": "http://patches.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-23-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 28180,
            "url": "http://patches.dpdk.org/api/series/28180/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28180",
            "date": "2023-05-25T09:58:36",
            "name": "[v3,01/32] common/cnxk: allocate dynamic BPIDs",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/28180/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/127429/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/127429/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2AA4340FAE;\n\tThu, 25 May 2023 12:37:45 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EDCAD40FAE\n for <dev@dpdk.org>; Thu, 25 May 2023 12:37:42 +0200 (CEST)",
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            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qt5jng41g-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 25 May 2023 03:37:41 -0700",
            "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 25 May 2023 03:37:39 -0700",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 25 May 2023 03:37:39 -0700",
            "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id BC8C95B694F;\n Thu, 25 May 2023 03:00:25 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=06m5qER3c3zLamXLRYCXJebgmX0o61Y3culNhGpHFVI=;\n b=RirXa3UyMRb74HjpVvHPbZ790tYhmzxO8WthdyCC3LfeWolSpyXiBTTuu9BR/FcBV+s+\n KsnWFqZM60kFBAKh5tOMbHBNLpU7qRQ26xaT/Wfnh244pvlsuXi2k+JUe7CpzK8Y8QUy\n Y97Pu5sItw5+fDJynrHQPZw5LTjStR5XnSIu/fT1GnqoF2AfhHvaml/k8MNipBGvA4rb\n dkPdKPYVMVTR16DfOxmjNUcLk3vjrqNDfenMzt/ZIFjeMRxb/Icc9756EXHnqnrRdNL6\n HUbjzhQ7+CPlqsbhLYwoSbPosGyIkWCU9zTQxiPrizbNjr9ytAsVobtV3mvZSDRBhGPC cw==",
        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>",
        "CC": "<jerinj@marvell.com>, <dev@dpdk.org>",
        "Subject": "[PATCH v3 23/32] net/cnxk: support for inbound without inline dev\n mode",
        "Date": "Thu, 25 May 2023 15:28:55 +0530",
        "Message-ID": "<20230525095904.3967080-23-ndabilpuram@marvell.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230525095904.3967080-1-ndabilpuram@marvell.com>",
        "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>\n <20230525095904.3967080-1-ndabilpuram@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-ORIG-GUID": "BCpc0P_teO8HxZPc4k74XtHTu7XA15YX",
        "X-Proofpoint-GUID": "BCpc0P_teO8HxZPc4k74XtHTu7XA15YX",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Support for inbound Inline IPsec without Inline device\nRQ i.e both first pass and second pass hitting same\nethdev RQ in poll mode. Remove the switching from\ninline dev to non inline dev mode as inline dev mode\nis default and can only be overridden by devargs.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_queue.c      |  3 +++\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 15 ---------------\n drivers/net/cnxk/cnxk_ethdev.c           | 15 ++++++++++-----\n 3 files changed, 13 insertions(+), 20 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex d29fafa895..08e8bf7ea2 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -473,6 +473,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \tif (rq->ipsech_ena) {\n \t\taq->rq.ipsech_ena = 1;\n \t\taq->rq.ipsecd_drop_en = 1;\n+\t\taq->rq.ena_wqwd = 1;\n+\t\taq->rq.wqe_skip = rq->wqe_skip;\n+\t\taq->rq.wqe_caching = 1;\n \t}\n \n \taq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle);\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex 8ad84198b9..92aea92389 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -273,15 +273,6 @@ cnxk_sso_rx_adapter_queue_add(\n \t}\n \n \tdev->rx_offloads |= cnxk_eth_dev->rx_offload_flags;\n-\n-\t/* Switch to use PF/VF's NIX LF instead of inline device for inbound\n-\t * when all the RQ's are switched to event dev mode. We do this only\n-\t * when dev arg no_inl_dev=1 is selected.\n-\t */\n-\tif (cnxk_eth_dev->inb.no_inl_dev &&\n-\t    cnxk_eth_dev->nb_rxq_sso == cnxk_eth_dev->nb_rxq)\n-\t\tcnxk_nix_inb_mode_set(cnxk_eth_dev, false);\n-\n \treturn 0;\n }\n \n@@ -309,12 +300,6 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \tif (rc < 0)\n \t\tplt_err(\"Failed to clear Rx adapter config port=%d, q=%d\",\n \t\t\teth_dev->data->port_id, rx_queue_id);\n-\n-\t/* Removing RQ from Rx adapter implies need to use\n-\t * inline device for CQ/Poll mode.\n-\t */\n-\tcnxk_nix_inb_mode_set(cnxk_eth_dev, true);\n-\n \treturn rc;\n }\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex aaa1014479..916198d802 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -81,9 +81,6 @@ cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)\n {\n \tstruct roc_nix *nix = &dev->nix;\n \n-\tif (dev->inb.inl_dev == use_inl_dev)\n-\t\treturn 0;\n-\n \tplt_nix_dbg(\"Security sessions(%u) still active, inl=%u!!!\",\n \t\t    dev->inb.nb_sess, !!dev->inb.inl_dev);\n \n@@ -119,7 +116,7 @@ nix_security_setup(struct cnxk_eth_dev *dev)\n \t\t/* By default pick using inline device for poll mode.\n \t\t * Will be overridden when event mode rq's are setup.\n \t\t */\n-\t\tcnxk_nix_inb_mode_set(dev, true);\n+\t\tcnxk_nix_inb_mode_set(dev, !dev->inb.no_inl_dev);\n \n \t\t/* Allocate memory to be used as dptr for CPT ucode\n \t\t * WRITE_SA op.\n@@ -633,6 +630,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tstruct roc_nix_rq *rq;\n \tstruct roc_nix_cq *cq;\n \tuint16_t first_skip;\n+\tuint16_t wqe_skip;\n \tint rc = -EINVAL;\n \tsize_t rxq_sz;\n \tstruct rte_mempool *lpb_pool = mp;\n@@ -712,8 +710,15 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n \n \t/* Enable Inline IPSec on RQ, will not be used for Poll mode */\n-\tif (roc_nix_inl_inb_is_enabled(nix))\n+\tif (roc_nix_inl_inb_is_enabled(nix) && !dev->inb.inl_dev) {\n \t\trq->ipsech_ena = true;\n+\t\t/* WQE skip is needed when poll mode is enabled in CN10KA_B0 and above\n+\t\t * for Inline IPsec traffic to CQ without inline device.\n+\t\t */\n+\t\twqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ);\n+\t\twqe_skip = wqe_skip / ROC_CACHE_LINE_SZ;\n+\t\trq->wqe_skip = wqe_skip;\n+\t}\n \n \tif (spb_pool) {\n \t\trq->spb_ena = 1;\n",
    "prefixes": [
        "v3",
        "23/32"
    ]
}