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GET /api/patches/127426/?format=api
{ "id": 127426, "url": "http://patches.dpdk.org/api/patches/127426/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-8-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230525095904.3967080-8-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230525095904.3967080-8-ndabilpuram@marvell.com", "date": "2023-05-25T09:58:40", "name": "[v3,08/32] common/cnxk: make aura flow control config more predictable", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3d9ccc6bc3ffda08f2ed6a25571cd14c43b372c6", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-8-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 28180, "url": "http://patches.dpdk.org/api/series/28180/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28180", "date": "2023-05-25T09:58:36", "name": "[v3,01/32] common/cnxk: allocate dynamic BPIDs", "version": 3, "mbox": "http://patches.dpdk.org/series/28180/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/127426/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/127426/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81FA142B9A;\n\tThu, 25 May 2023 12:37:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 920EE42D52;\n\tThu, 25 May 2023 12:37:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id DF6FF42D38\n for <dev@dpdk.org>; Thu, 25 May 2023 12:37:14 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 34P9Il3A025637 for <dev@dpdk.org>; Thu, 25 May 2023 03:37:14 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3qsspt2cm7-8\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 25 May 2023 03:37:13 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 25 May 2023 03:37:12 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 25 May 2023 03:37:12 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 8C3675B6BAF;\n Thu, 25 May 2023 02:59:41 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=E0GNLvc0t3enTAwrMf4NSvqhzwYsTAssiv6ZcfLIttg=;\n b=Qy8L904kwi5CbMt2M2/xbkeZzhXAOVIEBLAmXXmIahz2NSuyk+PxIfYWOEN/XOY2rIkv\n oFOj3ctvlg8fxW4+Gyac9eD3VYiKPtM87v6VKNIhzW4uk+4qkcgnTFoo6iJ3NcCCSFqF\n pQZve1RLnjGz9LDj//tsEJv+gm0yjhn7HRd9BNQoyYg6JjYNE0i3I35lTrDAZonUwU5t\n ATCvu1D6lL3RYZz5AzIjC6oucdEt1ZOlTB9M/qkvs1+jbOXrR2hAxyz6ZzNhJZNkbwyH\n Ip/P9qHECeImBcyOfrHd6/j7Mi9MRe54fB+fluG9ckxqPjleyRXc/TkUyKUdl5tpxev2 BA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 08/32] common/cnxk: make aura flow control config more\n predictable", "Date": "Thu, 25 May 2023 15:28:40 +0530", "Message-ID": "<20230525095904.3967080-8-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230525095904.3967080-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>\n <20230525095904.3967080-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "2oIGKFAg3S2NnWt7UwvhAzvXJKNWE6g0", "X-Proofpoint-ORIG-GUID": "2oIGKFAg3S2NnWt7UwvhAzvXJKNWE6g0", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Restrict shared BPID config only when force BP is enabled\nand make aura flow control config more predictable by not disabling\nit if there is a collision but ignore new config and log the same.\n\nAlso remove BPID setup from Rx adapter as it is now evaluated and\nconfigured every time ethdev is stopped/started.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_fc.c | 49 ++++++++++++------------\n drivers/common/cnxk/roc_nix_inl.c | 2 +-\n drivers/common/cnxk/roc_npa.c | 3 ++\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 13 +------\n 5 files changed, 32 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex fde8fe4ecc..2b576f0891 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -451,6 +451,7 @@ struct roc_nix {\n \tbool custom_sa_action;\n \tbool local_meta_aura_ena;\n \tuint32_t meta_buf_sz;\n+\tbool force_rx_aura_bp;\n \t/* End of input parameters */\n \t/* LMT line base for \"Per Core Tx LMT line\" mode*/\n \tuintptr_t lmt_base;\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 78f482ea52..21e3b7d5bd 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -300,13 +300,13 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\t\tpool_drop_pct = ROC_NIX_AURA_THRESH;\n \n \t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool,\n-\t\t\t\t fc_cfg->rq_cfg.enable, true,\n-\t\t\t\t fc_cfg->rq_cfg.tc, fc_cfg->rq_cfg.pool_drop_pct);\n+\t\t\t\t fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n+\t\t\t\t fc_cfg->rq_cfg.tc, pool_drop_pct);\n \n \t\tif (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle,\n-\t\t\t\t\t fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc,\n-\t\t\t\t\t fc_cfg->rq_cfg.pool_drop_pct);\n+\t\t\t\t\t fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n+\t\t\t\t\t fc_cfg->rq_cfg.tc, pool_drop_pct);\n \t}\n \n \t/* Copy RQ config to CQ config as they are occupying same area */\n@@ -479,7 +479,8 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \tstruct npa_aq_enq_rsp *rsp;\n \tuint8_t bp_thresh, bp_intf;\n \tstruct mbox *mbox;\n-\tint rc;\n+\tuint16_t bpid;\n+\tint rc, i;\n \n \tif (roc_nix_is_sdp(roc_nix))\n \t\treturn;\n@@ -508,34 +509,25 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \tbp_intf = 1 << nix->is_nix1;\n \tbp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift);\n \n+\tbpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;\n \t/* BP is already enabled. */\n \tif (rsp->aura.bp_ena && ena) {\n-\t\tuint16_t bpid =\n-\t\t\t(rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;\n-\n \t\t/* Disable BP if BPIDs don't match and couldn't add new BPID. */\n \t\tif (bpid != nix->bpid[tc]) {\n \t\t\tuint16_t bpid_new = NIX_BPID_INVALID;\n \n-\t\t\tif ((nix_rx_chan_multi_bpid_cfg(roc_nix, tc, bpid, &bpid_new) < 0) &&\n-\t\t\t !force) {\n-\t\t\t\tplt_info(\"Disabling BP/FC on aura 0x%\" PRIx64\n-\t\t\t\t\t \" as it shared across ports or tc\",\n+\t\t\tif (force && !nix_rx_chan_multi_bpid_cfg(roc_nix, tc, bpid, &bpid_new)) {\n+\t\t\t\tplt_info(\"Setting up shared BPID on shared aura 0x%\" PRIx64,\n \t\t\t\t\t pool_id);\n \n-\t\t\t\tif (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))\n-\t\t\t\t\tplt_nix_dbg(\n-\t\t\t\t\t\t\"Disabling backpressue failed on aura 0x%\" PRIx64,\n-\t\t\t\t\t\tpool_id);\n-\t\t\t}\n-\n-\t\t\t/* Configure Aura with new BPID if it is allocated. */\n-\t\t\tif (bpid_new != NIX_BPID_INVALID) {\n+\t\t\t\t/* Configure Aura with new BPID if it is allocated. */\n \t\t\t\tif (roc_npa_aura_bp_configure(pool_id, bpid_new, bp_intf, bp_thresh,\n \t\t\t\t\t\t\t true))\n-\t\t\t\t\tplt_nix_dbg(\n-\t\t\t\t\t\t\"Enabling backpressue failed on aura 0x%\" PRIx64,\n+\t\t\t\t\tplt_err(\"Enabling backpressue failed on aura 0x%\" PRIx64,\n \t\t\t\t\t\tpool_id);\n+\t\t\t} else {\n+\t\t\t\tplt_info(\"Ignoring port=%u tc=%u config on shared aura 0x%\" PRIx64,\n+\t\t\t\t\t roc_nix->port_id, tc, pool_id);\n \t\t\t}\n \t\t}\n \n@@ -548,10 +540,19 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \n \tif (ena) {\n \t\tif (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))\n-\t\t\tplt_nix_dbg(\"Enabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n+\t\t\tplt_err(\"Enabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n \t} else {\n+\t\tbool found = !!force;\n+\n+\t\t/* Don't disable if existing BPID is not within this port's list */\n+\t\tfor (i = 0; i < nix->chan_cnt; i++)\n+\t\t\tif (bpid == nix->bpid[i])\n+\t\t\t\tfound = true;\n+\t\tif (!found)\n+\t\t\treturn;\n+\n \t\tif (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))\n-\t\t\tplt_nix_dbg(\"Disabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n+\t\t\tplt_err(\"Disabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n \t}\n \n \treturn;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 329ebf9405..8592e1cb0b 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -263,7 +263,7 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n \t\t */\n \t\tif (aura_setup && nix->rqs[0] && nix->rqs[0]->tc != ROC_NIX_PFC_CLASS_INVALID)\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle,\n-\t\t\t\t\t true, true, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH);\n+\t\t\t\t\t true, false, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH);\n \t} else {\n \t\trc = nix_inl_global_meta_buffer_validate(idev, rq);\n \t\tif (rc)\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex dd649812b4..377439c2ba 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -892,6 +892,9 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf,\n \tstruct mbox *mbox;\n \tint rc = 0;\n \n+\tplt_npa_dbg(\"Setting BPID %u BP_INTF 0x%x BP_THRESH %u enable %u on aura %\" PRIx64,\n+\t\t bpid, bp_intf, bp_thresh, enable, aura_handle);\n+\n \tif (lf == NULL)\n \t\treturn NPA_ERR_PARAM;\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex d39bed6e84..8ad84198b9 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -260,10 +260,8 @@ cnxk_sso_rx_adapter_queue_add(\n \t\t\t\t\t\t\t false);\n \t\t}\n \n-\t\tif (rxq_sp->tx_pause)\n-\t\t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n-\t\t\t\t\t rxq_sp->qconf.mp->pool_id, true,\n-\t\t\t\t\t dev->force_ena_bp, rxq_sp->tc, ROC_NIX_AURA_THRESH);\n+\t\t/* Propagate force bp devarg */\n+\t\tcnxk_eth_dev->nix.force_rx_aura_bp = dev->force_ena_bp;\n \t\tcnxk_sso_tstamp_cfg(eth_dev->data->port_id, cnxk_eth_dev, dev);\n \t\tcnxk_eth_dev->nb_rxq_sso++;\n \t}\n@@ -293,8 +291,6 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \t\t\t int32_t rx_queue_id)\n {\n \tstruct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;\n-\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n-\tstruct cnxk_eth_rxq_sp *rxq_sp;\n \tint i, rc = 0;\n \n \tRTE_SET_USED(event_dev);\n@@ -302,12 +298,7 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \t\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++)\n \t\t\tcnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, i);\n \t} else {\n-\t\trxq_sp = cnxk_eth_rxq_to_sp(\n-\t\t\teth_dev->data->rx_queues[rx_queue_id]);\n \t\trc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id);\n-\t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n-\t\t\t\t rxq_sp->qconf.mp->pool_id, false,\n-\t\t\t\t dev->force_ena_bp, 0, ROC_NIX_AURA_THRESH);\n \t\tcnxk_eth_dev->nb_rxq_sso--;\n \n \t\t/* Enable drop_re if it was disabled earlier */\n", "prefixes": [ "v3", "08/32" ] }