Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 127233,
    "url": "http://patches.dpdk.org/api/patches/127233/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230523184818.139353-7-hernan.vargas@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230523184818.139353-7-hernan.vargas@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230523184818.139353-7-hernan.vargas@intel.com",
    "date": "2023-05-23T18:48:18",
    "name": "[v1,6/6] baseband/fpga_5gnr_fec: cosmetic comment changes",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b8e10ec221d962dd78f3b4347e377ddc71cdd394",
    "submitter": {
        "id": 2659,
        "url": "http://patches.dpdk.org/api/people/2659/?format=api",
        "name": "Hernan Vargas",
        "email": "hernan.vargas@intel.com"
    },
    "delegate": {
        "id": 2642,
        "url": "http://patches.dpdk.org/api/users/2642/?format=api",
        "username": "mcoquelin",
        "first_name": "Maxime",
        "last_name": "Coquelin",
        "email": "maxime.coquelin@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230523184818.139353-7-hernan.vargas@intel.com/mbox/",
    "series": [
        {
            "id": 28139,
            "url": "http://patches.dpdk.org/api/series/28139/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28139",
            "date": "2023-05-23T18:48:12",
            "name": "baseband/fpga_5gnr_fec: changes for 23.07",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/28139/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/127233/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/127233/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 241A242B83;\n\tTue, 23 May 2023 20:50:11 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 20AA242D51;\n\tTue, 23 May 2023 20:49:37 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 91CAE42D17\n for <dev@dpdk.org>; Tue, 23 May 2023 20:49:31 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2023 11:49:30 -0700",
            "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by orsmga005.jf.intel.com with ESMTP; 23 May 2023 11:49:29 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684867771; x=1716403771;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=00M1ThAjWbOoFMSJF8OUVTmW50ZaZKAbY4G3wssVfpA=;\n b=cwUX/ofbruUUPCK+HByAU7p4KijJm2a7y3GNH1X5srLI/wo6vws38lhH\n SEUdV/lRWX+9EpIDCQmFPC34JQIhBUi7BHU1YNkUUCCk7SI7Vpd/M1B7F\n K7fhYmL/susZH8sWHbpzTYGvG/H+6YxJ6xIqNvtvdLpScfIUtlnLIsIuA\n 01pIGmqVgbLpD6VJzS4JC4so0Dh9CTajT6mECedRaZRKp+wW5LJkQ8N4e\n Iq6D8ZWAhUs3TPS5kZIs8mMmALPs4fAmWBGiFjI3r8YPA3seRHthJp7vc\n J9Xl0C/uX+rLdh1d8irN6DH30TnoDwG0Va/CQnWS6QiGKD9NPKCOWVfld g==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10719\"; a=\"439677959\"",
            "E=Sophos;i=\"6.00,187,1681196400\"; d=\"scan'208\";a=\"439677959\"",
            "E=McAfee;i=\"6600,9927,10719\"; a=\"878317366\"",
            "E=Sophos;i=\"6.00,187,1681196400\"; d=\"scan'208\";a=\"878317366\""
        ],
        "X-ExtLoop1": "1",
        "From": "Hernan Vargas <hernan.vargas@intel.com>",
        "To": "dev@dpdk.org, maxime.coquelin@redhat.com, gakhil@marvell.com,\n trix@redhat.com",
        "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>",
        "Subject": "[PATCH v1 6/6] baseband/fpga_5gnr_fec: cosmetic comment changes",
        "Date": "Tue, 23 May 2023 11:48:18 -0700",
        "Message-Id": "<20230523184818.139353-7-hernan.vargas@intel.com>",
        "X-Mailer": "git-send-email 2.37.1",
        "In-Reply-To": "<20230523184818.139353-1-hernan.vargas@intel.com>",
        "References": "<20230523184818.139353-1-hernan.vargas@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Cosmetic changes for comments.\nNo functional impact.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h    |  93 ++--\n .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c         | 398 +++++++++---------\n .../fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h     |  16 +-\n 3 files changed, 252 insertions(+), 255 deletions(-)",
    "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex d0d9ee64dbde..c2aa5af2af40 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -11,7 +11,7 @@\n #include \"agx100_pmd.h\"\n #include \"vc_5gnr_pmd.h\"\n \n-/* Helper macro for logging */\n+/* Helper macro for logging. */\n #define rte_bbdev_log(level, fmt, ...) \\\n \trte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt \"\\n\", \\\n \t\t##__VA_ARGS__)\n@@ -24,7 +24,7 @@\n #define rte_bbdev_log_debug(fmt, ...)\n #endif\n \n-/* FPGA 5GNR FEC driver names */\n+/* FPGA 5GNR FEC driver names. */\n #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf\n #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf\n \n@@ -43,15 +43,15 @@\n #define VC_5GNR_FPGA_VARIANT\t0\n #define AGX100_FPGA_VARIANT\t1\n \n-/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */\n-#define N_ZC_1 66 /* N = 66 Zc for BG 1 */\n-#define N_ZC_2 50 /* N = 50 Zc for BG 2 */\n-#define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */\n-#define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */\n-#define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */\n-#define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */\n-#define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */\n-#define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */\n+/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2. */\n+#define N_ZC_1 66 /**< N = 66 Zc for BG 1. */\n+#define N_ZC_2 50 /**< N = 50 Zc for BG 2. */\n+#define K0_1_1 17 /**< K0 fraction numerator for rv 1 and BG 1. */\n+#define K0_1_2 13 /**< K0 fraction numerator for rv 1 and BG 2. */\n+#define K0_2_1 33 /**< K0 fraction numerator for rv 2 and BG 1. */\n+#define K0_2_2 25 /**< K0 fraction numerator for rv 2 and BG 2. */\n+#define K0_3_1 56 /**< K0 fraction numerator for rv 3 and BG 1. */\n+#define K0_3_2 43 /**< K0 fraction numerator for rv 3 and BG 2. */\n \n /* FPGA 5GNR Ring Control Registers. */\n enum {\n@@ -66,25 +66,25 @@ enum {\n \n /* VC 5GNR and AGX100 common register mapping on BAR0. */\n enum {\n-\tFPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B */\n-\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B */\n-\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B */\n-\tFPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B */\n-\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B */\n-\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B */\n-\tFPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B */\n-\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B */\n-\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B */\n-\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B */\n-\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B */\n-\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B */\n-\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B */\n-\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B */\n-\tFPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B */\n-\tFPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68  /**< len: 4B */\n+\tFPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */\n+\tFPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */\n+\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68  /**< len: 4B. */\n };\n \n /* FPGA 5GNR Ring Control Register. */\n@@ -93,7 +93,7 @@ struct __rte_packed fpga_5gnr_ring_ctrl_reg {\n \tuint64_t ring_head_addr;\n \tuint16_t ring_size:11;\n \tuint16_t rsrvd0;\n-\tunion { /* Miscellaneous register */\n+\tunion { /* Miscellaneous register. */\n \t\tuint8_t misc;\n \t\tuint8_t max_ul_dec:5,\n \t\t\tmax_ul_dec_en:1,\n@@ -132,30 +132,27 @@ struct fpga_5gnr_fec_device {\n \tuint64_t q_assigned_bit_map;\n \t/** True if this is a PF FPGA 5GNR device. */\n \tbool pf_device;\n-\t/** Maximum number of possible queues for this device */\n+\t/** Maximum number of possible queues for this device. */\n \tuint8_t total_num_queues;\n-\t/** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1 */\n+\t/** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1. */\n \tuint8_t fpga_variant;\n };\n \n /** Structure associated with each queue. */\n struct __rte_cache_aligned fpga_5gnr_queue {\n-\tstruct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg;  /**< Ring Control Register */\n+\tstruct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg;  /**< Ring Control Register. */\n \tunion vc_5gnr_dma_desc *vc_5gnr_ring_addr; /**< Virtual address of VC 5GNR software ring. */\n-\tunion agx100_dma_desc *agx100_ring_addr;  /**< Virtual address of AGX100 software ring */\n-\tuint64_t *ring_head_addr;  /* Virtual address of completion_head */\n-\tuint64_t shadow_completion_head; /* Shadow completion head value */\n-\tuint16_t head_free_desc;  /* Ring head */\n-\tuint16_t tail;  /* Ring tail */\n-\t/* Mask used to wrap enqueued descriptors on the sw ring */\n-\tuint32_t sw_ring_wrap_mask;\n-\tuint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */\n-\tuint8_t q_idx;  /* Queue index */\n-\t/** uuid used for MUTEX acquision for DDR */\n-\tuint16_t ddr_mutex_uuid;\n-\tstruct fpga_5gnr_fec_device *d;\n-\t/* MMIO register of shadow_tail used to enqueue descriptors */\n-\tvoid *shadow_tail_addr;\n+\tunion agx100_dma_desc *agx100_ring_addr;  /**< Virtual address of AGX100 software ring. */\n+\tuint64_t *ring_head_addr;  /**< Virtual address of completion_head. */\n+\tuint64_t shadow_completion_head; /**< Shadow completion head value. */\n+\tuint16_t head_free_desc;  /**< Ring head. */\n+\tuint16_t tail;  /**< Ring tail. */\n+\tuint32_t sw_ring_wrap_mask; /**< Mask used to wrap enqueued descriptors on the sw ring. */\n+\tuint32_t irq_enable;  /**< Enable ops dequeue interrupts if set to 1. */\n+\tuint8_t q_idx;  /**< Queue index. */\n+\tuint16_t ddr_mutex_uuid; /**< uuid used for MUTEX acquision for DDR. */\n+\tstruct fpga_5gnr_fec_device *d; /**< FPGA 5GNR device structure. */\n+\tvoid *shadow_tail_addr; /**< MMIO register of shadow_tail used to enqueue descriptors. */\n };\n \n /* Write to 16 bit MMIO register address. */\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex a2ce859f5d4b..68e4223d7954 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -29,7 +29,7 @@ RTE_LOG_REGISTER_DEFAULT(fpga_5gnr_fec_logtype, NOTICE);\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \n-/* Read Ring Control Register of FPGA 5GNR FEC device */\n+/* Read Ring Control Register of FPGA 5GNR FEC device. */\n static inline void\n print_ring_reg_debug_info(void *mmio_base, uint32_t offset)\n {\n@@ -149,7 +149,7 @@ vc_5gnr_print_dma_dec_desc_debug_info(union vc_5gnr_dma_desc *desc)\n \t\t\tword[4], word[5], word[6], word[7]);\n }\n \n-/* Print decode DMA Descriptor of AGX100 Decoder device */\n+/* Print decode DMA Descriptor of AGX100 Decoder device. */\n static void\n agx100_print_dma_dec_desc_debug_info(union agx100_dma_desc *desc)\n {\n@@ -251,7 +251,7 @@ agx100_print_dma_dec_desc_debug_info(union agx100_dma_desc *desc)\n \t\t\tword[12], word[13], word[14], word[15]);\n }\n \n-/* Print decode DMA Descriptor of Vista Creek encoder device */\n+/* Print decode DMA Descriptor of Vista Creek encoder device. */\n static void\n vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc)\n {\n@@ -284,7 +284,7 @@ vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc)\n \t\t\tword[4], word[5], word[6], word[7]);\n }\n \n-/* Print decode DMA Descriptor of AGX100 encoder device */\n+/* Print decode DMA Descriptor of AGX100 encoder device. */\n static void\n agx100_print_dma_enc_desc_debug_info(union agx100_dma_desc *desc)\n {\n@@ -370,7 +370,7 @@ agx100_print_dma_enc_desc_debug_info(union agx100_dma_desc *desc)\n static int\n fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n {\n-\t/* Number of queues bound to a PF/VF */\n+\t/* Number of queues bound to a PF/VF. */\n \tuint32_t hw_q_num = 0;\n \tuint32_t ring_size, payload, address, q_id, offset;\n \trte_iova_t phys_addr;\n@@ -385,11 +385,11 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t\treturn -EPERM;\n \t}\n \n-\t/* Clear queue registers structure */\n+\t/* Clear queue registers structure. */\n \tmemset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg));\n \n \tif (d->fpga_variant == AGX100_FPGA_VARIANT) {\n-\t\t/* Maximum number of queues possible for this device */\n+\t\t/* Maximum number of queues possible for this device. */\n \t\td->total_num_queues = fpga_5gnr_reg_read_32(\n \t\t\t\td->mmio_base,\n \t\t\t\tFPGA_5GNR_FEC_VERSION_ID) >> 24;\n@@ -420,7 +420,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \n \t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) {\n \t\t\td->q_bound_bit_map |= (1ULL << q_id);\n-\t\t\t/* Clear queue register of found queue */\n+\t\t\t/* Clear queue register of found queue. */\n \t\t\toffset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n \t\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_id);\n \t\t\tfpga_ring_reg_write(d->mmio_base, offset, ring_reg);\n@@ -444,10 +444,10 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \telse\n \t\tring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct agx100_dma_dec_desc);\n \n-\t/* Enforce 32 byte alignment */\n+\t/* Enforce 32 byte alignment. */\n \tRTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);\n \n-\t/* Allocate memory for SW descriptor rings */\n+\t/* Allocate memory for SW descriptor rings. */\n \td->sw_rings = rte_zmalloc_socket(dev->device->driver->name,\n \t\t\tnum_queues * ring_size, RTE_CACHE_LINE_SIZE,\n \t\t\tsocket_id);\n@@ -462,7 +462,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \td->sw_ring_size = ring_size;\n \td->sw_ring_max_depth = FPGA_5GNR_RING_MAX_SIZE;\n \n-\t/* Allocate memory for ring flush status */\n+\t/* Allocate memory for ring flush status. */\n \td->flush_queue_status = rte_zmalloc_socket(NULL,\n \t\t\tsizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);\n \tif (d->flush_queue_status == NULL) {\n@@ -472,7 +472,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t\treturn -ENOMEM;\n \t}\n \n-\t/* Set the flush status address registers */\n+\t/* Set the flush status address registers. */\n \tphys_addr = rte_malloc_virt2iova(d->flush_queue_status);\n \n \taddress = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW;\n@@ -543,7 +543,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_\n \t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n \t};\n \n-\t/* Check the HARQ DDR size available */\n+\t/* Check the HARQ DDR size available (in MB). */\n \tuint8_t timeout_counter = 0;\n \tuint32_t harq_buf_ready = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);\n@@ -578,7 +578,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_\n \tdev_info->data_endianness = RTE_LITTLE_ENDIAN;\n \tdev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED;\n \n-\t/* Calculates number of queues assigned to device */\n+\t/* Calculates number of queues assigned to device. */\n \tdev_info->max_num_queues = 0;\n \tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\tuint32_t hw_q_id;\n@@ -591,7 +591,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_\n \t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID)\n \t\t\tdev_info->max_num_queues++;\n \t}\n-\t/* Expose number of queue per operation type */\n+\t/* Expose number of queue per operation type. */\n \tdev_info->num_queues[RTE_BBDEV_OP_NONE] = 0;\n \tdev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0;\n \tdev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0;\n@@ -621,9 +621,9 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev,\n \n \tfor (; i < range; ++i) {\n \t\tq_idx = 1ULL << i;\n-\t\t/* Check if index of queue is bound to current PF/VF */\n+\t\t/* Check if index of queue is bound to current PF/VF. */\n \t\tif (d->q_bound_bit_map & q_idx)\n-\t\t\t/* Check if found queue was not already assigned */\n+\t\t\t/* Check if found queue was not already assigned. */\n \t\t\tif (!(d->q_assigned_bit_map & q_idx)) {\n \t\t\t\td->q_assigned_bit_map |= q_idx;\n \t\t\t\treturn i;\n@@ -644,7 +644,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tstruct fpga_5gnr_queue *q;\n \tint8_t q_idx;\n \n-\t/* Check if there is a free queue to assign */\n+\t/* Check if there is a free queue to assign. */\n \tq_idx = fpga_5gnr_find_free_queue_idx(dev, conf);\n \tif (q_idx == -1)\n \t\treturn -1;\n@@ -653,7 +653,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tq = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),\n \t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n \tif (q == NULL) {\n-\t\t/* Mark queue as un-assigned */\n+\t\t/* Mark queue as un-assigned. */\n \t\td->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));\n \t\trte_bbdev_log(ERR, \"Failed to allocate queue memory\");\n \t\treturn -ENOMEM;\n@@ -662,7 +662,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tq->d = d;\n \tq->q_idx = q_idx;\n \n-\t/* Set ring_base_addr */\n+\t/* Set ring_base_addr. */\n \tif (d->fpga_variant == VC_5GNR_FPGA_VARIANT)\n \t\tq->vc_5gnr_ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));\n \telse\n@@ -670,11 +670,11 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \n \tq->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + (d->sw_ring_size * queue_id);\n \n-\t/* Allocate memory for Completion Head variable*/\n+\t/* Allocate memory for Completion Head variable. */\n \tq->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,\n \t\t\tsizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);\n \tif (q->ring_head_addr == NULL) {\n-\t\t/* Mark queue as un-assigned */\n+\t\t/* Mark queue as un-assigned. */\n \t\td->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));\n \t\trte_free(q);\n \t\trte_bbdev_log(ERR,\n@@ -682,15 +682,15 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t\t\t\tdev->device->driver->name, dev->data->dev_id);\n \t\treturn -ENOMEM;\n \t}\n-\t/* Set ring_head_addr */\n+\t/* Set ring_head_addr. */\n \tq->ring_ctrl_reg.ring_head_addr = rte_malloc_virt2iova(q->ring_head_addr);\n \n-\t/* Clear shadow_completion_head */\n+\t/* Clear shadow_completion_head. */\n \tq->shadow_completion_head = 0;\n \n-\t/* Set ring_size */\n+\t/* Set ring_size. */\n \tif (conf->queue_size > FPGA_5GNR_RING_MAX_SIZE) {\n-\t\t/* Mark queue as un-assigned */\n+\t\t/* Mark queue as un-assigned. */\n \t\td->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));\n \t\trte_free(q->ring_head_addr);\n \t\trte_free(q);\n@@ -703,34 +703,34 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tq->ring_ctrl_reg.ring_size = conf->queue_size;\n \n \t/* Set Miscellaneous FPGA 5GNR register. */\n-\t/* Max iteration number for TTI mitigation - todo */\n+\t/* TODO: Max iteration number for TTI mitigation. */\n \tq->ring_ctrl_reg.max_ul_dec = 0;\n-\t/* Enable max iteration number for TTI - todo */\n+\t/* TODO: Enable max iteration number for TTI. */\n \tq->ring_ctrl_reg.max_ul_dec_en = 0;\n \n-\t/* Enable the ring */\n+\t/* Enable the ring. */\n \tq->ring_ctrl_reg.enable = 1;\n \n-\t/* Set FPGA 5GNR head_point and tail registers */\n+\t/* Set FPGA 5GNR head_point and tail registers. */\n \tq->ring_ctrl_reg.head_point = q->tail = 0;\n \n-\t/* Set FPGA 5GNR shadow_tail register */\n+\t/* Set FPGA 5GNR shadow_tail register. */\n \tq->ring_ctrl_reg.shadow_tail = q->tail;\n \n-\t/* Calculates the ring offset for found queue */\n+\t/* Calculates the ring offset for found queue. */\n \tring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n \t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_idx);\n \n-\t/* Set FPGA 5GNR Ring Control Registers */\n+\t/* Set FPGA 5GNR Ring Control Registers. */\n \tfpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);\n \n-\t/* Store MMIO register of shadow_tail */\n+\t/* Store MMIO register of shadow_tail. */\n \taddress = ring_offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL;\n \tq->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);\n \n \tq->head_free_desc = q->tail;\n \n-\t/* Set wrap mask */\n+\t/* Set wrap mask. */\n \tq->sw_ring_wrap_mask = conf->queue_size - 1;\n \n \trte_bbdev_log_debug(\"Setup dev%u q%u: queue_idx=%u\",\n@@ -741,7 +741,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \trte_bbdev_log_debug(\"BBDEV queue[%d] set up for FPGA 5GNR queue[%d]\", queue_id, q_idx);\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\t/* Read FPGA Ring Control Registers after configuration*/\n+\t/* Read FPGA Ring Control Registers after configuration. */\n \tprint_ring_reg_debug_info(d->mmio_base, ring_offset);\n #endif\n \treturn 0;\n@@ -761,13 +761,13 @@ fpga_5gnr_queue_release(struct rte_bbdev *dev, uint16_t queue_id)\n \t\tmemset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg));\n \t\toffset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n \t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q->q_idx);\n-\t\t/* Disable queue */\n+\t\t/* Disable queue. */\n \t\tfpga_5gnr_reg_write_8(d->mmio_base,\n \t\t\t\toffset + FPGA_5GNR_FEC_RING_ENABLE, 0x00);\n-\t\t/* Clear queue registers */\n+\t\t/* Clear queue registers. */\n \t\tfpga_ring_reg_write(d->mmio_base, offset, ring_reg);\n \n-\t\t/* Mark the Queue as un-assigned */\n+\t\t/* Mark the Queue as un-assigned. */\n \t\td->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));\n \t\trte_free(q->ring_head_addr);\n \t\trte_free(q);\n@@ -798,14 +798,14 @@ fpga_5gnr_queue_start(struct rte_bbdev *dev, uint16_t queue_id)\n \tuint8_t enable = 0x01;\n \tuint16_t zero = 0x0000;\n \n-\t/* Clear queue head and tail variables */\n+\t/* Clear queue head and tail variables. */\n \tq->tail = q->head_free_desc = 0;\n \n-\t/* Clear FPGA 5GNR head_point and tail registers */\n+\t/* Clear FPGA 5GNR head_point and tail registers. */\n \tfpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, zero);\n \tfpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, zero);\n \n-\t/* Enable queue */\n+\t/* Enable queue. */\n \tfpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, enable);\n \n \trte_bbdev_log_debug(\"FPGA 5GNR Queue[%d] started\", queue_id);\n@@ -830,7 +830,7 @@ fpga_5gnr_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n \tuint8_t counter = 0;\n \tuint8_t timeout = FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US / FPGA_5GNR_TIMEOUT_CHECK_INTERVAL;\n \n-\t/* Set flush_queue_en bit to trigger queue flushing */\n+\t/* Set flush_queue_en bit to trigger queue flushing. */\n \tfpga_5gnr_reg_write_8(d->mmio_base,\n \t\t\toffset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload);\n \n@@ -848,7 +848,7 @@ fpga_5gnr_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n \t\tcounter++;\n \t}\n \n-\t/* Disable queue */\n+\t/* Disable queue. */\n \tpayload = 0x00;\n \tfpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload);\n \n@@ -882,7 +882,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg)\n \tuint16_t queue_id;\n \tuint8_t i;\n \n-\t/* Scan queue assigned to this device */\n+\t/* Scan queue assigned to this device. */\n \tfor (i = 0; i < d->total_num_queues; ++i) {\n \t\tq_idx = 1ULL << i;\n \t\tif (d->q_bound_bit_map & q_idx) {\n@@ -890,7 +890,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg)\n \t\t\tif (queue_id == (uint16_t) -1)\n \t\t\t\tcontinue;\n \n-\t\t\t/* Check if completion head was changed */\n+\t\t\t/* Check if completion head was changed. */\n \t\t\tq = dev->data->queues[queue_id].queue_private;\n \t\t\tring_head = *q->ring_head_addr;\n \t\t\tif (q->shadow_completion_head != ring_head &&\n@@ -1014,7 +1014,7 @@ fpga_5gnr_dma_enqueue(struct fpga_5gnr_queue *q, uint16_t num_desc,\n \tuint64_t start_time = 0;\n \tqueue_stats->acc_offload_cycles = 0;\n \n-\t/* Update tail and shadow_tail register */\n+\t/* Update tail and shadow_tail register. */\n \tq->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;\n \n \trte_wmb();\n@@ -1027,7 +1027,7 @@ fpga_5gnr_dma_enqueue(struct fpga_5gnr_queue *q, uint16_t num_desc,\n \tqueue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;\n }\n \n-/* Read flag value 0/1/ from bitmap */\n+/* Read flag value 0/1/ from bitmap. */\n static inline bool\n check_bit(uint32_t bitmap, uint32_t bitmask)\n {\n@@ -1171,7 +1171,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)\n \t\telse\n \t\t\treturn (bg == 1 ? K0_3_1 : K0_3_2) * z_c;\n \t}\n-\t/* LBRM case - includes a division by N */\n+\t/* LBRM case - includes a division by N. */\n \tif (rv_index == 1)\n \t\treturn (((bg == 1 ? K0_1_1 : K0_1_2) * n_cb)\n \t\t\t\t/ n) * z_c;\n@@ -1215,7 +1215,7 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n \t\tuint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,\n \t\tuint8_t cbs_in_op)\n {\n-\t/* reset */\n+\t/* reset. */\n \tdesc->done = 0;\n \tdesc->error = 0;\n \tdesc->k_ = k_;\n@@ -1231,7 +1231,7 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n \t\t\top->ldpc_enc.basegraph, op->ldpc_enc.rv_index);\n \tdesc->ncb = op->ldpc_enc.n_cb;\n \tdesc->num_null = op->ldpc_enc.n_filler;\n-\t/* Set inbound data buffer address */\n+\t/* Set inbound data buffer address. */\n \tdesc->in_addr_hi = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n@@ -1241,9 +1241,9 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n \t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(output, out_offset));\n-\t/* Save software context needed for dequeue */\n+\t/* Save software context needed for dequeue. */\n \tdesc->op_addr = op;\n-\t/* Set total number of CBs in an op */\n+\t/* Set total number of CBs in an op. */\n \tdesc->cbs_in_op = cbs_in_op;\n \treturn 0;\n }\n@@ -1280,7 +1280,7 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op,\n \t\tuint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,\n \t\tuint8_t cbs_in_op)\n {\n-\t/* reset */\n+\t/* reset. */\n \tdesc->done = 0;\n \tdesc->error_msg = 0;\n \tdesc->error_code = 0;\n@@ -1289,28 +1289,28 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op,\n \tdesc->qm_idx = op->ldpc_enc.q_m >> 1;\n \tdesc->zc = op->ldpc_enc.z_c;\n \tdesc->rv = op->ldpc_enc.rv_index;\n-\tdesc->int_en = 0;\t/**< Set by device externally*/\n-\tdesc->max_cbg = 0;\t/*TODO: CBG specific */\n-\tdesc->cbgti = 0;\t/*TODO: CBG specific */\n-\tdesc->cbgs = 0;\t\t/*TODO: CBG specific */\n+\tdesc->int_en = 0;\t/**< Set by device externally. */\n+\tdesc->max_cbg = 0;\t/**< TODO: CBG specific. */\n+\tdesc->cbgti = 0;\t/**< TODO: CBG specific. */\n+\tdesc->cbgs = 0;\t\t/**< TODO: CBG specific. */\n \tdesc->desc_idx = desc_offset;\n-\tdesc->ca = 0;\t/*TODO: CBG specific */\n-\tdesc->c = 0;\t/*TODO: CBG specific */\n+\tdesc->ca = 0;\t/**< TODO: CBG specific. */\n+\tdesc->c = 0;\t/**< TODO: CBG specific. */\n \tdesc->num_null = op->ldpc_enc.n_filler;\n \tdesc->ea = e;\n-\tdesc->eb = e;\t/*TODO: TB/CBG specific */\n+\tdesc->eb = e;\t/**< TODO: TB/CBG specific. */\n \tdesc->k_ = k_;\n-\tdesc->en_slice_ts = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_host_ts = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_cb_wr_status = 0;\t/*TODO: Event Queue specific*/\n-\tdesc->en_output_sg = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_input_sg = 0;\t/*TODO: Slice specific*/\n-\tdesc->tb_cb = 0;\t/*Descriptor for CB. TODO: Add TB and CBG logic*/\n+\tdesc->en_slice_ts = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_host_ts = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_cb_wr_status = 0;\t/**< TODO: Event Queue specific. */\n+\tdesc->en_output_sg = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_input_sg = 0;\t/**< TODO: Slice specific. */\n+\tdesc->tb_cb = 0;\t/**< Descriptor for CB. TODO: Add TB and CBG logic. */\n \tdesc->crc_en = check_bit(op->ldpc_enc.op_flags,\n \t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH);\n \n-\t/* Set inbound/outbound data buffer address */\n-\t/* TODO: add logic for input_slice */\n+\t/* Set inbound/outbound data buffer address. */\n+\t/* TODO: add logic for input_slice. */\n \tdesc->output_start_addr_hi = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->output_start_addr_lo = (uint32_t)(\n@@ -1319,13 +1319,13 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op,\n \t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->input_start_addr_lo = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(input, in_offset));\n-\tdesc->output_length = (e + 7) >> 3; /* in bytes */\n+\tdesc->output_length = (e + 7) >> 3; /* in bytes. */\n \tdesc->input_length = input->data_len;\n \tdesc->enqueue_timestamp = 0;\n \tdesc->completion_timestamp = 0;\n-\t/* Save software context needed for dequeue */\n+\t/* Save software context needed for dequeue. */\n \tdesc->op_addr = op;\n-\t/* Set total number of CBs in an op */\n+\t/* Set total number of CBs in an op. */\n \tdesc->cbs_in_op = cbs_in_op;\n \treturn 0;\n }\n@@ -1359,10 +1359,10 @@ vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\tuint16_t desc_offset,\n \t\tuint8_t cbs_in_op)\n {\n-\t/* reset */\n+\t/* reset. */\n \tdesc->done = 0;\n \tdesc->error = 0;\n-\t/* Set inbound data buffer address */\n+\t/* Set inbound data buffer address. */\n \tdesc->in_addr_hi = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n@@ -1390,9 +1390,9 @@ vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(output, out_offset));\n-\t/* Save software context needed for dequeue */\n+\t/* Save software context needed for dequeue. */\n \tdesc->op_addr = op;\n-\t/* Set total number of CBs in an op */\n+\t/* Set total number of CBs in an op. */\n \tdesc->cbs_in_op = cbs_in_op;\n \n \treturn 0;\n@@ -1428,13 +1428,13 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\tuint16_t desc_offset,\n \t\tuint8_t cbs_in_op)\n {\n-\t/* reset */\n+\t/* reset. */\n \tdesc->done = 0;\n \tdesc->tb_crc_pass = 0;\n \tdesc->cb_crc_all_pass = 0;\n \tdesc->cb_all_et_pass = 0;\n \tdesc->max_iter_ret = 0;\n-\tdesc->cgb_crc_bitmap = 0;\t/*TODO: CBG specific */\n+\tdesc->cgb_crc_bitmap = 0;\t/**< TODO: CBG specific. */\n \tdesc->error_msg = 0;\n \tdesc->error_code = 0;\n \tdesc->et_dis = !check_bit(op->ldpc_dec.op_flags,\n@@ -1447,36 +1447,36 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \tdesc->qm_idx = op->ldpc_dec.q_m >> 1;\n \tdesc->zc = op->ldpc_dec.z_c;\n \tdesc->rv = op->ldpc_dec.rv_index;\n-\tdesc->int_en = 0;\t/**< Set by device externally*/\n-\tdesc->max_cbg = 0;\t/*TODO: CBG specific*/\n-\tdesc->cbgti = 0;\t/*TODO: CBG specific*/\n-\tdesc->cbgfi = 0;\t/*TODO: CBG specific*/\n-\tdesc->cbgs = 0;\t\t/*TODO: CBG specific*/\n+\tdesc->int_en = 0;\t/**< Set by device externally. */\n+\tdesc->max_cbg = 0;\t/**< TODO: CBG specific. */\n+\tdesc->cbgti = 0;\t/**< TODO: CBG specific. */\n+\tdesc->cbgfi = 0;\t/**< TODO: CBG specific. */\n+\tdesc->cbgs = 0;\t\t/**< TODO: CBG specific. */\n \tdesc->desc_idx = desc_offset;\n-\tdesc->ca = 0;\t/*TODO: CBG specific*/\n-\tdesc->c = 0;\t\t/*TODO: CBG specific*/\n-\tdesc->llr_pckg = 0;\t\t/*TODO: Not implemented yet*/\n-\tdesc->syndrome_check_mode = 1;\t/*TODO: Make it configurable*/\n+\tdesc->ca = 0;\t/**< TODO: CBG specific. */\n+\tdesc->c = 0;\t\t/**< TODO: CBG specific. */\n+\tdesc->llr_pckg = 0;\t\t/**< TODO: Not implemented yet. */\n+\tdesc->syndrome_check_mode = 1;\t/**< TODO: Make it configurable. */\n \tdesc->num_null = op->ldpc_dec.n_filler;\n-\tdesc->ea = op->ldpc_dec.cb_params.e;\t/*TODO: TB/CBG specific*/\n-\tdesc->eba = 0;\t/*TODO: TB/CBG specific*/\n+\tdesc->ea = op->ldpc_dec.cb_params.e;\t/**< TODO: TB/CBG specific. */\n+\tdesc->eba = 0;\t/**< TODO: TB/CBG specific. */\n \tdesc->hbstore_offset_out = harq_out_offset >> 10;\n \tdesc->hbstore_offset_in = harq_in_offset >> 10;\n-\tdesc->en_slice_ts = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_host_ts = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_cb_wr_status = 0;\t/*TODO: Event Queue specific*/\n-\tdesc->en_output_sg = 0;\t/*TODO: Slice specific*/\n-\tdesc->en_input_sg = 0;\t/*TODO: Slice specific*/\n-\tdesc->tb_cb = 0; /* Descriptor for CB. TODO: Add TB and CBG logic*/\n+\tdesc->en_slice_ts = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_host_ts = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_cb_wr_status = 0;\t/**< TODO: Event Queue specific. */\n+\tdesc->en_output_sg = 0;\t/**< TODO: Slice specific. */\n+\tdesc->en_input_sg = 0;\t/**< TODO: Slice specific. */\n+\tdesc->tb_cb = 0; /**< Descriptor for CB. TODO: Add TB and CBG logic. */\n \tdesc->crc24b_ind = check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);\n \tdesc->drop_crc24b = check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_DROP);\n \tdesc->harq_input_length_a =\n-\t\t\tharq_in_length; /*Descriptor for CB. TODO: Add TB and CBG logic*/\n-\tdesc->harq_input_length_b = 0; /*Descriptor for CB. TODO: Add TB and CBG logic*/\n-\t/* Set inbound/outbound data buffer address */\n-\t/* TODO: add logic for input_slice */\n+\t\t\tharq_in_length; /**< Descriptor for CB. TODO: Add TB and CBG logic. */\n+\tdesc->harq_input_length_b = 0; /**< Descriptor for CB. TODO: Add TB and CBG logic. */\n+\t/* Set inbound/outbound data buffer address. */\n+\t/* TODO: add logic for input_slice. */\n \tdesc->output_start_addr_hi = (uint32_t)(\n \t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->output_start_addr_lo = (uint32_t)(\n@@ -1487,12 +1487,12 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \t\t\trte_pktmbuf_iova_offset(input, in_offset));\n \tdesc->output_length = (((op->ldpc_dec.basegraph == 1) ? 22 : 10) * op->ldpc_dec.z_c\n \t\t\t- op->ldpc_dec.n_filler - desc->drop_crc24b * 24) >> 3;\n-\tdesc->input_length = op->ldpc_dec.cb_params.e;\t/*TODO: TB/CBG specific*/\n+\tdesc->input_length = op->ldpc_dec.cb_params.e;\t/**< TODO: TB/CBG specific. */\n \tdesc->enqueue_timestamp = 0;\n \tdesc->completion_timestamp = 0;\n-\t/* Save software context needed for dequeue */\n+\t/* Save software context needed for dequeue. */\n \tdesc->op_addr = op;\n-\t/* Set total number of CBs in an op */\n+\t/* Set total number of CBs in an op. */\n \tdesc->cbs_in_op = cbs_in_op;\n \treturn 0;\n }\n@@ -1546,7 +1546,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t}\n \n \tz_c = ldpc_enc->z_c;\n-\t/* Check Zc is valid value */\n+\t/* Check Zc is valid value. */\n \tif ((z_c > 384) || (z_c < 4)) {\n \t\trte_bbdev_log(ERR, \"Zc (%u) is out of range\", z_c);\n \t\treturn -1;\n@@ -1602,7 +1602,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \n \t}\n \n-\t/* K' range check */\n+\t/* K' range check. */\n \tif (Kp % 8 > 0) {\n \t\trte_bbdev_log(ERR, \"K' not byte aligned %u\", Kp);\n \t\treturn -1;\n@@ -1619,23 +1619,23 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t\trte_bbdev_log(ERR, \"K - F invalid %u %u\", K, n_filler);\n \t\treturn -1;\n \t}\n-\t/* Ncb range check */\n+\t/* Ncb range check. */\n \tif ((n_cb > N) || (n_cb < 32) || (n_cb <= (Kp - crc24))) {\n \t\trte_bbdev_log(ERR, \"Ncb (%u) is out of range K  %d N %d\", n_cb, K, N);\n \t\treturn -1;\n \t}\n-\t/* Qm range check */\n+\t/* Qm range check. */\n \tif (!check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) &&\n \t\t\t((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) || (q_m > 8))) {\n \t\trte_bbdev_log(ERR, \"Qm (%u) is out of range\", q_m);\n \t\treturn -1;\n \t}\n-\t/* K0 range check */\n+\t/* K0 range check. */\n \tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) {\n \t\trte_bbdev_log(ERR, \"K0 (%u) is out of range\", k0);\n \t\treturn -1;\n \t}\n-\t/* E range check */\n+\t/* E range check. */\n \tif (e <= RTE_MAX(32, z_c)) {\n \t\trte_bbdev_log(ERR, \"E is too small %\"PRIu32\"\", e);\n \t\treturn -1;\n@@ -1650,7 +1650,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t\t\treturn -1;\n \t\t}\n \t}\n-\t/* Code word in RM range check */\n+\t/* Code word in RM range check. */\n \tif (k0 > (Kp - 2 * z_c))\n \t\tL = k0 + e;\n \telse\n@@ -1750,7 +1750,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t}\n \n \tz_c = ldpc_dec->z_c;\n-\t/* Check Zc is valid value */\n+\t/* Check Zc is valid value. */\n \tif ((z_c > 384) || (z_c < 4)) {\n \t\trte_bbdev_log(ERR, \"Zc (%u) is out of range\", z_c);\n \t\treturn -1;\n@@ -1799,7 +1799,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\trte_bbdev_log(ERR, \"TB mode not supported\");\n \t\treturn -1;\n \t}\n-\t/* Enforce HARQ input length */\n+\t/* Enforce HARQ input length. */\n \tldpc_dec->harq_combined_input.length = RTE_MIN((uint32_t) n_cb,\n \t\t\tldpc_dec->harq_combined_input.length);\n \tif ((ldpc_dec->harq_combined_input.length == 0) &&\n@@ -1816,7 +1816,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\tldpc_dec->harq_combined_input.length = 0;\n \t}\n \n-\t/* K' range check */\n+\t/* K' range check. */\n \tif (Kp % 8 > 0) {\n \t\trte_bbdev_log(ERR, \"K' not byte aligned %u\", Kp);\n \t\treturn -1;\n@@ -1833,12 +1833,12 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\trte_bbdev_log(ERR, \"K - F invalid %u %u\", K, n_filler);\n \t\treturn -1;\n \t}\n-\t/* Ncb range check */\n+\t/* Ncb range check. */\n \tif (n_cb != N) {\n \t\trte_bbdev_log(ERR, \"Ncb (%u) is out of range K  %d N %d\", n_cb, K, N);\n \t\treturn -1;\n \t}\n-\t/* Qm range check */\n+\t/* Qm range check. */\n \tif (!check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_INTERLEAVER_BYPASS) &&\n \t\t\t((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1))\n@@ -1846,12 +1846,12 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\trte_bbdev_log(ERR, \"Qm (%u) is out of range\", q_m);\n \t\treturn -1;\n \t}\n-\t/* K0 range check */\n+\t/* K0 range check. */\n \tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) {\n \t\trte_bbdev_log(ERR, \"K0 (%u) is out of range\", k0);\n \t\treturn -1;\n \t}\n-\t/* E range check */\n+\t/* E range check. */\n \tif (e <= RTE_MAX(32, z_c)) {\n \t\trte_bbdev_log(ERR, \"E is too small\");\n \t\treturn -1;\n@@ -1866,7 +1866,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\t\treturn -1;\n \t\t}\n \t}\n-\t/* Code word in RM range check */\n+\t/* Code word in RM range check. */\n \tif (k0 > (Kp - 2 * z_c))\n \t\tL = k0 + e;\n \telse\n@@ -1924,9 +1924,9 @@ static inline void\n fpga_5gnr_mutex_acquisition(struct fpga_5gnr_queue *q)\n {\n \tuint32_t mutex_ctrl, mutex_read, cnt = 0;\n-\t/* Assign a unique id for the duration of the DDR access */\n+\t/* Assign a unique id for the duration of the DDR access. */\n \tq->ddr_mutex_uuid = rand();\n-\t/* Request and wait for acquisition of the mutex */\n+\t/* Request and wait for acquisition of the mutex. */\n \tmutex_ctrl = (q->ddr_mutex_uuid << 16) + 1;\n \tdo {\n \t\tif (cnt > 0)\n@@ -2121,7 +2121,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \t\t}\n \t}\n \n-\t/* Clear op status */\n+\t/* Clear op status. */\n \top->status = 0;\n \n \tif (m_in == NULL || m_out == NULL) {\n@@ -2134,15 +2134,15 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \t\tcrc24_bits = 24;\n \n \tif (enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {\n-\t\t/* TODO: For Transport Block mode */\n+\t\t/* TODO: For Transport Block mode. */\n \t\trte_bbdev_log(ERR, \"Transport Block not supported yet\");\n \t\treturn -1;\n \t}\n-\t/* For Code Block mode */\n+\t/* For Code Block mode. */\n \tc = 1;\n \te = enc->cb_params.e;\n \n-\t/* Update total_left */\n+\t/* Update total_left. */\n \tK = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;\n \tk_ = K - enc->n_filler;\n \tin_length = (k_ - crc24_bits) >> 3;\n@@ -2150,7 +2150,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \n \ttotal_left = rte_pktmbuf_data_len(m_in) - in_offset;\n \n-\t/* Update offsets */\n+\t/* Update offsets. */\n \tif (total_left != in_length) {\n \t\top->status |= 1 << RTE_BBDEV_DATA_ERROR;\n \t\trte_bbdev_log(ERR,\n@@ -2160,16 +2160,16 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \n \tmbuf_append(m_out_head, m_out, out_length);\n \n-\t/* Offset into the ring */\n+\t/* Offset into the ring. */\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \n \tif (d->fpga_variant == VC_5GNR_FPGA_VARIANT) {\n-\t\t/* Setup DMA Descriptor */\n+\t\t/* Setup DMA Descriptor. */\n \t\tvc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset;\n \t\tret = vc_5gnr_dma_desc_te_fill(op, &vc_5gnr_desc->vc_5gnr_enc_req, m_in, m_out,\n \t\t\t\tk_, e, in_offset, out_offset, ring_offset, c);\n \t} else {\n-\t\t/* Setup DMA Descriptor */\n+\t\t/* Setup DMA Descriptor. */\n \t\tagx100_desc = q->agx100_ring_addr + ring_offset;\n \t\tret = agx100_dma_desc_le_fill(op, &agx100_desc->agx100_enc_req, m_in, m_out,\n \t\t\t\tk_, e, in_offset, out_offset, ring_offset, c);\n@@ -2178,7 +2178,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \tif (unlikely(ret < 0))\n \t\treturn ret;\n \n-\t/* Update lengths */\n+\t/* Update lengths. */\n \ttotal_left -= in_length;\n \top->ldpc_enc.output.length += out_length;\n \n@@ -2222,10 +2222,10 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d\n \t\treturn -EINVAL;\n \t}\n \n-\t/* Clear op status */\n+\t/* Clear op status. */\n \top->status = 0;\n \n-\t/* Setup DMA Descriptor */\n+\t/* Setup DMA Descriptor. */\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \tvc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset;\n \n@@ -2252,16 +2252,16 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d\n \t\t\tret = -1;\n \t\t}\n \n-\t\t/* Set descriptor for dequeue */\n+\t\t/* Set descriptor for dequeue. */\n \t\tvc_5gnr_desc->vc_5gnr_dec_req.done = 1;\n \t\tvc_5gnr_desc->vc_5gnr_dec_req.error = 0;\n \t\tvc_5gnr_desc->vc_5gnr_dec_req.op_addr = op;\n \t\tvc_5gnr_desc->vc_5gnr_dec_req.cbs_in_op = 1;\n \n-\t\t/* Mark this dummy descriptor to be dropped by HW */\n+\t\t/* Mark this dummy descriptor to be dropped by HW. */\n \t\tvc_5gnr_desc->vc_5gnr_dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask;\n \n-\t\treturn ret; /* Error or number of CB */\n+\t\treturn ret; /* Error or number of CB. */\n \t}\n \n \tif (m_in == NULL || m_out == NULL) {\n@@ -2316,7 +2316,7 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d\n \n \tif (unlikely(ret < 0))\n \t\treturn ret;\n-\t/* Update lengths */\n+\t/* Update lengths. */\n \tseg_total_left -= in_length;\n \top->ldpc_dec.hard_output.length += out_length;\n \tif (seg_total_left > 0) {\n@@ -2353,10 +2353,10 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de\n \tuint32_t harq_in_offset = 0;\n \tuint32_t harq_out_offset = 0;\n \n-\t/* Clear op status */\n+\t/* Clear op status. */\n \top->status = 0;\n \n-\t/* Setup DMA Descriptor */\n+\t/* Setup DMA Descriptor. */\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \tdesc = q->agx100_ring_addr + ring_offset;\n \n@@ -2382,17 +2382,17 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de\n \t\t\tret = -1;\n \t\t}\n \n-\t\t/* Set descriptor for dequeue */\n+\t\t/* Set descriptor for dequeue. */\n \t\tdesc->agx100_dec_req.done = 1;\n \t\tdesc->agx100_dec_req.error_code = 0;\n \t\tdesc->agx100_dec_req.error_msg = 0;\n \t\tdesc->agx100_dec_req.op_addr = op;\n \t\tdesc->agx100_dec_req.cbs_in_op = 1;\n \n-\t\t/* Mark this dummy descriptor to be dropped by HW */\n+\t\t/* Mark this dummy descriptor to be dropped by HW. */\n \t\tdesc->agx100_dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask;\n \n-\t\treturn ret; /* Error or number of CB */\n+\t\treturn ret; /* Error or number of CB. */\n \t}\n \n \tif (m_in == NULL || m_out == NULL) {\n@@ -2438,7 +2438,7 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de\n \n \tif (unlikely(ret < 0))\n \t\treturn ret;\n-\t/* Update lengths */\n+\t/* Update lengths. */\n \tseg_total_left -= in_length;\n \top->ldpc_dec.hard_output.length += out_length;\n \tif (seg_total_left > 0) {\n@@ -2467,11 +2467,11 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \tunion agx100_dma_desc *agx100_desc;\n \tstruct fpga_5gnr_fec_device *d = q->d;\n \n-\t/* Check if queue is not full */\n+\t/* Check if queue is not full. */\n \tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc))\n \t\treturn 0;\n \n-\t/* Calculates available space */\n+\t/* Calculates available space. */\n \tavail = (q->head_free_desc > q->tail) ?\n \t\tq->head_free_desc - q->tail - 1 :\n \t\tq->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;\n@@ -2510,7 +2510,7 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \n \tfpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n \n-\t/* Update stats */\n+\t/* Update stats. */\n \tq_data->queue_stats.enqueued_count += i;\n \tq_data->queue_stats.enqueue_err_count += num - i;\n \n@@ -2529,11 +2529,11 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \tunion agx100_dma_desc *agx100_desc;\n \tstruct fpga_5gnr_fec_device *d = q->d;\n \n-\t/* Check if queue is not full */\n+\t/* Check if queue is not full. */\n \tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc))\n \t\treturn 0;\n \n-\t/* Calculates available space */\n+\t/* Calculates available space. */\n \tavail = (q->head_free_desc > q->tail) ?\n \t\tq->head_free_desc - q->tail - 1 :\n \t\tq->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;\n@@ -2564,7 +2564,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\t\t\tq->head_free_desc, q->tail);\n \t}\n \n-\t/* Update stats */\n+\t/* Update stats. */\n \tq_data->queue_stats.enqueued_count += i;\n \tq_data->queue_stats.enqueue_err_count += num - i;\n \n@@ -2592,14 +2592,14 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_e\n {\n \tunion vc_5gnr_dma_desc *desc;\n \tint desc_error;\n-\t/* Set current desc */\n+\t/* Set current desc. */\n \tdesc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n \n-\t/*check if done */\n+\t/*check if done. */\n \tif (desc->vc_5gnr_enc_req.done == 0)\n \t\treturn -1;\n \n-\t/* make sure the response is read atomically */\n+\t/* make sure the response is read atomically. */\n \trte_smp_rmb();\n \n \trte_bbdev_log_debug(\"DMA response desc %p\", desc);\n@@ -2608,7 +2608,7 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_e\n \tvc_5gnr_print_dma_enc_desc_debug_info(desc);\n #endif\n \t*op = desc->vc_5gnr_enc_req.op_addr;\n-\t/* Check the descriptor error field, return 1 on error */\n+\t/* Check the descriptor error field, return 1 on error. */\n \tdesc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_enc_req.error);\n \t(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;\n \n@@ -2622,13 +2622,13 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_en\n \tunion agx100_dma_desc *desc;\n \tint desc_error;\n \n-\t/* Set current desc */\n+\t/* Set current desc. */\n \tdesc = q->agx100_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n-\t/*check if done */\n+\t/*check if done. */\n \tif (desc->agx100_enc_req.done == 0)\n \t\treturn -1;\n \n-\t/* make sure the response is read atomically */\n+\t/* make sure the response is read atomically. */\n \trte_smp_rmb();\n \n \trte_bbdev_log_debug(\"DMA response desc %p\", desc);\n@@ -2637,7 +2637,7 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_en\n \tagx100_print_dma_enc_desc_debug_info(desc);\n #endif\n \t*op = desc->agx100_enc_req.op_addr;\n-\t/* Check the descriptor error field, return 1 on error */\n+\t/* Check the descriptor error field, return 1 on error. */\n \tdesc_error = agx100_check_desc_error(desc->agx100_enc_req.error_code,\n \t\t\tdesc->agx100_enc_req.error_msg);\n \n@@ -2653,14 +2653,14 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d\n \tunion vc_5gnr_dma_desc *desc;\n \tint desc_error;\n \n-\t/* Set descriptor */\n+\t/* Set descriptor. */\n \tdesc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n \n-\t/* Verify done bit is set */\n+\t/* Verify done bit is set. */\n \tif (desc->vc_5gnr_dec_req.done == 0)\n \t\treturn -1;\n \n-\t/* make sure the response is read atomically */\n+\t/* make sure the response is read atomically. */\n \trte_smp_rmb();\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n@@ -2675,17 +2675,17 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d\n \t\treturn 1;\n \t}\n \n-\t/* FPGA reports iterations based on round-up minus 1 */\n+\t/* FPGA reports iterations based on round-up minus 1. */\n \t(*op)->ldpc_dec.iter_count = desc->vc_5gnr_dec_req.iter + 1;\n \n-\t/* CRC Check criteria */\n+\t/* CRC Check criteria. */\n \tif (desc->vc_5gnr_dec_req.crc24b_ind && !(desc->vc_5gnr_dec_req.crcb_pass))\n \t\t(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;\n \n-\t/* et_pass = 0 when decoder fails */\n+\t/* et_pass = 0 when decoder fails. */\n \t(*op)->status |= !(desc->vc_5gnr_dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;\n \n-\t/* Check the descriptor error field, return 1 on error */\n+\t/* Check the descriptor error field, return 1 on error. */\n \tdesc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_dec_req.error);\n \n \t(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;\n@@ -2700,14 +2700,14 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de\n \tunion agx100_dma_desc *desc;\n \tint desc_error;\n \n-\t/* Set descriptor */\n+\t/* Set descriptor. */\n \tdesc = q->agx100_ring_addr +\n \t\t\t((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n-\t/* Verify done bit is set */\n+\t/* Verify done bit is set. */\n \tif (desc->agx100_dec_req.done == 0)\n \t\treturn -1;\n \n-\t/* make sure the response is read atomically */\n+\t/* make sure the response is read atomically. */\n \trte_smp_rmb();\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n@@ -2721,17 +2721,17 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de\n \t\treturn 1;\n \t}\n \n-\t/* FPGA reports iterations based on round-up minus 1 */\n+\t/* FPGA reports iterations based on round-up minus 1. */\n \t(*op)->ldpc_dec.iter_count = desc->agx100_dec_req.max_iter_ret + 1;\n \n-\t/* CRC Check criteria */\n+\t/* CRC Check criteria. */\n \tif (desc->agx100_dec_req.crc24b_ind && !(desc->agx100_dec_req.cb_crc_all_pass))\n \t\t(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;\n \n-\t/* et_pass = 0 when decoder fails */\n+\t/* et_pass = 0 when decoder fails. */\n \t(*op)->status |= !(desc->agx100_dec_req.cb_all_et_pass) << RTE_BBDEV_SYNDROME_ERROR;\n \n-\t/* Check the descriptor error field, return 1 on error */\n+\t/* Check the descriptor error field, return 1 on error. */\n \tdesc_error = agx100_check_desc_error(desc->agx100_dec_req.error_code,\n \t\t\tdesc->agx100_dec_req.error_msg);\n \n@@ -2764,11 +2764,11 @@ fpga_5gnr_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\t\t\tdequeued_cbs, num, q->head_free_desc, q->tail);\n \t}\n \n-\t/* Update head */\n+\t/* Update head. */\n \tq->head_free_desc = (q->head_free_desc + dequeued_cbs) &\n \t\t\tq->sw_ring_wrap_mask;\n \n-\t/* Update stats */\n+\t/* Update stats. */\n \tq_data->queue_stats.dequeued_count += i;\n \n \treturn i;\n@@ -2799,17 +2799,17 @@ fpga_5gnr_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\t\t\tdequeued_cbs, num, q->head_free_desc, q->tail);\n \t}\n \n-\t/* Update head */\n+\t/* Update head. */\n \tq->head_free_desc = (q->head_free_desc + dequeued_cbs) & q->sw_ring_wrap_mask;\n \n-\t/* Update stats */\n+\t/* Update stats. */\n \tq_data->queue_stats.dequeued_count += i;\n \n \treturn i;\n }\n \n \n-/* Initialization Function */\n+/* Initialization Function. */\n static void\n fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n {\n@@ -2821,7 +2821,7 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \tdev->dequeue_ldpc_enc_ops = fpga_5gnr_dequeue_ldpc_enc;\n \tdev->dequeue_ldpc_dec_ops = fpga_5gnr_dequeue_ldpc_dec;\n \n-\t/* Device variant specific handling */\n+\t/* Device variant specific handling. */\n \tif ((pci_dev->id.device_id == AGX100_PF_DEVICE_ID) ||\n \t\t\t(pci_dev->id.device_id == AGX100_VF_DEVICE_ID)) {\n \t\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->fpga_variant =\n@@ -2830,7 +2830,7 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \t\t\t\t!strcmp(drv->driver.name, RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));\n \t\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =\n \t\t\t\tpci_dev->mem_resource[0].addr;\n-\t\t/* Maximum number of queues possible for this device */\n+\t\t/* Maximum number of queues possible for this device. */\n \t\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->total_num_queues =\n \t\t\t\tfpga_5gnr_reg_read_32(pci_dev->mem_resource[0].addr,\n \t\t\t\tFPGA_5GNR_FEC_VERSION_ID) >> 24;\n@@ -2867,12 +2867,12 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,\n \n \trte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));\n \n-\t/* Allocate memory to be used privately by drivers */\n+\t/* Allocate memory to be used privately by drivers. */\n \tbbdev = rte_bbdev_allocate(pci_dev->device.name);\n \tif (bbdev == NULL)\n \t\treturn -ENODEV;\n \n-\t/* allocate device private memory */\n+\t/* allocate device private memory. */\n \tbbdev->data->dev_private = rte_zmalloc_socket(dev_name,\n \t\t\tsizeof(struct fpga_5gnr_fec_device),\n \t\t\tRTE_CACHE_LINE_SIZE,\n@@ -2886,12 +2886,12 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,\n \t\t\treturn -ENOMEM;\n \t}\n \n-\t/* Fill HW specific part of device structure */\n+\t/* Fill HW specific part of device structure. */\n \tbbdev->device = &pci_dev->device;\n \tbbdev->intr_handle = pci_dev->intr_handle;\n \tbbdev->data->socket_id = pci_dev->device.numa_node;\n \n-\t/* Invoke FPGA 5GNR FEC device initialization function */\n+\t/* Invoke FPGA 5GNR FEC device initialization function. */\n \tfpga_5gnr_fec_init(bbdev, pci_drv);\n \n \trte_bbdev_log_debug(\"bbdev id = %u [%s]\",\n@@ -2929,7 +2929,7 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n \tif (pci_dev == NULL)\n \t\treturn -EINVAL;\n \n-\t/* Find device */\n+\t/* Find device. */\n \tbbdev = rte_bbdev_get_named_dev(pci_dev->device.name);\n \tif (bbdev == NULL) {\n \t\trte_bbdev_log(CRIT,\n@@ -2939,17 +2939,17 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n \t}\n \tdev_id = bbdev->data->dev_id;\n \n-\t/* free device private memory before close */\n+\t/* free device private memory before close. */\n \trte_free(bbdev->data->dev_private);\n \n-\t/* Close device */\n+\t/* Close device. */\n \tret = rte_bbdev_close(dev_id);\n \tif (ret < 0)\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Device %i failed to close during uninit: %i\",\n \t\t\t\tdev_id, ret);\n \n-\t/* release bbdev from library */\n+\t/* release bbdev from library. */\n \tret = rte_bbdev_release(bbdev);\n \tif (ret)\n \t\trte_bbdev_log(ERR, \"Device %i failed to uninit: %i\", dev_id, ret);\n@@ -2962,16 +2962,16 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n static inline void\n fpga_5gnr_set_default_conf(struct rte_fpga_5gnr_fec_conf *def_conf)\n {\n-\t/* clear default configuration before initialization */\n+\t/* clear default configuration before initialization. */\n \tmemset(def_conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));\n-\t/* Set pf mode to true */\n+\t/* Set pf mode to true. */\n \tdef_conf->pf_mode_en = true;\n \n \t/* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */\n \tdef_conf->ul_bandwidth = 3;\n \tdef_conf->dl_bandwidth = 3;\n \n-\t/* Set Load Balance Factor to 64 */\n+\t/* Set Load Balance Factor to 64. */\n \tdef_conf->dl_load_balance = 64;\n \tdef_conf->ul_load_balance = 64;\n }\n@@ -3011,7 +3011,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \taddress = VC_5GNR_CONFIGURATION;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n-\t/* Clear all queues registers */\n+\t/* Clear all queues registers. */\n \tpayload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID;\n \tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\taddress = (q_id << 2) + VC_5GNR_QUEUE_MAP;\n@@ -3079,7 +3079,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t\t}\n \t} else {\n-\t\t/* Calculate total number of UL and DL queues to configure */\n+\t\t/* Calculate total number of UL and DL queues to configure. */\n \t\ttotal_ul_q_id = total_dl_q_id = 0;\n \t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n \t\t\ttotal_ul_q_id += conf->vf_ul_queues_number[vf_id];\n@@ -3122,17 +3122,17 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \t\t}\n \t}\n \n-\t/* Setting Load Balance Factor */\n+\t/* Setting Load Balance Factor. */\n \tpayload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);\n \taddress = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n-\t/* Setting length of ring descriptor entry */\n+\t/* Setting length of ring descriptor entry. */\n \tpayload_16 = FPGA_5GNR_RING_DESC_ENTRY_LENGTH;\n \taddress = FPGA_5GNR_FEC_RING_DESC_LEN;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n-\t/* Queue PF/VF mapping table is ready */\n+\t/* Queue PF/VF mapping table is ready. */\n \tpayload_8 = 0x1;\n \taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n \tfpga_5gnr_reg_write_8(d->mmio_base, address, payload_8);\n@@ -3145,7 +3145,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \treturn 0;\n }\n \n-/* Initial configuration of AGX100 device */\n+/* Initial configuration of AGX100 device. */\n static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf)\n {\n \tuint32_t payload_32, address;\n@@ -3175,7 +3175,7 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec\n \tuint8_t num_ul_queues = total_num_queues >> 1;\n \tuint8_t num_dl_queues = total_num_queues >> 1;\n \n-\t/* Clear all queues registers */\n+\t/* Clear all queues registers. */\n \tpayload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID;\n \tfor (q_id = 0; q_id < total_num_queues; ++q_id) {\n \t\taddress = (q_id << 2) + AGX100_QUEUE_MAP;\n@@ -3243,7 +3243,7 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec\n \t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t\t}\n \t} else {\n-\t\t/* Calculate total number of UL and DL queues to configure */\n+\t\t/* Calculate total number of UL and DL queues to configure. */\n \t\ttotal_ul_q_id = total_dl_q_id = 0;\n \t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n \t\t\ttotal_ul_q_id += conf->vf_ul_queues_number[vf_id];\n@@ -3284,17 +3284,17 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec\n \t\t}\n \t}\n \n-\t/* Setting Load Balance Factor */\n+\t/* Setting Load Balance Factor. */\n \tpayload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);\n \taddress = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n-\t/* Setting length of ring descriptor entry */\n+\t/* Setting length of ring descriptor entry. */\n \tpayload_16 = FPGA_5GNR_RING_DESC_ENTRY_LENGTH;\n \taddress = FPGA_5GNR_FEC_RING_DESC_LEN;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n-\t/* Queue PF/VF mapping table is ready */\n+\t/* Queue PF/VF mapping table is ready. */\n \tpayload_8 = 0x1;\n \taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n \tfpga_5gnr_reg_write_8(d->mmio_base, address, payload_8);\n@@ -3326,7 +3326,7 @@ int rte_fpga_5gnr_fec_configure(const char *dev_name, const struct rte_fpga_5gnr\n \treturn -ENODEV;\n }\n \n-/* FPGA 5GNR FEC PCI PF address map */\n+/* FPGA 5GNR FEC PCI PF address map. */\n static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {\n \t{\n \t\tRTE_PCI_DEVICE(AGX100_VENDOR_ID, AGX100_PF_DEVICE_ID)\n@@ -3344,7 +3344,7 @@ static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {\n \t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n };\n \n-/* FPGA 5GNR FEC PCI VF address map */\n+/* FPGA 5GNR FEC PCI VF address map. */\n static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {\n \t{\n \t\tRTE_PCI_DEVICE(AGX100_VENDOR_ID, AGX100_VF_DEVICE_ID)\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\nindex 894c218a5f7d..2bf87c197f54 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h\n@@ -25,26 +25,26 @@\n extern \"C\" {\n #endif\n \n-/** Number of Virtual Functions FPGA 5GNR FEC supports */\n+/** Number of Virtual Functions FPGA 5GNR FEC supports. */\n #define FPGA_5GNR_FEC_NUM_VFS 8\n \n /**\n  * Structure to pass FPGA 5GNR FEC configuration.\n  */\n struct rte_fpga_5gnr_fec_conf {\n-\t/** 1 if PF is used for dataplane, 0 for VFs */\n+\t/** 1 if PF is used for dataplane, 0 for VFs. */\n \tbool pf_mode_en;\n-\t/** Number of UL queues per VF */\n+\t/** Number of UL queues per VF. */\n \tuint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n-\t/** Number of DL queues per VF */\n+\t/** Number of DL queues per VF. */\n \tuint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];\n-\t/** UL bandwidth. Needed only for VC schedule algorithm */\n+\t/** UL bandwidth. Needed only for VC schedule algorithm. */\n \tuint8_t ul_bandwidth;\n-\t/** DL bandwidth. Needed only for VC schedule algorithm */\n+\t/** DL bandwidth. Needed only for VC schedule algorithm. */\n \tuint8_t dl_bandwidth;\n-\t/** UL Load Balance */\n+\t/** UL Load Balance. */\n \tuint8_t ul_load_balance;\n-\t/** DL Load Balance */\n+\t/** DL Load Balance. */\n \tuint8_t dl_load_balance;\n };\n \n",
    "prefixes": [
        "v1",
        "6/6"
    ]
}