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GET /api/patches/126895/?format=api
{ "id": 126895, "url": "http://patches.dpdk.org/api/patches/126895/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230516152422.606617-4-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230516152422.606617-4-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230516152422.606617-4-ciara.power@intel.com", "date": "2023-05-16T15:24:17", "name": "[v2,3/8] crypto/ipsec_mb: use new SGL API", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "220d753000f64172a2c93204895c4789527ed9ff", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230516152422.606617-4-ciara.power@intel.com/mbox/", "series": [ { "id": 28014, "url": "http://patches.dpdk.org/api/series/28014/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28014", "date": "2023-05-16T15:24:14", "name": "add AESNI_MB optimisations", "version": 2, "mbox": "http://patches.dpdk.org/series/28014/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126895/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126895/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C24142B24;\n\tTue, 16 May 2023 17:24:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E8B5642D39;\n\tTue, 16 May 2023 17:24:33 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 4347342D29\n for <dev@dpdk.org>; Tue, 16 May 2023 17:24:31 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 May 2023 08:24:30 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.80])\n by orsmga007.jf.intel.com with ESMTP; 16 May 2023 08:24:29 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684250671; x=1715786671;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=A7LBtgyDcv5HuHJ0NgyFUyDfmeHE2CrW8vtwvyQ0Nfc=;\n b=Elrzsly+M6qgspBZTS6dlDisMlR/BvnFyZ8M4hEmDnTFg4Y3buTHiFmX\n HIqANt3GVNFO99oI5GRq+aAaQFj0dkCBTr69RHInRw42jNr+gftbi2YqR\n kTMsoMJ3yMb2UKhVcyal9jLFY4VNPDFYl5b95EsTQ5Mc5SZ2EajgMTNqb\n DIKVhsChbhTNwH4yyejznXYlglmvg1/HGuDjxRTPr4UrAqAnR5WBvPJoM\n baOg71oC0R9ABdRhZ2ilmU6tQ6FX43JMcFBL8jfdjoPlgzBaGQY1jGbZo\n cV4YaDso3HYQeh2SAaFCowlfYcRCv30ppAHg3DupkK/NF4rSgK0CW1y4v Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10712\"; a=\"353789089\"", "E=Sophos;i=\"5.99,278,1677571200\"; d=\"scan'208\";a=\"353789089\"", "E=McAfee;i=\"6600,9927,10712\"; a=\"695500665\"", "E=Sophos;i=\"5.99,278,1677571200\"; d=\"scan'208\";a=\"695500665\"" ], "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "kai.ji@intel.com, gakhil@marvell.com,\n Pablo de Lara <pablo.de.lara.guarch@intel.com>,\n Ciara Power <ciara.power@intel.com>", "Subject": "[PATCH v2 3/8] crypto/ipsec_mb: use new SGL API", "Date": "Tue, 16 May 2023 15:24:17 +0000", "Message-Id": "<20230516152422.606617-4-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230516152422.606617-1-ciara.power@intel.com>", "References": "<20230421131221.1732314-1-ciara.power@intel.com>\n <20230516152422.606617-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pablo de Lara <pablo.de.lara.guarch@intel.com>\n\nUse new SGL API available from IPSec Multi-buffer v1.3,\nwhere only one function call is required to submit\nall segments to be processed in an SGL scenario.\nInstead of having one call per segment, there is only\none call per buffer.\n\nSigned-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 187 +++++++++++++++-----\n drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 7 +\n 2 files changed, 153 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c\nindex b22c0183eb..ef1f141cad 100644\n--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c\n+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c\n@@ -1241,6 +1241,141 @@ imb_lib_support_sgl_algo(IMB_CIPHER_MODE alg)\n \treturn 0;\n }\n \n+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM\n+static inline int\n+single_sgl_job(IMB_JOB *job, struct rte_crypto_op *op,\n+\t\tint oop, uint32_t offset, struct rte_mbuf *m_src,\n+\t\tstruct rte_mbuf *m_dst, struct IMB_SGL_IOV *sgl_segs)\n+{\n+\tuint32_t num_segs = 0;\n+\tstruct aesni_mb_op_buf_data src_sgl = {0};\n+\tstruct aesni_mb_op_buf_data dst_sgl = {0};\n+\tuint32_t total_len;\n+\n+\tjob->sgl_state = IMB_SGL_ALL;\n+\n+\tsrc_sgl.m = m_src;\n+\tsrc_sgl.offset = offset;\n+\n+\twhile (src_sgl.offset >= src_sgl.m->data_len) {\n+\t\tsrc_sgl.offset -= src_sgl.m->data_len;\n+\t\tsrc_sgl.m = src_sgl.m->next;\n+\n+\t\tRTE_ASSERT(src_sgl.m != NULL);\n+\t}\n+\n+\tif (oop) {\n+\t\tdst_sgl.m = m_dst;\n+\t\tdst_sgl.offset = offset;\n+\n+\t\twhile (dst_sgl.offset >= dst_sgl.m->data_len) {\n+\t\t\tdst_sgl.offset -= dst_sgl.m->data_len;\n+\t\t\tdst_sgl.m = dst_sgl.m->next;\n+\n+\t\t\tRTE_ASSERT(dst_sgl.m != NULL);\n+\t\t}\n+\t}\n+\ttotal_len = op->sym->aead.data.length;\n+\n+\twhile (total_len != 0) {\n+\t\tuint32_t data_len, part_len;\n+\n+\t\tif (src_sgl.m == NULL) {\n+\t\t\tIPSEC_MB_LOG(ERR, \"Invalid source buffer\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tdata_len = src_sgl.m->data_len - src_sgl.offset;\n+\n+\t\tsgl_segs[num_segs].in = rte_pktmbuf_mtod_offset(src_sgl.m, uint8_t *,\n+\t\t\t\tsrc_sgl.offset);\n+\n+\t\tif (dst_sgl.m != NULL) {\n+\t\t\tif (dst_sgl.m->data_len - dst_sgl.offset == 0) {\n+\t\t\t\tdst_sgl.m = dst_sgl.m->next;\n+\t\t\t\tif (dst_sgl.m == NULL) {\n+\t\t\t\t\tIPSEC_MB_LOG(ERR, \"Invalid destination buffer\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t\tdst_sgl.offset = 0;\n+\t\t\t}\n+\t\t\tpart_len = RTE_MIN(data_len, (dst_sgl.m->data_len -\n+\t\t\t\t\tdst_sgl.offset));\n+\t\t\tsgl_segs[num_segs].out = rte_pktmbuf_mtod_offset(dst_sgl.m,\n+\t\t\t\t\tuint8_t *, dst_sgl.offset);\n+\t\t\tdst_sgl.offset += part_len;\n+\t\t} else {\n+\t\t\tpart_len = RTE_MIN(data_len, total_len);\n+\t\t\tsgl_segs[num_segs].out = rte_pktmbuf_mtod_offset(src_sgl.m, uint8_t *,\n+\t\t\t\tsrc_sgl.offset);\n+\t\t}\n+\n+\t\tsgl_segs[num_segs].len = part_len;\n+\n+\t\ttotal_len -= part_len;\n+\n+\t\tif (part_len != data_len) {\n+\t\t\tsrc_sgl.offset += part_len;\n+\t\t} else {\n+\t\t\tsrc_sgl.m = src_sgl.m->next;\n+\t\t\tsrc_sgl.offset = 0;\n+\t\t}\n+\t\tnum_segs++;\n+\t}\n+\tjob->num_sgl_io_segs = num_segs;\n+\tjob->sgl_io_segs = sgl_segs;\n+\treturn 0;\n+}\n+#endif\n+\n+static inline int\n+multi_sgl_job(IMB_JOB *job, struct rte_crypto_op *op,\n+\t\tint oop, uint32_t offset, struct rte_mbuf *m_src,\n+\t\tstruct rte_mbuf *m_dst, IMB_MGR *mb_mgr)\n+{\n+\tint ret;\n+\tIMB_JOB base_job;\n+\tstruct aesni_mb_op_buf_data src_sgl = {0};\n+\tstruct aesni_mb_op_buf_data dst_sgl = {0};\n+\tuint32_t total_len;\n+\n+\tbase_job = *job;\n+\tjob->sgl_state = IMB_SGL_INIT;\n+\tjob = IMB_SUBMIT_JOB(mb_mgr);\n+\ttotal_len = op->sym->aead.data.length;\n+\n+\tsrc_sgl.m = m_src;\n+\tsrc_sgl.offset = offset;\n+\n+\twhile (src_sgl.offset >= src_sgl.m->data_len) {\n+\t\tsrc_sgl.offset -= src_sgl.m->data_len;\n+\t\tsrc_sgl.m = src_sgl.m->next;\n+\n+\t\tRTE_ASSERT(src_sgl.m != NULL);\n+\t}\n+\n+\tif (oop) {\n+\t\tdst_sgl.m = m_dst;\n+\t\tdst_sgl.offset = offset;\n+\n+\t\twhile (dst_sgl.offset >= dst_sgl.m->data_len) {\n+\t\t\tdst_sgl.offset -= dst_sgl.m->data_len;\n+\t\t\tdst_sgl.m = dst_sgl.m->next;\n+\n+\t\t\tRTE_ASSERT(dst_sgl.m != NULL);\n+\t\t}\n+\t}\n+\n+\twhile (job->sgl_state != IMB_SGL_COMPLETE) {\n+\t\tjob = IMB_GET_NEXT_JOB(mb_mgr);\n+\t\t*job = base_job;\n+\t\tret = handle_aead_sgl_job(job, mb_mgr, &total_len,\n+\t\t\t&src_sgl, &dst_sgl);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n /**\n * Process a crypto operation and complete a IMB_JOB job structure for\n * submission to the multi buffer library for processing.\n@@ -1262,19 +1397,15 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,\n {\n \tstruct rte_mbuf *m_src = op->sym->m_src, *m_dst;\n \tstruct aesni_mb_qp_data *qp_data = ipsec_mb_get_qp_private_data(qp);\n-\tstruct aesni_mb_op_buf_data src_sgl = {0};\n-\tstruct aesni_mb_op_buf_data dst_sgl = {0};\n \tstruct aesni_mb_session *session;\n-\tuint32_t m_offset, oop;\n+\tuint32_t m_offset;\n+\tint oop;\n \tuint32_t auth_off_in_bytes;\n \tuint32_t ciph_off_in_bytes;\n \tuint32_t auth_len_in_bytes;\n \tuint32_t ciph_len_in_bytes;\n-\tuint32_t total_len;\n-\tIMB_JOB base_job;\n \tuint8_t sgl = 0;\n \tuint8_t lb_sgl = 0;\n-\tint ret;\n \n \tsession = ipsec_mb_get_session_private(qp, op);\n \tif (session == NULL) {\n@@ -1602,41 +1733,15 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,\n \t\tif (lb_sgl)\n \t\t\treturn handle_sgl_linear(job, op, m_offset, session);\n \n-\t\tbase_job = *job;\n-\t\tjob->sgl_state = IMB_SGL_INIT;\n-\t\tjob = IMB_SUBMIT_JOB(mb_mgr);\n-\t\ttotal_len = op->sym->aead.data.length;\n-\n-\t\tsrc_sgl.m = m_src;\n-\t\tsrc_sgl.offset = m_offset;\n-\n-\t\twhile (src_sgl.offset >= src_sgl.m->data_len) {\n-\t\t\tsrc_sgl.offset -= src_sgl.m->data_len;\n-\t\t\tsrc_sgl.m = src_sgl.m->next;\n-\n-\t\t\tRTE_ASSERT(src_sgl.m != NULL);\n-\t\t}\n-\n-\t\tif (oop) {\n-\t\t\tdst_sgl.m = m_dst;\n-\t\t\tdst_sgl.offset = m_offset;\n-\n-\t\t\twhile (dst_sgl.offset >= dst_sgl.m->data_len) {\n-\t\t\t\tdst_sgl.offset -= dst_sgl.m->data_len;\n-\t\t\t\tdst_sgl.m = dst_sgl.m->next;\n-\n-\t\t\t\tRTE_ASSERT(dst_sgl.m != NULL);\n-\t\t\t}\n-\t\t}\n-\n-\t\twhile (job->sgl_state != IMB_SGL_COMPLETE) {\n-\t\t\tjob = IMB_GET_NEXT_JOB(mb_mgr);\n-\t\t\t*job = base_job;\n-\t\t\tret = handle_aead_sgl_job(job, mb_mgr, &total_len,\n-\t\t\t\t&src_sgl, &dst_sgl);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t}\n+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM\n+\t\tif (m_src->nb_segs <= MAX_NUM_SEGS)\n+\t\t\treturn single_sgl_job(job, op, oop,\n+\t\t\t\t\tm_offset, m_src, m_dst,\n+\t\t\t\t\tqp_data->sgl_segs);\n+\t\telse\n+#endif\n+\t\t\treturn multi_sgl_job(job, op, oop,\n+\t\t\t\t\tm_offset, m_src, m_dst, mb_mgr);\n \t}\n \n \treturn 0;\ndiff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h\nindex 8a7c74f621..e17b53e4fe 100644\n--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h\n+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h\n@@ -20,6 +20,10 @@\n #define HMAC_IPAD_VALUE\t\t\t(0x36)\n #define HMAC_OPAD_VALUE\t\t\t(0x5C)\n \n+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM\n+#define MAX_NUM_SEGS 16\n+#endif\n+\n static const struct rte_cryptodev_capabilities aesni_mb_capabilities[] = {\n \t{\t/* MD5 HMAC */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n@@ -729,6 +733,9 @@ struct aesni_mb_qp_data {\n \t * by the driver when verifying a digest provided\n \t * by the user (using authentication verify operation)\n \t */\n+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM\n+\tstruct IMB_SGL_IOV sgl_segs[MAX_NUM_SEGS];\n+#endif\n \tunion {\n \t\tstruct gcm_context_data gcm_sgl_ctx;\n \t\tstruct chacha20_poly1305_context_data chacha_sgl_ctx;\n", "prefixes": [ "v2", "3/8" ] }